drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c

   1 /*
   2  * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <stdint.h>             /* for uint32_t */
   8 #include <mmio.h>
   9 #include "pfc_init_h3_v2.h"
  10 #include "rcar_def.h"
  11
  12 /* GPIO base address */
  13 #define GPIO_BASE               (0xE6050000U)
  14
  15 /* GPIO registers */
  16 #define GPIO_IOINTSEL0          (GPIO_BASE + 0x0000U)
  17 #define GPIO_INOUTSEL0          (GPIO_BASE + 0x0004U)
  18 #define GPIO_OUTDT0             (GPIO_BASE + 0x0008U)
  19 #define GPIO_INDT0              (GPIO_BASE + 0x000CU)
  20 #define GPIO_INTDT0             (GPIO_BASE + 0x0010U)
  21 #define GPIO_INTCLR0            (GPIO_BASE + 0x0014U)
  22 #define GPIO_INTMSK0            (GPIO_BASE + 0x0018U)
  23 #define GPIO_MSKCLR0            (GPIO_BASE + 0x001CU)
  24 #define GPIO_POSNEG0            (GPIO_BASE + 0x0020U)
  25 #define GPIO_EDGLEVEL0          (GPIO_BASE + 0x0024U)
  26 #define GPIO_FILONOFF0          (GPIO_BASE + 0x0028U)
  27 #define GPIO_INTMSKS0           (GPIO_BASE + 0x0038U)
  28 #define GPIO_MSKCLRS0           (GPIO_BASE + 0x003CU)
  29 #define GPIO_OUTDTSEL0          (GPIO_BASE + 0x0040U)
  30 #define GPIO_OUTDTH0            (GPIO_BASE + 0x0044U)
  31 #define GPIO_OUTDTL0            (GPIO_BASE + 0x0048U)
  32 #define GPIO_BOTHEDGE0          (GPIO_BASE + 0x004CU)
  33 #define GPIO_IOINTSEL1          (GPIO_BASE + 0x1000U)
  34 #define GPIO_INOUTSEL1          (GPIO_BASE + 0x1004U)
  35 #define GPIO_OUTDT1             (GPIO_BASE + 0x1008U)
  36 #define GPIO_INDT1              (GPIO_BASE + 0x100CU)
  37 #define GPIO_INTDT1             (GPIO_BASE + 0x1010U)
  38 #define GPIO_INTCLR1            (GPIO_BASE + 0x1014U)
  39 #define GPIO_INTMSK1            (GPIO_BASE + 0x1018U)
  40 #define GPIO_MSKCLR1            (GPIO_BASE + 0x101CU)
  41 #define GPIO_POSNEG1            (GPIO_BASE + 0x1020U)
  42 #define GPIO_EDGLEVEL1          (GPIO_BASE + 0x1024U)
  43 #define GPIO_FILONOFF1          (GPIO_BASE + 0x1028U)
  44 #define GPIO_INTMSKS1           (GPIO_BASE + 0x1038U)
  45 #define GPIO_MSKCLRS1           (GPIO_BASE + 0x103CU)
  46 #define GPIO_OUTDTSEL1          (GPIO_BASE + 0x1040U)
  47 #define GPIO_OUTDTH1            (GPIO_BASE + 0x1044U)
  48 #define GPIO_OUTDTL1            (GPIO_BASE + 0x1048U)
  49 #define GPIO_BOTHEDGE1          (GPIO_BASE + 0x104CU)
  50 #define GPIO_IOINTSEL2          (GPIO_BASE + 0x2000U)
  51 #define GPIO_INOUTSEL2          (GPIO_BASE + 0x2004U)
  52 #define GPIO_OUTDT2             (GPIO_BASE + 0x2008U)
  53 #define GPIO_INDT2              (GPIO_BASE + 0x200CU)
  54 #define GPIO_INTDT2             (GPIO_BASE + 0x2010U)
  55 #define GPIO_INTCLR2            (GPIO_BASE + 0x2014U)
  56 #define GPIO_INTMSK2            (GPIO_BASE + 0x2018U)
  57 #define GPIO_MSKCLR2            (GPIO_BASE + 0x201CU)
  58 #define GPIO_POSNEG2            (GPIO_BASE + 0x2020U)
  59 #define GPIO_EDGLEVEL2          (GPIO_BASE + 0x2024U)
  60 #define GPIO_FILONOFF2          (GPIO_BASE + 0x2028U)
  61 #define GPIO_INTMSKS2           (GPIO_BASE + 0x2038U)
  62 #define GPIO_MSKCLRS2           (GPIO_BASE + 0x203CU)
  63 #define GPIO_OUTDTSEL2          (GPIO_BASE + 0x2040U)
  64 #define GPIO_OUTDTH2            (GPIO_BASE + 0x2044U)
  65 #define GPIO_OUTDTL2            (GPIO_BASE + 0x2048U)
  66 #define GPIO_BOTHEDGE2          (GPIO_BASE + 0x204CU)
  67 #define GPIO_IOINTSEL3          (GPIO_BASE + 0x3000U)
  68 #define GPIO_INOUTSEL3          (GPIO_BASE + 0x3004U)
  69 #define GPIO_OUTDT3             (GPIO_BASE + 0x3008U)
  70 #define GPIO_INDT3              (GPIO_BASE + 0x300CU)
  71 #define GPIO_INTDT3             (GPIO_BASE + 0x3010U)
  72 #define GPIO_INTCLR3            (GPIO_BASE + 0x3014U)
  73 #define GPIO_INTMSK3            (GPIO_BASE + 0x3018U)
  74 #define GPIO_MSKCLR3            (GPIO_BASE + 0x301CU)
  75 #define GPIO_POSNEG3            (GPIO_BASE + 0x3020U)
  76 #define GPIO_EDGLEVEL3          (GPIO_BASE + 0x3024U)
  77 #define GPIO_FILONOFF3          (GPIO_BASE + 0x3028U)
  78 #define GPIO_INTMSKS3           (GPIO_BASE + 0x3038U)
  79 #define GPIO_MSKCLRS3           (GPIO_BASE + 0x303CU)
  80 #define GPIO_OUTDTSEL3          (GPIO_BASE + 0x3040U)
  81 #define GPIO_OUTDTH3            (GPIO_BASE + 0x3044U)
  82 #define GPIO_OUTDTL3            (GPIO_BASE + 0x3048U)
  83 #define GPIO_BOTHEDGE3          (GPIO_BASE + 0x304CU)
  84 #define GPIO_IOINTSEL4          (GPIO_BASE + 0x4000U)
  85 #define GPIO_INOUTSEL4          (GPIO_BASE + 0x4004U)
  86 #define GPIO_OUTDT4             (GPIO_BASE + 0x4008U)
  87 #define GPIO_INDT4              (GPIO_BASE + 0x400CU)
  88 #define GPIO_INTDT4             (GPIO_BASE + 0x4010U)
  89 #define GPIO_INTCLR4            (GPIO_BASE + 0x4014U)
  90 #define GPIO_INTMSK4            (GPIO_BASE + 0x4018U)
  91 #define GPIO_MSKCLR4            (GPIO_BASE + 0x401CU)
  92 #define GPIO_POSNEG4            (GPIO_BASE + 0x4020U)
  93 #define GPIO_EDGLEVEL4          (GPIO_BASE + 0x4024U)
  94 #define GPIO_FILONOFF4          (GPIO_BASE + 0x4028U)
  95 #define GPIO_INTMSKS4           (GPIO_BASE + 0x4038U)
  96 #define GPIO_MSKCLRS4           (GPIO_BASE + 0x403CU)
  97 #define GPIO_OUTDTSEL4          (GPIO_BASE + 0x4040U)
  98 #define GPIO_OUTDTH4            (GPIO_BASE + 0x4044U)
  99 #define GPIO_OUTDTL4            (GPIO_BASE + 0x4048U)
 100 #define GPIO_BOTHEDGE4          (GPIO_BASE + 0x404CU)
 101 #define GPIO_IOINTSEL5          (GPIO_BASE + 0x5000U)
 102 #define GPIO_INOUTSEL5          (GPIO_BASE + 0x5004U)
 103 #define GPIO_OUTDT5             (GPIO_BASE + 0x5008U)
 104 #define GPIO_INDT5              (GPIO_BASE + 0x500CU)
 105 #define GPIO_INTDT5             (GPIO_BASE + 0x5010U)
 106 #define GPIO_INTCLR5            (GPIO_BASE + 0x5014U)
 107 #define GPIO_INTMSK5            (GPIO_BASE + 0x5018U)
 108 #define GPIO_MSKCLR5            (GPIO_BASE + 0x501CU)
 109 #define GPIO_POSNEG5            (GPIO_BASE + 0x5020U)
 110 #define GPIO_EDGLEVEL5          (GPIO_BASE + 0x5024U)
 111 #define GPIO_FILONOFF5          (GPIO_BASE + 0x5028U)
 112 #define GPIO_INTMSKS5           (GPIO_BASE + 0x5038U)
 113 #define GPIO_MSKCLRS5           (GPIO_BASE + 0x503CU)
 114 #define GPIO_OUTDTSEL5          (GPIO_BASE + 0x5040U)
 115 #define GPIO_OUTDTH5            (GPIO_BASE + 0x5044U)
 116 #define GPIO_OUTDTL5            (GPIO_BASE + 0x5048U)
 117 #define GPIO_BOTHEDGE5          (GPIO_BASE + 0x504CU)
 118 #define GPIO_IOINTSEL6          (GPIO_BASE + 0x5400U)
 119 #define GPIO_INOUTSEL6          (GPIO_BASE + 0x5404U)
 120 #define GPIO_OUTDT6             (GPIO_BASE + 0x5408U)
 121 #define GPIO_INDT6              (GPIO_BASE + 0x540CU)
 122 #define GPIO_INTDT6             (GPIO_BASE + 0x5410U)
 123 #define GPIO_INTCLR6            (GPIO_BASE + 0x5414U)
 124 #define GPIO_INTMSK6            (GPIO_BASE + 0x5418U)
 125 #define GPIO_MSKCLR6            (GPIO_BASE + 0x541CU)
 126 #define GPIO_POSNEG6            (GPIO_BASE + 0x5420U)
 127 #define GPIO_EDGLEVEL6          (GPIO_BASE + 0x5424U)
 128 #define GPIO_FILONOFF6          (GPIO_BASE + 0x5428U)
 129 #define GPIO_INTMSKS6           (GPIO_BASE + 0x5438U)
 130 #define GPIO_MSKCLRS6           (GPIO_BASE + 0x543CU)
 131 #define GPIO_OUTDTSEL6          (GPIO_BASE + 0x5440U)
 132 #define GPIO_OUTDTH6            (GPIO_BASE + 0x5444U)
 133 #define GPIO_OUTDTL6            (GPIO_BASE + 0x5448U)
 134 #define GPIO_BOTHEDGE6          (GPIO_BASE + 0x544CU)
 135 #define GPIO_IOINTSEL7          (GPIO_BASE + 0x5800U)
 136 #define GPIO_INOUTSEL7          (GPIO_BASE + 0x5804U)
 137 #define GPIO_OUTDT7             (GPIO_BASE + 0x5808U)
 138 #define GPIO_INDT7              (GPIO_BASE + 0x580CU)
 139 #define GPIO_INTDT7             (GPIO_BASE + 0x5810U)
 140 #define GPIO_INTCLR7            (GPIO_BASE + 0x5814U)
 141 #define GPIO_INTMSK7            (GPIO_BASE + 0x5818U)
 142 #define GPIO_MSKCLR7            (GPIO_BASE + 0x581CU)
 143 #define GPIO_POSNEG7            (GPIO_BASE + 0x5820U)
 144 #define GPIO_EDGLEVEL7          (GPIO_BASE + 0x5824U)
 145 #define GPIO_FILONOFF7          (GPIO_BASE + 0x5828U)
 146 #define GPIO_INTMSKS7           (GPIO_BASE + 0x5838U)
 147 #define GPIO_MSKCLRS7           (GPIO_BASE + 0x583CU)
 148 #define GPIO_OUTDTSEL7          (GPIO_BASE + 0x5840U)
 149 #define GPIO_OUTDTH7            (GPIO_BASE + 0x5844U)
 150 #define GPIO_OUTDTL7            (GPIO_BASE + 0x5848U)
 151 #define GPIO_BOTHEDGE7          (GPIO_BASE + 0x584CU)
 152
 153 /* Pin functon base address */
 154 #define PFC_BASE                (0xE6060000U)
 155
 156 /* Pin functon registers */
 157 #define PFC_PMMR                (PFC_BASE + 0x0000U)
 158 #define PFC_GPSR0               (PFC_BASE + 0x0100U)
 159 #define PFC_GPSR1               (PFC_BASE + 0x0104U)
 160 #define PFC_GPSR2               (PFC_BASE + 0x0108U)
 161 #define PFC_GPSR3               (PFC_BASE + 0x010CU)
 162 #define PFC_GPSR4               (PFC_BASE + 0x0110U)
 163 #define PFC_GPSR5               (PFC_BASE + 0x0114U)
 164 #define PFC_GPSR6               (PFC_BASE + 0x0118U)
 165 #define PFC_GPSR7               (PFC_BASE + 0x011CU)
 166 #define PFC_IPSR0               (PFC_BASE + 0x0200U)
 167 #define PFC_IPSR1               (PFC_BASE + 0x0204U)
 168 #define PFC_IPSR2               (PFC_BASE + 0x0208U)
 169 #define PFC_IPSR3               (PFC_BASE + 0x020CU)
 170 #define PFC_IPSR4               (PFC_BASE + 0x0210U)
 171 #define PFC_IPSR5               (PFC_BASE + 0x0214U)
 172 #define PFC_IPSR6               (PFC_BASE + 0x0218U)
 173 #define PFC_IPSR7               (PFC_BASE + 0x021CU)
 174 #define PFC_IPSR8               (PFC_BASE + 0x0220U)
 175 #define PFC_IPSR9               (PFC_BASE + 0x0224U)
 176 #define PFC_IPSR10              (PFC_BASE + 0x0228U)
 177 #define PFC_IPSR11              (PFC_BASE + 0x022CU)
 178 #define PFC_IPSR12              (PFC_BASE + 0x0230U)
 179 #define PFC_IPSR13              (PFC_BASE + 0x0234U)
 180 #define PFC_IPSR14              (PFC_BASE + 0x0238U)
 181 #define PFC_IPSR15              (PFC_BASE + 0x023CU)
 182 #define PFC_IPSR16              (PFC_BASE + 0x0240U)
 183 #define PFC_IPSR17              (PFC_BASE + 0x0244U)
 184 #define PFC_IPSR18              (PFC_BASE + 0x0248U)
 185 #define PFC_DRVCTRL0            (PFC_BASE + 0x0300U)
 186 #define PFC_DRVCTRL1            (PFC_BASE + 0x0304U)
 187 #define PFC_DRVCTRL2            (PFC_BASE + 0x0308U)
 188 #define PFC_DRVCTRL3            (PFC_BASE + 0x030CU)
 189 #define PFC_DRVCTRL4            (PFC_BASE + 0x0310U)
 190 #define PFC_DRVCTRL5            (PFC_BASE + 0x0314U)
 191 #define PFC_DRVCTRL6            (PFC_BASE + 0x0318U)
 192 #define PFC_DRVCTRL7            (PFC_BASE + 0x031CU)
 193 #define PFC_DRVCTRL8            (PFC_BASE + 0x0320U)
 194 #define PFC_DRVCTRL9            (PFC_BASE + 0x0324U)
 195 #define PFC_DRVCTRL10           (PFC_BASE + 0x0328U)
 196 #define PFC_DRVCTRL11           (PFC_BASE + 0x032CU)
 197 #define PFC_DRVCTRL12           (PFC_BASE + 0x0330U)
 198 #define PFC_DRVCTRL13           (PFC_BASE + 0x0334U)
 199 #define PFC_DRVCTRL14           (PFC_BASE + 0x0338U)
 200 #define PFC_DRVCTRL15           (PFC_BASE + 0x033CU)
 201 #define PFC_DRVCTRL16           (PFC_BASE + 0x0340U)
 202 #define PFC_DRVCTRL17           (PFC_BASE + 0x0344U)
 203 #define PFC_DRVCTRL18           (PFC_BASE + 0x0348U)
 204 #define PFC_DRVCTRL19           (PFC_BASE + 0x034CU)
 205 #define PFC_DRVCTRL20           (PFC_BASE + 0x0350U)
 206 #define PFC_DRVCTRL21           (PFC_BASE + 0x0354U)
 207 #define PFC_DRVCTRL22           (PFC_BASE + 0x0358U)
 208 #define PFC_DRVCTRL23           (PFC_BASE + 0x035CU)
 209 #define PFC_DRVCTRL24           (PFC_BASE + 0x0360U)
 210 #define PFC_POCCTRL0            (PFC_BASE + 0x0380U)
 211 #define PFC_TDSELCTRL0          (PFC_BASE + 0x03C0U)
 212 #define PFC_IOCTRL              (PFC_BASE + 0x03E0U)
 213 #define PFC_TSREG               (PFC_BASE + 0x03E4U)
 214 #define PFC_PUEN0               (PFC_BASE + 0x0400U)
 215 #define PFC_PUEN1               (PFC_BASE + 0x0404U)
 216 #define PFC_PUEN2               (PFC_BASE + 0x0408U)
 217 #define PFC_PUEN3               (PFC_BASE + 0x040CU)
 218 #define PFC_PUEN4               (PFC_BASE + 0x0410U)
 219 #define PFC_PUEN5               (PFC_BASE + 0x0414U)
 220 #define PFC_PUEN6               (PFC_BASE + 0x0418U)
 221 #define PFC_PUD0                (PFC_BASE + 0x0440U)
 222 #define PFC_PUD1                (PFC_BASE + 0x0444U)
 223 #define PFC_PUD2                (PFC_BASE + 0x0448U)
 224 #define PFC_PUD3                (PFC_BASE + 0x044CU)
 225 #define PFC_PUD4                (PFC_BASE + 0x0450U)
 226 #define PFC_PUD5                (PFC_BASE + 0x0454U)
 227 #define PFC_PUD6                (PFC_BASE + 0x0458U)
 228 #define PFC_MOD_SEL0            (PFC_BASE + 0x0500U)
 229 #define PFC_MOD_SEL1            (PFC_BASE + 0x0504U)
 230 #define PFC_MOD_SEL2            (PFC_BASE + 0x0508U)
 231
 232 #define GPSR0_D15               ((uint32_t)1U << 15U)
 233 #define GPSR0_D14               ((uint32_t)1U << 14U)
 234 #define GPSR0_D13               ((uint32_t)1U << 13U)
 235 #define GPSR0_D12               ((uint32_t)1U << 12U)
 236 #define GPSR0_D11               ((uint32_t)1U << 11U)
 237 #define GPSR0_D10               ((uint32_t)1U << 10U)
 238 #define GPSR0_D9                ((uint32_t)1U << 9U)
 239 #define GPSR0_D8                ((uint32_t)1U << 8U)
 240 #define GPSR0_D7                ((uint32_t)1U << 7U)
 241 #define GPSR0_D6                ((uint32_t)1U << 6U)
 242 #define GPSR0_D5                ((uint32_t)1U << 5U)
 243 #define GPSR0_D4                ((uint32_t)1U << 4U)
 244 #define GPSR0_D3                ((uint32_t)1U << 3U)
 245 #define GPSR0_D2                ((uint32_t)1U << 2U)
 246 #define GPSR0_D1                ((uint32_t)1U << 1U)
 247 #define GPSR0_D0                ((uint32_t)1U << 0U)
 248 #define GPSR1_CLKOUT            ((uint32_t)1U << 28U)
 249 #define GPSR1_EX_WAIT0_A        ((uint32_t)1U << 27U)
 250 #define GPSR1_WE1               ((uint32_t)1U << 26U)
 251 #define GPSR1_WE0               ((uint32_t)1U << 25U)
 252 #define GPSR1_RD_WR             ((uint32_t)1U << 24U)
 253 #define GPSR1_RD                ((uint32_t)1U << 23U)
 254 #define GPSR1_BS                ((uint32_t)1U << 22U)
 255 #define GPSR1_CS1_A26           ((uint32_t)1U << 21U)
 256 #define GPSR1_CS0               ((uint32_t)1U << 20U)
 257 #define GPSR1_A19               ((uint32_t)1U << 19U)
 258 #define GPSR1_A18               ((uint32_t)1U << 18U)
 259 #define GPSR1_A17               ((uint32_t)1U << 17U)
 260 #define GPSR1_A16               ((uint32_t)1U << 16U)
 261 #define GPSR1_A15               ((uint32_t)1U << 15U)
 262 #define GPSR1_A14               ((uint32_t)1U << 14U)
 263 #define GPSR1_A13               ((uint32_t)1U << 13U)
 264 #define GPSR1_A12               ((uint32_t)1U << 12U)
 265 #define GPSR1_A11               ((uint32_t)1U << 11U)
 266 #define GPSR1_A10               ((uint32_t)1U << 10U)
 267 #define GPSR1_A9                ((uint32_t)1U << 9U)
 268 #define GPSR1_A8                ((uint32_t)1U << 8U)
 269 #define GPSR1_A7                ((uint32_t)1U << 7U)
 270 #define GPSR1_A6                ((uint32_t)1U << 6U)
 271 #define GPSR1_A5                ((uint32_t)1U << 5U)
 272 #define GPSR1_A4                ((uint32_t)1U << 4U)
 273 #define GPSR1_A3                ((uint32_t)1U << 3U)
 274 #define GPSR1_A2                ((uint32_t)1U << 2U)
 275 #define GPSR1_A1                ((uint32_t)1U << 1U)
 276 #define GPSR1_A0                ((uint32_t)1U << 0U)
 277 #define GPSR2_AVB_AVTP_CAPTURE_A        ((uint32_t)1U << 14U)
 278 #define GPSR2_AVB_AVTP_MATCH_A  ((uint32_t)1U << 13U)
 279 #define GPSR2_AVB_LINK          ((uint32_t)1U << 12U)
 280 #define GPSR2_AVB_PHY_INT       ((uint32_t)1U << 11U)
 281 #define GPSR2_AVB_MAGIC         ((uint32_t)1U << 10U)
 282 #define GPSR2_AVB_MDC           ((uint32_t)1U << 9U)
 283 #define GPSR2_PWM2_A            ((uint32_t)1U << 8U)
 284 #define GPSR2_PWM1_A            ((uint32_t)1U << 7U)
 285 #define GPSR2_PWM0              ((uint32_t)1U << 6U)
 286 #define GPSR2_IRQ5              ((uint32_t)1U << 5U)
 287 #define GPSR2_IRQ4              ((uint32_t)1U << 4U)
 288 #define GPSR2_IRQ3              ((uint32_t)1U << 3U)
 289 #define GPSR2_IRQ2              ((uint32_t)1U << 2U)
 290 #define GPSR2_IRQ1              ((uint32_t)1U << 1U)
 291 #define GPSR2_IRQ0              ((uint32_t)1U << 0U)
 292 #define GPSR3_SD1_WP            ((uint32_t)1U << 15U)
 293 #define GPSR3_SD1_CD            ((uint32_t)1U << 14U)
 294 #define GPSR3_SD0_WP            ((uint32_t)1U << 13U)
 295 #define GPSR3_SD0_CD            ((uint32_t)1U << 12U)
 296 #define GPSR3_SD1_DAT3          ((uint32_t)1U << 11U)
 297 #define GPSR3_SD1_DAT2          ((uint32_t)1U << 10U)
 298 #define GPSR3_SD1_DAT1          ((uint32_t)1U << 9U)
 299 #define GPSR3_SD1_DAT0          ((uint32_t)1U << 8U)
 300 #define GPSR3_SD1_CMD           ((uint32_t)1U << 7U)
 301 #define GPSR3_SD1_CLK           ((uint32_t)1U << 6U)
 302 #define GPSR3_SD0_DAT3          ((uint32_t)1U << 5U)
 303 #define GPSR3_SD0_DAT2          ((uint32_t)1U << 4U)
 304 #define GPSR3_SD0_DAT1          ((uint32_t)1U << 3U)
 305 #define GPSR3_SD0_DAT0          ((uint32_t)1U << 2U)
 306 #define GPSR3_SD0_CMD           ((uint32_t)1U << 1U)
 307 #define GPSR3_SD0_CLK           ((uint32_t)1U << 0U)
 308 #define GPSR4_SD3_DS            ((uint32_t)1U << 17U)
 309 #define GPSR4_SD3_DAT7          ((uint32_t)1U << 16U)
 310 #define GPSR4_SD3_DAT6          ((uint32_t)1U << 15U)
 311 #define GPSR4_SD3_DAT5          ((uint32_t)1U << 14U)
 312 #define GPSR4_SD3_DAT4          ((uint32_t)1U << 13U)
 313 #define GPSR4_SD3_DAT3          ((uint32_t)1U << 12U)
 314 #define GPSR4_SD3_DAT2          ((uint32_t)1U << 11U)
 315 #define GPSR4_SD3_DAT1          ((uint32_t)1U << 10U)
 316 #define GPSR4_SD3_DAT0          ((uint32_t)1U << 9U)
 317 #define GPSR4_SD3_CMD           ((uint32_t)1U << 8U)
 318 #define GPSR4_SD3_CLK           ((uint32_t)1U << 7U)
 319 #define GPSR4_SD2_DS            ((uint32_t)1U << 6U)
 320 #define GPSR4_SD2_DAT3          ((uint32_t)1U << 5U)
 321 #define GPSR4_SD2_DAT2          ((uint32_t)1U << 4U)
 322 #define GPSR4_SD2_DAT1          ((uint32_t)1U << 3U)
 323 #define GPSR4_SD2_DAT0          ((uint32_t)1U << 2U)
 324 #define GPSR4_SD2_CMD           ((uint32_t)1U << 1U)
 325 #define GPSR4_SD2_CLK           ((uint32_t)1U << 0U)
 326 #define GPSR5_MLB_DAT           ((uint32_t)1U << 25U)
 327 #define GPSR5_MLB_SIG           ((uint32_t)1U << 24U)
 328 #define GPSR5_MLB_CLK           ((uint32_t)1U << 23U)
 329 #define GPSR5_MSIOF0_RXD        ((uint32_t)1U << 22U)
 330 #define GPSR5_MSIOF0_SS2        ((uint32_t)1U << 21U)
 331 #define GPSR5_MSIOF0_TXD        ((uint32_t)1U << 20U)
 332 #define GPSR5_MSIOF0_SS1        ((uint32_t)1U << 19U)
 333 #define GPSR5_MSIOF0_SYNC       ((uint32_t)1U << 18U)
 334 #define GPSR5_MSIOF0_SCK        ((uint32_t)1U << 17U)
 335 #define GPSR5_HRTS0             ((uint32_t)1U << 16U)
 336 #define GPSR5_HCTS0             ((uint32_t)1U << 15U)
 337 #define GPSR5_HTX0              ((uint32_t)1U << 14U)
 338 #define GPSR5_HRX0              ((uint32_t)1U << 13U)
 339 #define GPSR5_HSCK0             ((uint32_t)1U << 12U)
 340 #define GPSR5_RX2_A             ((uint32_t)1U << 11U)
 341 #define GPSR5_TX2_A             ((uint32_t)1U << 10U)
 342 #define GPSR5_SCK2              ((uint32_t)1U << 9U)
 343 #define GPSR5_RTS1_TANS         ((uint32_t)1U << 8U)
 344 #define GPSR5_CTS1              ((uint32_t)1U << 7U)
 345 #define GPSR5_TX1_A             ((uint32_t)1U << 6U)
 346 #define GPSR5_RX1_A             ((uint32_t)1U << 5U)
 347 #define GPSR5_RTS0_TANS         ((uint32_t)1U << 4U)
 348 #define GPSR5_CTS0              ((uint32_t)1U << 3U)
 349 #define GPSR5_TX0               ((uint32_t)1U << 2U)
 350 #define GPSR5_RX0               ((uint32_t)1U << 1U)
 351 #define GPSR5_SCK0              ((uint32_t)1U << 0U)
 352 #define GPSR6_USB31_OVC         ((uint32_t)1U << 31U)
 353 #define GPSR6_USB31_PWEN        ((uint32_t)1U << 30U)
 354 #define GPSR6_USB30_OVC         ((uint32_t)1U << 29U)
 355 #define GPSR6_USB30_PWEN        ((uint32_t)1U << 28U)
 356 #define GPSR6_USB1_OVC          ((uint32_t)1U << 27U)
 357 #define GPSR6_USB1_PWEN         ((uint32_t)1U << 26U)
 358 #define GPSR6_USB0_OVC          ((uint32_t)1U << 25U)
 359 #define GPSR6_USB0_PWEN         ((uint32_t)1U << 24U)
 360 #define GPSR6_AUDIO_CLKB_B      ((uint32_t)1U << 23U)
 361 #define GPSR6_AUDIO_CLKA_A      ((uint32_t)1U << 22U)
 362 #define GPSR6_SSI_SDATA9_A      ((uint32_t)1U << 21U)
 363 #define GPSR6_SSI_SDATA8        ((uint32_t)1U << 20U)
 364 #define GPSR6_SSI_SDATA7        ((uint32_t)1U << 19U)
 365 #define GPSR6_SSI_WS78          ((uint32_t)1U << 18U)
 366 #define GPSR6_SSI_SCK78         ((uint32_t)1U << 17U)
 367 #define GPSR6_SSI_SDATA6        ((uint32_t)1U << 16U)
 368 #define GPSR6_SSI_WS6           ((uint32_t)1U << 15U)
 369 #define GPSR6_SSI_SCK6          ((uint32_t)1U << 14U)
 370 #define GPSR6_SSI_SDATA5        ((uint32_t)1U << 13U)
 371 #define GPSR6_SSI_WS5           ((uint32_t)1U << 12U)
 372 #define GPSR6_SSI_SCK5          ((uint32_t)1U << 11U)
 373 #define GPSR6_SSI_SDATA4        ((uint32_t)1U << 10U)
 374 #define GPSR6_SSI_WS4           ((uint32_t)1U << 9U)
 375 #define GPSR6_SSI_SCK4          ((uint32_t)1U << 8U)
 376 #define GPSR6_SSI_SDATA3        ((uint32_t)1U << 7U)
 377 #define GPSR6_SSI_WS34          ((uint32_t)1U << 6U)
 378 #define GPSR6_SSI_SCK34         ((uint32_t)1U << 5U)
 379 #define GPSR6_SSI_SDATA2_A      ((uint32_t)1U << 4U)
 380 #define GPSR6_SSI_SDATA1_A      ((uint32_t)1U << 3U)
 381 #define GPSR6_SSI_SDATA0        ((uint32_t)1U << 2U)
 382 #define GPSR6_SSI_WS0129        ((uint32_t)1U << 1U)
 383 #define GPSR6_SSI_SCK0129       ((uint32_t)1U << 0U)
 384 #define GPSR7_HDMI1_CEC         ((uint32_t)1U << 3U)
 385 #define GPSR7_HDMI0_CEC         ((uint32_t)1U << 2U)
 386 #define GPSR7_AVS2              ((uint32_t)1U << 1U)
 387 #define GPSR7_AVS1              ((uint32_t)1U << 0U)
 388
 389 #define IPSR_28_FUNC(x)         ((uint32_t)(x) << 28U)
 390 #define IPSR_24_FUNC(x)         ((uint32_t)(x) << 24U)
 391 #define IPSR_20_FUNC(x)         ((uint32_t)(x) << 20U)
 392 #define IPSR_16_FUNC(x)         ((uint32_t)(x) << 16U)
 393 #define IPSR_12_FUNC(x)         ((uint32_t)(x) << 12U)
 394 #define IPSR_8_FUNC(x)          ((uint32_t)(x) << 8U)
 395 #define IPSR_4_FUNC(x)          ((uint32_t)(x) << 4U)
 396 #define IPSR_0_FUNC(x)          ((uint32_t)(x) << 0U)
 397
 398 #define POC_SD3_DS_33V          ((uint32_t)1U << 29U)
 399 #define POC_SD3_DAT7_33V        ((uint32_t)1U << 28U)
 400 #define POC_SD3_DAT6_33V        ((uint32_t)1U << 27U)
 401 #define POC_SD3_DAT5_33V        ((uint32_t)1U << 26U)
 402 #define POC_SD3_DAT4_33V        ((uint32_t)1U << 25U)
 403 #define POC_SD3_DAT3_33V        ((uint32_t)1U << 24U)
 404 #define POC_SD3_DAT2_33V        ((uint32_t)1U << 23U)
 405 #define POC_SD3_DAT1_33V        ((uint32_t)1U << 22U)
 406 #define POC_SD3_DAT0_33V        ((uint32_t)1U << 21U)
 407 #define POC_SD3_CMD_33V         ((uint32_t)1U << 20U)
 408 #define POC_SD3_CLK_33V         ((uint32_t)1U << 19U)
 409 #define POC_SD2_DS_33V          ((uint32_t)1U << 18U)
 410 #define POC_SD2_DAT3_33V        ((uint32_t)1U << 17U)
 411 #define POC_SD2_DAT2_33V        ((uint32_t)1U << 16U)
 412 #define POC_SD2_DAT1_33V        ((uint32_t)1U << 15U)
 413 #define POC_SD2_DAT0_33V        ((uint32_t)1U << 14U)
 414 #define POC_SD2_CMD_33V         ((uint32_t)1U << 13U)
 415 #define POC_SD2_CLK_33V         ((uint32_t)1U << 12U)
 416 #define POC_SD1_DAT3_33V        ((uint32_t)1U << 11U)
 417 #define POC_SD1_DAT2_33V        ((uint32_t)1U << 10U)
 418 #define POC_SD1_DAT1_33V        ((uint32_t)1U << 9U)
 419 #define POC_SD1_DAT0_33V        ((uint32_t)1U << 8U)
 420 #define POC_SD1_CMD_33V         ((uint32_t)1U << 7U)
 421 #define POC_SD1_CLK_33V         ((uint32_t)1U << 6U)
 422 #define POC_SD0_DAT3_33V        ((uint32_t)1U << 5U)
 423 #define POC_SD0_DAT2_33V        ((uint32_t)1U << 4U)
 424 #define POC_SD0_DAT1_33V        ((uint32_t)1U << 3U)
 425 #define POC_SD0_DAT0_33V        ((uint32_t)1U << 2U)
 426 #define POC_SD0_CMD_33V         ((uint32_t)1U << 1U)
 427 #define POC_SD0_CLK_33V         ((uint32_t)1U << 0U)
 428
 429 #define DRVCTRL0_MASK           (0xCCCCCCCCU)
 430 #define DRVCTRL1_MASK           (0xCCCCCCC8U)
 431 #define DRVCTRL2_MASK           (0x88888888U)
 432 #define DRVCTRL3_MASK           (0x88888888U)
 433 #define DRVCTRL4_MASK           (0x88888888U)
 434 #define DRVCTRL5_MASK           (0x88888888U)
 435 #define DRVCTRL6_MASK           (0x88888888U)
 436 #define DRVCTRL7_MASK           (0x88888888U)
 437 #define DRVCTRL8_MASK           (0x88888888U)
 438 #define DRVCTRL9_MASK           (0x88888888U)
 439 #define DRVCTRL10_MASK          (0x88888888U)
 440 #define DRVCTRL11_MASK          (0x888888CCU)
 441 #define DRVCTRL12_MASK          (0xCCCFFFCFU)
 442 #define DRVCTRL13_MASK          (0xCC888888U)
 443 #define DRVCTRL14_MASK          (0x88888888U)
 444 #define DRVCTRL15_MASK          (0x88888888U)
 445 #define DRVCTRL16_MASK          (0x88888888U)
 446 #define DRVCTRL17_MASK          (0x88888888U)
 447 #define DRVCTRL18_MASK          (0x88888888U)
 448 #define DRVCTRL19_MASK          (0x88888888U)
 449 #define DRVCTRL20_MASK          (0x88888888U)
 450 #define DRVCTRL21_MASK          (0x88888888U)
 451 #define DRVCTRL22_MASK          (0x88888888U)
 452 #define DRVCTRL23_MASK          (0x88888888U)
 453 #define DRVCTRL24_MASK          (0x8888888FU)
 454
 455 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
 456 #define DRVCTRL0_QSPI0_MOSI_IO0(x)      ((uint32_t)(x) << 24U)
 457 #define DRVCTRL0_QSPI0_MISO_IO1(x)      ((uint32_t)(x) << 20U)
 458 #define DRVCTRL0_QSPI0_IO2(x)   ((uint32_t)(x) << 16U)
 459 #define DRVCTRL0_QSPI0_IO3(x)   ((uint32_t)(x) << 12U)
 460 #define DRVCTRL0_QSPI0_SSL(x)   ((uint32_t)(x) << 8U)
 461 #define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
 462 #define DRVCTRL0_QSPI1_MOSI_IO0(x)      ((uint32_t)(x) << 0U)
 463 #define DRVCTRL1_QSPI1_MISO_IO1(x)      ((uint32_t)(x) << 28U)
 464 #define DRVCTRL1_QSPI1_IO2(x)   ((uint32_t)(x) << 24U)
 465 #define DRVCTRL1_QSPI1_IO3(x)   ((uint32_t)(x) << 20U)
 466 #define DRVCTRL1_QSPI1_SS(x)    ((uint32_t)(x) << 16U)
 467 #define DRVCTRL1_RPC_INT(x)     ((uint32_t)(x) << 12U)
 468 #define DRVCTRL1_RPC_WP(x)      ((uint32_t)(x) << 8U)
 469 #define DRVCTRL1_RPC_RESET(x)   ((uint32_t)(x) << 4U)
 470 #define DRVCTRL1_AVB_RX_CTL(x)  ((uint32_t)(x) << 0U)
 471 #define DRVCTRL2_AVB_RXC(x)     ((uint32_t)(x) << 28U)
 472 #define DRVCTRL2_AVB_RD0(x)     ((uint32_t)(x) << 24U)
 473 #define DRVCTRL2_AVB_RD1(x)     ((uint32_t)(x) << 20U)
 474 #define DRVCTRL2_AVB_RD2(x)     ((uint32_t)(x) << 16U)
 475 #define DRVCTRL2_AVB_RD3(x)     ((uint32_t)(x) << 12U)
 476 #define DRVCTRL2_AVB_TX_CTL(x)  ((uint32_t)(x) << 8U)
 477 #define DRVCTRL2_AVB_TXC(x)     ((uint32_t)(x) << 4U)
 478 #define DRVCTRL2_AVB_TD0(x)     ((uint32_t)(x) << 0U)
 479 #define DRVCTRL3_AVB_TD1(x)     ((uint32_t)(x) << 28U)
 480 #define DRVCTRL3_AVB_TD2(x)     ((uint32_t)(x) << 24U)
 481 #define DRVCTRL3_AVB_TD3(x)     ((uint32_t)(x) << 20U)
 482 #define DRVCTRL3_AVB_TXCREFCLK(x)       ((uint32_t)(x) << 16U)
 483 #define DRVCTRL3_AVB_MDIO(x)    ((uint32_t)(x) << 12U)
 484 #define DRVCTRL3_AVB_MDC(x)     ((uint32_t)(x) << 8U)
 485 #define DRVCTRL3_AVB_MAGIC(x)   ((uint32_t)(x) << 4U)
 486 #define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
 487 #define DRVCTRL4_AVB_LINK(x)    ((uint32_t)(x) << 28U)
 488 #define DRVCTRL4_AVB_AVTP_MATCH(x)      ((uint32_t)(x) << 24U)
 489 #define DRVCTRL4_AVB_AVTP_CAPTURE(x)    ((uint32_t)(x) << 20U)
 490 #define DRVCTRL4_IRQ0(x)        ((uint32_t)(x) << 16U)
 491 #define DRVCTRL4_IRQ1(x)        ((uint32_t)(x) << 12U)
 492 #define DRVCTRL4_IRQ2(x)        ((uint32_t)(x) << 8U)
 493 #define DRVCTRL4_IRQ3(x)        ((uint32_t)(x) << 4U)
 494 #define DRVCTRL4_IRQ4(x)        ((uint32_t)(x) << 0U)
 495 #define DRVCTRL5_IRQ5(x)        ((uint32_t)(x) << 28U)
 496 #define DRVCTRL5_PWM0(x)        ((uint32_t)(x) << 24U)
 497 #define DRVCTRL5_PWM1(x)        ((uint32_t)(x) << 20U)
 498 #define DRVCTRL5_PWM2(x)        ((uint32_t)(x) << 16U)
 499 #define DRVCTRL5_A0(x)          ((uint32_t)(x) << 12U)
 500 #define DRVCTRL5_A1(x)          ((uint32_t)(x) << 8U)
 501 #define DRVCTRL5_A2(x)          ((uint32_t)(x) << 4U)
 502 #define DRVCTRL5_A3(x)          ((uint32_t)(x) << 0U)
 503 #define DRVCTRL6_A4(x)          ((uint32_t)(x) << 28U)
 504 #define DRVCTRL6_A5(x)          ((uint32_t)(x) << 24U)
 505 #define DRVCTRL6_A6(x)          ((uint32_t)(x) << 20U)
 506 #define DRVCTRL6_A7(x)          ((uint32_t)(x) << 16U)
 507 #define DRVCTRL6_A8(x)          ((uint32_t)(x) << 12U)
 508 #define DRVCTRL6_A9(x)          ((uint32_t)(x) << 8U)
 509 #define DRVCTRL6_A10(x)         ((uint32_t)(x) << 4U)
 510 #define DRVCTRL6_A11(x)         ((uint32_t)(x) << 0U)
 511 #define DRVCTRL7_A12(x)         ((uint32_t)(x) << 28U)
 512 #define DRVCTRL7_A13(x)         ((uint32_t)(x) << 24U)
 513 #define DRVCTRL7_A14(x)         ((uint32_t)(x) << 20U)
 514 #define DRVCTRL7_A15(x)         ((uint32_t)(x) << 16U)
 515 #define DRVCTRL7_A16(x)         ((uint32_t)(x) << 12U)
 516 #define DRVCTRL7_A17(x)         ((uint32_t)(x) << 8U)
 517 #define DRVCTRL7_A18(x)         ((uint32_t)(x) << 4U)
 518 #define DRVCTRL7_A19(x)         ((uint32_t)(x) << 0U)
 519 #define DRVCTRL8_CLKOUT(x)      ((uint32_t)(x) << 28U)
 520 #define DRVCTRL8_CS0(x)         ((uint32_t)(x) << 24U)
 521 #define DRVCTRL8_CS1_A2(x)      ((uint32_t)(x) << 20U)
 522 #define DRVCTRL8_BS(x)          ((uint32_t)(x) << 16U)
 523 #define DRVCTRL8_RD(x)          ((uint32_t)(x) << 12U)
 524 #define DRVCTRL8_RD_W(x)        ((uint32_t)(x) << 8U)
 525 #define DRVCTRL8_WE0(x)         ((uint32_t)(x) << 4U)
 526 #define DRVCTRL8_WE1(x)         ((uint32_t)(x) << 0U)
 527 #define DRVCTRL9_EX_WAIT0(x)    ((uint32_t)(x) << 28U)
 528 #define DRVCTRL9_PRESETOU(x)    ((uint32_t)(x) << 24U)
 529 #define DRVCTRL9_D0(x)          ((uint32_t)(x) << 20U)
 530 #define DRVCTRL9_D1(x)          ((uint32_t)(x) << 16U)
 531 #define DRVCTRL9_D2(x)          ((uint32_t)(x) << 12U)
 532 #define DRVCTRL9_D3(x)          ((uint32_t)(x) << 8U)
 533 #define DRVCTRL9_D4(x)          ((uint32_t)(x) << 4U)
 534 #define DRVCTRL9_D5(x)          ((uint32_t)(x) << 0U)
 535 #define DRVCTRL10_D6(x)         ((uint32_t)(x) << 28U)
 536 #define DRVCTRL10_D7(x)         ((uint32_t)(x) << 24U)
 537 #define DRVCTRL10_D8(x)         ((uint32_t)(x) << 20U)
 538 #define DRVCTRL10_D9(x)         ((uint32_t)(x) << 16U)
 539 #define DRVCTRL10_D10(x)        ((uint32_t)(x) << 12U)
 540 #define DRVCTRL10_D11(x)        ((uint32_t)(x) << 8U)
 541 #define DRVCTRL10_D12(x)        ((uint32_t)(x) << 4U)
 542 #define DRVCTRL10_D13(x)        ((uint32_t)(x) << 0U)
 543 #define DRVCTRL11_D14(x)        ((uint32_t)(x) << 28U)
 544 #define DRVCTRL11_D15(x)        ((uint32_t)(x) << 24U)
 545 #define DRVCTRL11_AVS1(x)       ((uint32_t)(x) << 20U)
 546 #define DRVCTRL11_AVS2(x)       ((uint32_t)(x) << 16U)
 547 #define DRVCTRL11_HDMI0_CEC(x)  ((uint32_t)(x) << 12U)
 548 #define DRVCTRL11_HDMI1_CEC(x)  ((uint32_t)(x) << 8U)
 549 #define DRVCTRL11_DU_DOTCLKIN0(x)       ((uint32_t)(x) << 4U)
 550 #define DRVCTRL11_DU_DOTCLKIN1(x)       ((uint32_t)(x) << 0U)
 551 #define DRVCTRL12_DU_DOTCLKIN2(x)       ((uint32_t)(x) << 28U)
 552 #define DRVCTRL12_DU_DOTCLKIN3(x)       ((uint32_t)(x) << 24U)
 553 #define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
 554 #define DRVCTRL12_DU_TMS(x)     ((uint32_t)(x) << 4U)
 555 #define DRVCTRL13_TDO(x)        ((uint32_t)(x) << 28U)
 556 #define DRVCTRL13_ASEBRK(x)     ((uint32_t)(x) << 24U)
 557 #define DRVCTRL13_SD0_CLK(x)    ((uint32_t)(x) << 20U)
 558 #define DRVCTRL13_SD0_CMD(x)    ((uint32_t)(x) << 16U)
 559 #define DRVCTRL13_SD0_DAT0(x)   ((uint32_t)(x) << 12U)
 560 #define DRVCTRL13_SD0_DAT1(x)   ((uint32_t)(x) << 8U)
 561 #define DRVCTRL13_SD0_DAT2(x)   ((uint32_t)(x) << 4U)
 562 #define DRVCTRL13_SD0_DAT3(x)   ((uint32_t)(x) << 0U)
 563 #define DRVCTRL14_SD1_CLK(x)    ((uint32_t)(x) << 28U)
 564 #define DRVCTRL14_SD1_CMD(x)    ((uint32_t)(x) << 24U)
 565 #define DRVCTRL14_SD1_DAT0(x)   ((uint32_t)(x) << 20U)
 566 #define DRVCTRL14_SD1_DAT1(x)   ((uint32_t)(x) << 16U)
 567 #define DRVCTRL14_SD1_DAT2(x)   ((uint32_t)(x) << 12U)
 568 #define DRVCTRL14_SD1_DAT3(x)   ((uint32_t)(x) << 8U)
 569 #define DRVCTRL14_SD2_CLK(x)    ((uint32_t)(x) << 4U)
 570 #define DRVCTRL14_SD2_CMD(x)    ((uint32_t)(x) << 0U)
 571 #define DRVCTRL15_SD2_DAT0(x)   ((uint32_t)(x) << 28U)
 572 #define DRVCTRL15_SD2_DAT1(x)   ((uint32_t)(x) << 24U)
 573 #define DRVCTRL15_SD2_DAT2(x)   ((uint32_t)(x) << 20U)
 574 #define DRVCTRL15_SD2_DAT3(x)   ((uint32_t)(x) << 16U)
 575 #define DRVCTRL15_SD2_DS(x)     ((uint32_t)(x) << 12U)
 576 #define DRVCTRL15_SD3_CLK(x)    ((uint32_t)(x) << 8U)
 577 #define DRVCTRL15_SD3_CMD(x)    ((uint32_t)(x) << 4U)
 578 #define DRVCTRL15_SD3_DAT0(x)   ((uint32_t)(x) << 0U)
 579 #define DRVCTRL16_SD3_DAT1(x)   ((uint32_t)(x) << 28U)
 580 #define DRVCTRL16_SD3_DAT2(x)   ((uint32_t)(x) << 24U)
 581 #define DRVCTRL16_SD3_DAT3(x)   ((uint32_t)(x) << 20U)
 582 #define DRVCTRL16_SD3_DAT4(x)   ((uint32_t)(x) << 16U)
 583 #define DRVCTRL16_SD3_DAT5(x)   ((uint32_t)(x) << 12U)
 584 #define DRVCTRL16_SD3_DAT6(x)   ((uint32_t)(x) << 8U)
 585 #define DRVCTRL16_SD3_DAT7(x)   ((uint32_t)(x) << 4U)
 586 #define DRVCTRL16_SD3_DS(x)     ((uint32_t)(x) << 0U)
 587 #define DRVCTRL17_SD0_CD(x)     ((uint32_t)(x) << 28U)
 588 #define DRVCTRL17_SD0_WP(x)     ((uint32_t)(x) << 24U)
 589 #define DRVCTRL17_SD1_CD(x)     ((uint32_t)(x) << 20U)
 590 #define DRVCTRL17_SD1_WP(x)     ((uint32_t)(x) << 16U)
 591 #define DRVCTRL17_SCK0(x)       ((uint32_t)(x) << 12U)
 592 #define DRVCTRL17_RX0(x)        ((uint32_t)(x) << 8U)
 593 #define DRVCTRL17_TX0(x)        ((uint32_t)(x) << 4U)
 594 #define DRVCTRL17_CTS0(x)       ((uint32_t)(x) << 0U)
 595 #define DRVCTRL18_RTS0_TANS(x)  ((uint32_t)(x) << 28U)
 596 #define DRVCTRL18_RX1(x)        ((uint32_t)(x) << 24U)
 597 #define DRVCTRL18_TX1(x)        ((uint32_t)(x) << 20U)
 598 #define DRVCTRL18_CTS1(x)       ((uint32_t)(x) << 16U)
 599 #define DRVCTRL18_RTS1_TANS(x)  ((uint32_t)(x) << 12U)
 600 #define DRVCTRL18_SCK2(x)       ((uint32_t)(x) << 8U)
 601 #define DRVCTRL18_TX2(x)        ((uint32_t)(x) << 4U)
 602 #define DRVCTRL18_RX2(x)        ((uint32_t)(x) << 0U)
 603 #define DRVCTRL19_HSCK0(x)      ((uint32_t)(x) << 28U)
 604 #define DRVCTRL19_HRX0(x)       ((uint32_t)(x) << 24U)
 605 #define DRVCTRL19_HTX0(x)       ((uint32_t)(x) << 20U)
 606 #define DRVCTRL19_HCTS0(x)      ((uint32_t)(x) << 16U)
 607 #define DRVCTRL19_HRTS0(x)      ((uint32_t)(x) << 12U)
 608 #define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
 609 #define DRVCTRL19_MSIOF0_SYNC(x)        ((uint32_t)(x) << 4U)
 610 #define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
 611 #define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
 612 #define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
 613 #define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
 614 #define DRVCTRL20_MLB_CLK(x)    ((uint32_t)(x) << 16U)
 615 #define DRVCTRL20_MLB_SIG(x)    ((uint32_t)(x) << 12U)
 616 #define DRVCTRL20_MLB_DAT(x)    ((uint32_t)(x) << 8U)
 617 #define DRVCTRL20_MLB_REF(x)    ((uint32_t)(x) << 4U)
 618 #define DRVCTRL20_SSI_SCK0129(x)        ((uint32_t)(x) << 0U)
 619 #define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
 620 #define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
 621 #define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
 622 #define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
 623 #define DRVCTRL21_SSI_SCK34(x)  ((uint32_t)(x) << 12U)
 624 #define DRVCTRL21_SSI_WS34(x)   ((uint32_t)(x) << 8U)
 625 #define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
 626 #define DRVCTRL21_SSI_SCK4(x)   ((uint32_t)(x) << 0U)
 627 #define DRVCTRL22_SSI_WS4(x)    ((uint32_t)(x) << 28U)
 628 #define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
 629 #define DRVCTRL22_SSI_SCK5(x)   ((uint32_t)(x) << 20U)
 630 #define DRVCTRL22_SSI_WS5(x)    ((uint32_t)(x) << 16U)
 631 #define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
 632 #define DRVCTRL22_SSI_SCK6(x)   ((uint32_t)(x) << 8U)
 633 #define DRVCTRL22_SSI_WS6(x)    ((uint32_t)(x) << 4U)
 634 #define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
 635 #define DRVCTRL23_SSI_SCK78(x)  ((uint32_t)(x) << 28U)
 636 #define DRVCTRL23_SSI_WS78(x)   ((uint32_t)(x) << 24U)
 637 #define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
 638 #define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
 639 #define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
 640 #define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
 641 #define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
 642 #define DRVCTRL23_USB0_PWEN(x)  ((uint32_t)(x) << 0U)
 643 #define DRVCTRL24_USB0_OVC(x)   ((uint32_t)(x) << 28U)
 644 #define DRVCTRL24_USB1_PWEN(x)  ((uint32_t)(x) << 24U)
 645 #define DRVCTRL24_USB1_OVC(x)   ((uint32_t)(x) << 20U)
 646 #define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
 647 #define DRVCTRL24_USB30_OVC(x)  ((uint32_t)(x) << 12U)
 648 #define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
 649 #define DRVCTRL24_USB31_OVC(x)  ((uint32_t)(x) << 4U)
 650
 651 #define MOD_SEL0_MSIOF3_A       ((uint32_t)0U << 29U)
 652 #define MOD_SEL0_MSIOF3_B       ((uint32_t)1U << 29U)
 653 #define MOD_SEL0_MSIOF3_C       ((uint32_t)2U << 29U)
 654 #define MOD_SEL0_MSIOF3_D       ((uint32_t)3U << 29U)
 655 #define MOD_SEL0_MSIOF3_E       ((uint32_t)4U << 29U)
 656 #define MOD_SEL0_MSIOF2_A       ((uint32_t)0U << 27U)
 657 #define MOD_SEL0_MSIOF2_B       ((uint32_t)1U << 27U)
 658 #define MOD_SEL0_MSIOF2_C       ((uint32_t)2U << 27U)
 659 #define MOD_SEL0_MSIOF2_D       ((uint32_t)3U << 27U)
 660 #define MOD_SEL0_MSIOF1_A       ((uint32_t)0U << 24U)
 661 #define MOD_SEL0_MSIOF1_B       ((uint32_t)1U << 24U)
 662 #define MOD_SEL0_MSIOF1_C       ((uint32_t)2U << 24U)
 663 #define MOD_SEL0_MSIOF1_D       ((uint32_t)3U << 24U)
 664 #define MOD_SEL0_MSIOF1_E       ((uint32_t)4U << 24U)
 665 #define MOD_SEL0_MSIOF1_F       ((uint32_t)5U << 24U)
 666 #define MOD_SEL0_MSIOF1_G       ((uint32_t)6U << 24U)
 667 #define MOD_SEL0_LBSC_A         ((uint32_t)0U << 23U)
 668 #define MOD_SEL0_LBSC_B         ((uint32_t)1U << 23U)
 669 #define MOD_SEL0_IEBUS_A        ((uint32_t)0U << 22U)
 670 #define MOD_SEL0_IEBUS_B        ((uint32_t)1U << 22U)
 671 #define MOD_SEL0_I2C2_A         ((uint32_t)0U << 21U)
 672 #define MOD_SEL0_I2C2_B         ((uint32_t)1U << 21U)
 673 #define MOD_SEL0_I2C1_A         ((uint32_t)0U << 20U)
 674 #define MOD_SEL0_I2C1_B         ((uint32_t)1U << 20U)
 675 #define MOD_SEL0_HSCIF4_A       ((uint32_t)0U << 19U)
 676 #define MOD_SEL0_HSCIF4_B       ((uint32_t)1U << 19U)
 677 #define MOD_SEL0_HSCIF3_A       ((uint32_t)0U << 17U)
 678 #define MOD_SEL0_HSCIF3_B       ((uint32_t)1U << 17U)
 679 #define MOD_SEL0_HSCIF3_C       ((uint32_t)2U << 17U)
 680 #define MOD_SEL0_HSCIF3_D       ((uint32_t)3U << 17U)
 681 #define MOD_SEL0_HSCIF1_A       ((uint32_t)0U << 16U)
 682 #define MOD_SEL0_HSCIF1_B       ((uint32_t)1U << 16U)
 683 #define MOD_SEL0_FSO_A          ((uint32_t)0U << 15U)
 684 #define MOD_SEL0_FSO_B          ((uint32_t)1U << 15U)
 685 #define MOD_SEL0_HSCIF2_A       ((uint32_t)0U << 13U)
 686 #define MOD_SEL0_HSCIF2_B       ((uint32_t)1U << 13U)
 687 #define MOD_SEL0_HSCIF2_C       ((uint32_t)2U << 13U)
 688 #define MOD_SEL0_ETHERAVB_A     ((uint32_t)0U << 12U)
 689 #define MOD_SEL0_ETHERAVB_B     ((uint32_t)1U << 12U)
 690 #define MOD_SEL0_DRIF3_A        ((uint32_t)0U << 11U)
 691 #define MOD_SEL0_DRIF3_B        ((uint32_t)1U << 11U)
 692 #define MOD_SEL0_DRIF2_A        ((uint32_t)0U << 10U)
 693 #define MOD_SEL0_DRIF2_B        ((uint32_t)1U << 10U)
 694 #define MOD_SEL0_DRIF1_A        ((uint32_t)0U << 8U)
 695 #define MOD_SEL0_DRIF1_B        ((uint32_t)1U << 8U)
 696 #define MOD_SEL0_DRIF1_C        ((uint32_t)2U << 8U)
 697 #define MOD_SEL0_DRIF0_A        ((uint32_t)0U << 6U)
 698 #define MOD_SEL0_DRIF0_B        ((uint32_t)1U << 6U)
 699 #define MOD_SEL0_DRIF0_C        ((uint32_t)2U << 6U)
 700 #define MOD_SEL0_CANFD0_A       ((uint32_t)0U << 5U)
 701 #define MOD_SEL0_CANFD0_B       ((uint32_t)1U << 5U)
 702 #define MOD_SEL0_ADG_A_A        ((uint32_t)0U << 3U)
 703 #define MOD_SEL0_ADG_A_B        ((uint32_t)1U << 3U)
 704 #define MOD_SEL0_ADG_A_C        ((uint32_t)2U << 3U)
 705 #define MOD_SEL1_TSIF1_A        ((uint32_t)0U << 30U)
 706 #define MOD_SEL1_TSIF1_B        ((uint32_t)1U << 30U)
 707 #define MOD_SEL1_TSIF1_C        ((uint32_t)2U << 30U)
 708 #define MOD_SEL1_TSIF1_D        ((uint32_t)3U << 30U)
 709 #define MOD_SEL1_TSIF0_A        ((uint32_t)0U << 27U)
 710 #define MOD_SEL1_TSIF0_B        ((uint32_t)1U << 27U)
 711 #define MOD_SEL1_TSIF0_C        ((uint32_t)2U << 27U)
 712 #define MOD_SEL1_TSIF0_D        ((uint32_t)3U << 27U)
 713 #define MOD_SEL1_TSIF0_E        ((uint32_t)4U << 27U)
 714 #define MOD_SEL1_TIMER_TMU_A    ((uint32_t)0U << 26U)
 715 #define MOD_SEL1_TIMER_TMU_B    ((uint32_t)1U << 26U)
 716 #define MOD_SEL1_SSP1_1_A       ((uint32_t)0U << 24U)
 717 #define MOD_SEL1_SSP1_1_B       ((uint32_t)1U << 24U)
 718 #define MOD_SEL1_SSP1_1_C       ((uint32_t)2U << 24U)
 719 #define MOD_SEL1_SSP1_1_D       ((uint32_t)3U << 24U)
 720 #define MOD_SEL1_SSP1_0_A       ((uint32_t)0U << 21U)
 721 #define MOD_SEL1_SSP1_0_B       ((uint32_t)1U << 21U)
 722 #define MOD_SEL1_SSP1_0_C       ((uint32_t)2U << 21U)
 723 #define MOD_SEL1_SSP1_0_D       ((uint32_t)3U << 21U)
 724 #define MOD_SEL1_SSP1_0_E       ((uint32_t)4U << 21U)
 725 #define MOD_SEL1_SSI_A          ((uint32_t)0U << 20U)
 726 #define MOD_SEL1_SSI_B          ((uint32_t)1U << 20U)
 727 #define MOD_SEL1_SPEED_PULSE_IF_A       ((uint32_t)0U << 19U)
 728 #define MOD_SEL1_SPEED_PULSE_IF_B       ((uint32_t)1U << 19U)
 729 #define MOD_SEL1_SIMCARD_A      ((uint32_t)0U << 17U)
 730 #define MOD_SEL1_SIMCARD_B      ((uint32_t)1U << 17U)
 731 #define MOD_SEL1_SIMCARD_C      ((uint32_t)2U << 17U)
 732 #define MOD_SEL1_SIMCARD_D      ((uint32_t)3U << 17U)
 733 #define MOD_SEL1_SDHI2_A        ((uint32_t)0U << 16U)
 734 #define MOD_SEL1_SDHI2_B        ((uint32_t)1U << 16U)
 735 #define MOD_SEL1_SCIF4_A        ((uint32_t)0U << 14U)
 736 #define MOD_SEL1_SCIF4_B        ((uint32_t)1U << 14U)
 737 #define MOD_SEL1_SCIF4_C        ((uint32_t)2U << 14U)
 738 #define MOD_SEL1_SCIF3_A        ((uint32_t)0U << 13U)
 739 #define MOD_SEL1_SCIF3_B        ((uint32_t)1U << 13U)
 740 #define MOD_SEL1_SCIF2_A        ((uint32_t)0U << 12U)
 741 #define MOD_SEL1_SCIF2_B        ((uint32_t)1U << 12U)
 742 #define MOD_SEL1_SCIF1_A        ((uint32_t)0U << 11U)
 743 #define MOD_SEL1_SCIF1_B        ((uint32_t)1U << 11U)
 744 #define MOD_SEL1_SCIF_A         ((uint32_t)0U << 10U)
 745 #define MOD_SEL1_SCIF_B         ((uint32_t)1U << 10U)
 746 #define MOD_SEL1_REMOCON_A      ((uint32_t)0U << 9U)
 747 #define MOD_SEL1_REMOCON_B      ((uint32_t)1U << 9U)
 748 #define MOD_SEL1_RCAN0_A        ((uint32_t)0U << 6U)
 749 #define MOD_SEL1_RCAN0_B        ((uint32_t)1U << 6U)
 750 #define MOD_SEL1_PWM6_A         ((uint32_t)0U << 5U)
 751 #define MOD_SEL1_PWM6_B         ((uint32_t)1U << 5U)
 752 #define MOD_SEL1_PWM5_A         ((uint32_t)0U << 4U)
 753 #define MOD_SEL1_PWM5_B         ((uint32_t)1U << 4U)
 754 #define MOD_SEL1_PWM4_A         ((uint32_t)0U << 3U)
 755 #define MOD_SEL1_PWM4_B         ((uint32_t)1U << 3U)
 756 #define MOD_SEL1_PWM3_A         ((uint32_t)0U << 2U)
 757 #define MOD_SEL1_PWM3_B         ((uint32_t)1U << 2U)
 758 #define MOD_SEL1_PWM2_A         ((uint32_t)0U << 1U)
 759 #define MOD_SEL1_PWM2_B         ((uint32_t)1U << 1U)
 760 #define MOD_SEL1_PWM1_A         ((uint32_t)0U << 0U)
 761 #define MOD_SEL1_PWM1_B         ((uint32_t)1U << 0U)
 762 #define MOD_SEL2_I2C_5_A        ((uint32_t)0U << 31U)
 763 #define MOD_SEL2_I2C_5_B        ((uint32_t)1U << 31U)
 764 #define MOD_SEL2_I2C_3_A        ((uint32_t)0U << 30U)
 765 #define MOD_SEL2_I2C_3_B        ((uint32_t)1U << 30U)
 766 #define MOD_SEL2_I2C_0_A        ((uint32_t)0U << 29U)
 767 #define MOD_SEL2_I2C_0_B        ((uint32_t)1U << 29U)
 768 #define MOD_SEL2_FM_A           ((uint32_t)0U << 27U)
 769 #define MOD_SEL2_FM_B           ((uint32_t)1U << 27U)
 770 #define MOD_SEL2_FM_C           ((uint32_t)2U << 27U)
 771 #define MOD_SEL2_FM_D           ((uint32_t)3U << 27U)
 772 #define MOD_SEL2_SCIF5_A        ((uint32_t)0U << 26U)
 773 #define MOD_SEL2_SCIF5_B        ((uint32_t)1U << 26U)
 774 #define MOD_SEL2_I2C6_A         ((uint32_t)0U << 23U)
 775 #define MOD_SEL2_I2C6_B         ((uint32_t)1U << 23U)
 776 #define MOD_SEL2_I2C6_C         ((uint32_t)2U << 23U)
 777 #define MOD_SEL2_NDF_A          ((uint32_t)0U << 22U)
 778 #define MOD_SEL2_NDF_B          ((uint32_t)1U << 22U)
 779 #define MOD_SEL2_SSI2_A         ((uint32_t)0U << 21U)
 780 #define MOD_SEL2_SSI2_B         ((uint32_t)1U << 21U)
 781 #define MOD_SEL2_SSI9_A         ((uint32_t)0U << 20U)
 782 #define MOD_SEL2_SSI9_B         ((uint32_t)1U << 20U)
 783 #define MOD_SEL2_TIMER_TMU2_A   ((uint32_t)0U << 19U)
 784 #define MOD_SEL2_TIMER_TMU2_B   ((uint32_t)1U << 19U)
 785 #define MOD_SEL2_ADG_B_A        ((uint32_t)0U << 18U)
 786 #define MOD_SEL2_ADG_B_B        ((uint32_t)1U << 18U)
 787 #define MOD_SEL2_ADG_C_A        ((uint32_t)0U << 17U)
 788 #define MOD_SEL2_ADG_C_B        ((uint32_t)1U << 17U)
 789 #define MOD_SEL2_VIN4_A         ((uint32_t)0U << 0U)
 790 #define MOD_SEL2_VIN4_B         ((uint32_t)1U << 0U)
 791
 792 /* SCIF3 Registers for Dummy write */
 793 #define SCIF3_BASE              (0xE6C50000U)
 794 #define SCIF3_SCFCR             (SCIF3_BASE + 0x0018U)
 795 #define SCIF3_SCFDR             (SCIF3_BASE + 0x001CU)
 796 #define SCFCR_DATA              (0x0000U)
 797
 798 /* Realtime module stop control */
 799 #define CPG_BASE                (0xE6150000U)
 800 #define CPG_MSTPSR0             (CPG_BASE + 0x0030U)
 801 #define CPG_RMSTPCR0            (CPG_BASE + 0x0110U)
 802 #define RMSTPCR0_RTDMAC         (0x00200000U)
 803
 804 static void pfc_reg_write(uint32_t addr, uint32_t data);
 805
 806 static void pfc_reg_write(uint32_t addr, uint32_t data)
 807 {
 808         mmio_write_32(PFC_PMMR, ~data);
 809         mmio_write_32((uintptr_t) addr, data);
 810 }
 811
 812 void pfc_init_h3_v2(void)
 813 {
 814         uint32_t reg;
 815
 816         /* initialize module select */
 817         pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A
 818                       | MOD_SEL0_MSIOF2_A
 819                       | MOD_SEL0_MSIOF1_A
 820                       | MOD_SEL0_LBSC_A
 821                       | MOD_SEL0_IEBUS_A
 822                       | MOD_SEL0_I2C2_A
 823                       | MOD_SEL0_I2C1_A
 824                       | MOD_SEL0_HSCIF4_A
 825                       | MOD_SEL0_HSCIF3_A
 826                       | MOD_SEL0_HSCIF1_A
 827                       | MOD_SEL0_FSO_A
 828                       | MOD_SEL0_HSCIF2_A
 829                       | MOD_SEL0_ETHERAVB_A
 830                       | MOD_SEL0_DRIF3_A
 831                       | MOD_SEL0_DRIF2_A
 832                       | MOD_SEL0_DRIF1_A
 833                       | MOD_SEL0_DRIF0_A
 834                       | MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
 835         pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
 836                       | MOD_SEL1_TSIF0_A
 837                       | MOD_SEL1_TIMER_TMU_A
 838                       | MOD_SEL1_SSP1_1_A
 839                       | MOD_SEL1_SSP1_0_A
 840                       | MOD_SEL1_SSI_A
 841                       | MOD_SEL1_SPEED_PULSE_IF_A
 842                       | MOD_SEL1_SIMCARD_A
 843                       | MOD_SEL1_SDHI2_A
 844                       | MOD_SEL1_SCIF4_A
 845                       | MOD_SEL1_SCIF3_A
 846                       | MOD_SEL1_SCIF2_A
 847                       | MOD_SEL1_SCIF1_A
 848                       | MOD_SEL1_SCIF_A
 849                       | MOD_SEL1_REMOCON_A
 850                       | MOD_SEL1_RCAN0_A
 851                       | MOD_SEL1_PWM6_A
 852                       | MOD_SEL1_PWM5_A
 853                       | MOD_SEL1_PWM4_A
 854                       | MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
 855         pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
 856                       | MOD_SEL2_I2C_3_A
 857                       | MOD_SEL2_I2C_0_A
 858                       | MOD_SEL2_FM_A
 859                       | MOD_SEL2_SCIF5_A
 860                       | MOD_SEL2_I2C6_A
 861                       | MOD_SEL2_NDF_A
 862                       | MOD_SEL2_SSI2_A
 863                       | MOD_SEL2_SSI9_A
 864                       | MOD_SEL2_TIMER_TMU2_A
 865                       | MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
 866
 867         /* initialize peripheral function select */
 868         pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
 869                       | IPSR_24_FUNC(0)
 870                       | IPSR_20_FUNC(0)
 871                       | IPSR_16_FUNC(0)
 872                       | IPSR_12_FUNC(0)
 873                       | IPSR_8_FUNC(0)
 874                       | IPSR_4_FUNC(0)
 875                       | IPSR_0_FUNC(0));
 876         pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6)
 877                       | IPSR_24_FUNC(0)
 878                       | IPSR_20_FUNC(0)
 879                       | IPSR_16_FUNC(0)
 880                       | IPSR_12_FUNC(3)
 881                       | IPSR_8_FUNC(3)
 882                       | IPSR_4_FUNC(3)
 883                       | IPSR_0_FUNC(3));
 884         pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0)
 885                       | IPSR_24_FUNC(6)
 886                       | IPSR_20_FUNC(6)
 887                       | IPSR_16_FUNC(6)
 888                       | IPSR_12_FUNC(6)
 889                       | IPSR_8_FUNC(6)
 890                       | IPSR_4_FUNC(6)
 891                       | IPSR_0_FUNC(6));
 892         pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6)
 893                       | IPSR_24_FUNC(6)
 894                       | IPSR_20_FUNC(6)
 895                       | IPSR_16_FUNC(6)
 896                       | IPSR_12_FUNC(6)
 897                       | IPSR_8_FUNC(0)
 898                       | IPSR_4_FUNC(0)
 899                       | IPSR_0_FUNC(0));
 900         pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0)
 901                       | IPSR_24_FUNC(0)
 902                       | IPSR_20_FUNC(0)
 903                       | IPSR_16_FUNC(0)
 904                       | IPSR_12_FUNC(0)
 905                       | IPSR_8_FUNC(6)
 906                       | IPSR_4_FUNC(6)
 907                       | IPSR_0_FUNC(6));
 908         pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0)
 909                       | IPSR_24_FUNC(0)
 910                       | IPSR_20_FUNC(0)
 911                       | IPSR_16_FUNC(0)
 912                       | IPSR_12_FUNC(0)
 913                       | IPSR_8_FUNC(6)
 914                       | IPSR_4_FUNC(0)
 915                       | IPSR_0_FUNC(0));
 916         pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6)
 917                       | IPSR_24_FUNC(6)
 918                       | IPSR_20_FUNC(6)
 919                       | IPSR_16_FUNC(6)
 920                       | IPSR_12_FUNC(6)
 921                       | IPSR_8_FUNC(0)
 922                       | IPSR_4_FUNC(0)
 923                       | IPSR_0_FUNC(0));
 924         pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0)
 925                       | IPSR_24_FUNC(0)
 926                       | IPSR_20_FUNC(0)
 927                       | IPSR_16_FUNC(0)
 928                       | IPSR_12_FUNC(0)
 929                       | IPSR_8_FUNC(6)
 930                       | IPSR_4_FUNC(6)
 931                       | IPSR_0_FUNC(6));
 932         pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1)
 933                       | IPSR_24_FUNC(1)
 934                       | IPSR_20_FUNC(1)
 935                       | IPSR_16_FUNC(1)
 936                       | IPSR_12_FUNC(0)
 937                       | IPSR_8_FUNC(0)
 938                       | IPSR_4_FUNC(0)
 939                       | IPSR_0_FUNC(0));
 940         pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0)
 941                       | IPSR_24_FUNC(0)
 942                       | IPSR_20_FUNC(0)
 943                       | IPSR_16_FUNC(0)
 944                       | IPSR_12_FUNC(0)
 945                       | IPSR_8_FUNC(0)
 946                       | IPSR_4_FUNC(0)
 947                       | IPSR_0_FUNC(0));
 948         pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1)
 949                       | IPSR_24_FUNC(0)
 950                       | IPSR_20_FUNC(0)
 951                       | IPSR_16_FUNC(0)
 952                       | IPSR_12_FUNC(0)
 953                       | IPSR_8_FUNC(0)
 954                       | IPSR_4_FUNC(0)
 955                       | IPSR_0_FUNC(0));
 956         pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
 957                       | IPSR_24_FUNC(4)
 958                       | IPSR_20_FUNC(0)
 959                       | IPSR_16_FUNC(0)
 960                       | IPSR_12_FUNC(0)
 961                       | IPSR_8_FUNC(0)
 962                       | IPSR_4_FUNC(0)
 963                       | IPSR_0_FUNC(1));
 964         pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
 965                       | IPSR_24_FUNC(0)
 966                       | IPSR_20_FUNC(0)
 967                       | IPSR_16_FUNC(0)
 968                       | IPSR_12_FUNC(0)
 969                       | IPSR_8_FUNC(4)
 970                       | IPSR_4_FUNC(0)
 971                       | IPSR_0_FUNC(0));
 972         pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8)
 973                       | IPSR_24_FUNC(0)
 974                       | IPSR_20_FUNC(0)
 975                       | IPSR_16_FUNC(0)
 976                       | IPSR_12_FUNC(0)
 977                       | IPSR_8_FUNC(3)
 978                       | IPSR_4_FUNC(0)
 979                       | IPSR_0_FUNC(0));
 980         pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0)
 981                       | IPSR_24_FUNC(0)
 982                       | IPSR_20_FUNC(0)
 983                       | IPSR_16_FUNC(0)
 984                       | IPSR_12_FUNC(0)
 985                       | IPSR_8_FUNC(0)
 986                       | IPSR_4_FUNC(3)
 987                       | IPSR_0_FUNC(8));
 988         pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0)
 989                       | IPSR_24_FUNC(0)
 990                       | IPSR_20_FUNC(0)
 991                       | IPSR_16_FUNC(0)
 992                       | IPSR_12_FUNC(0)
 993                       | IPSR_8_FUNC(0)
 994                       | IPSR_4_FUNC(0)
 995                       | IPSR_0_FUNC(0));
 996         pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0)
 997                       | IPSR_24_FUNC(0)
 998                       | IPSR_20_FUNC(0)
 999                       | IPSR_16_FUNC(0)
1000                       | IPSR_12_FUNC(0)
1001                       | IPSR_8_FUNC(0)
1002                       | IPSR_4_FUNC(0)
1003                       | IPSR_0_FUNC(0));
1004         pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0)
1005                       | IPSR_24_FUNC(0)
1006                       | IPSR_20_FUNC(0)
1007                       | IPSR_16_FUNC(0)
1008                       | IPSR_12_FUNC(0)
1009                       | IPSR_8_FUNC(0)
1010                       | IPSR_4_FUNC(1)
1011                       | IPSR_0_FUNC(0));
1012         pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0)
1013                       | IPSR_0_FUNC(0));
1014
1015         /* initialize GPIO/perihperal function select */
1016         pfc_reg_write(PFC_GPSR0, GPSR0_D15
1017                       | GPSR0_D14
1018                       | GPSR0_D13
1019                       | GPSR0_D12
1020                       | GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
1021         pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
1022                       | GPSR1_EX_WAIT0_A
1023                       | GPSR1_A19
1024                       | GPSR1_A18
1025                       | GPSR1_A17
1026                       | GPSR1_A16
1027                       | GPSR1_A15
1028                       | GPSR1_A14
1029                       | GPSR1_A13
1030                       | GPSR1_A12
1031                       | GPSR1_A7
1032                       | GPSR1_A6
1033                       | GPSR1_A5
1034                       | GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
1035         pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
1036                       | GPSR2_AVB_AVTP_MATCH_A
1037                       | GPSR2_AVB_LINK
1038                       | GPSR2_AVB_PHY_INT
1039                       | GPSR2_AVB_MDC
1040                       | GPSR2_PWM2_A
1041                       | GPSR2_PWM1_A
1042                       | GPSR2_IRQ5
1043                       | GPSR2_IRQ4
1044                       | GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
1045         pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
1046                       | GPSR3_SD0_CD
1047                       | GPSR3_SD1_DAT3
1048                       | GPSR3_SD1_DAT2
1049                       | GPSR3_SD1_DAT1
1050                       | GPSR3_SD1_DAT0
1051                       | GPSR3_SD0_DAT3
1052                       | GPSR3_SD0_DAT2
1053                       | GPSR3_SD0_DAT1
1054                       | GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
1055         pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
1056                       | GPSR4_SD3_DAT6
1057                       | GPSR4_SD3_DAT3
1058                       | GPSR4_SD3_DAT2
1059                       | GPSR4_SD3_DAT1
1060                       | GPSR4_SD3_DAT0
1061                       | GPSR4_SD3_CMD
1062                       | GPSR4_SD3_CLK
1063                       | GPSR4_SD2_DS
1064                       | GPSR4_SD2_DAT3
1065                       | GPSR4_SD2_DAT2
1066                       | GPSR4_SD2_DAT1
1067                       | GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
1068         pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
1069                       | GPSR5_MSIOF0_SS1
1070                       | GPSR5_MSIOF0_SYNC
1071                       | GPSR5_HRTS0
1072                       | GPSR5_HCTS0
1073                       | GPSR5_HTX0
1074                       | GPSR5_HRX0
1075                       | GPSR5_HSCK0
1076                       | GPSR5_RX2_A
1077                       | GPSR5_TX2_A
1078                       | GPSR5_SCK2
1079                       | GPSR5_RTS1_TANS
1080                       | GPSR5_CTS1
1081                       | GPSR5_TX1_A
1082                       | GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
1083         pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
1084                       | GPSR6_USB30_PWEN
1085                       | GPSR6_USB1_OVC
1086                       | GPSR6_USB1_PWEN
1087                       | GPSR6_USB0_OVC
1088                       | GPSR6_USB0_PWEN
1089                       | GPSR6_AUDIO_CLKB_B
1090                       | GPSR6_AUDIO_CLKA_A
1091                       | GPSR6_SSI_SDATA8
1092                       | GPSR6_SSI_SDATA7
1093                       | GPSR6_SSI_WS78
1094                       | GPSR6_SSI_SCK78
1095                       | GPSR6_SSI_WS6
1096                       | GPSR6_SSI_SCK6
1097                       | GPSR6_SSI_SDATA4
1098                       | GPSR6_SSI_WS4
1099                       | GPSR6_SSI_SCK4
1100                       | GPSR6_SSI_SDATA1_A
1101                       | GPSR6_SSI_SDATA0
1102                       | GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
1103         pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
1104                       | GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
1105
1106         /* initialize POC control register */
1107         pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
1108                       | POC_SD3_DAT7_33V
1109                       | POC_SD3_DAT6_33V
1110                       | POC_SD3_DAT5_33V
1111                       | POC_SD3_DAT4_33V
1112                       | POC_SD3_DAT3_33V
1113                       | POC_SD3_DAT2_33V
1114                       | POC_SD3_DAT1_33V
1115                       | POC_SD3_DAT0_33V
1116                       | POC_SD3_CMD_33V
1117                       | POC_SD3_CLK_33V
1118                       | POC_SD0_DAT3_33V
1119                       | POC_SD0_DAT2_33V
1120                       | POC_SD0_DAT1_33V
1121                       | POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
1122
1123         /* initialize DRV control register */
1124         reg = mmio_read_32(PFC_DRVCTRL0);
1125         reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3)
1126                | DRVCTRL0_QSPI0_MOSI_IO0(3)
1127                | DRVCTRL0_QSPI0_MISO_IO1(3)
1128                | DRVCTRL0_QSPI0_IO2(3)
1129                | DRVCTRL0_QSPI0_IO3(3)
1130                | DRVCTRL0_QSPI0_SSL(3)
1131                | DRVCTRL0_QSPI1_SPCLK(3)
1132                | DRVCTRL0_QSPI1_MOSI_IO0(3));
1133         pfc_reg_write(PFC_DRVCTRL0, reg);
1134         reg = mmio_read_32(PFC_DRVCTRL1);
1135         reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3)
1136                | DRVCTRL1_QSPI1_IO2(3)
1137                | DRVCTRL1_QSPI1_IO3(3)
1138                | DRVCTRL1_QSPI1_SS(3)
1139                | DRVCTRL1_RPC_INT(3)
1140                | DRVCTRL1_RPC_WP(3)
1141                | DRVCTRL1_RPC_RESET(3)
1142                | DRVCTRL1_AVB_RX_CTL(7));
1143         pfc_reg_write(PFC_DRVCTRL1, reg);
1144         reg = mmio_read_32(PFC_DRVCTRL2);
1145         reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7)
1146                | DRVCTRL2_AVB_RD0(7)
1147                | DRVCTRL2_AVB_RD1(7)
1148                | DRVCTRL2_AVB_RD2(7)
1149                | DRVCTRL2_AVB_RD3(7)
1150                | DRVCTRL2_AVB_TX_CTL(3)
1151                | DRVCTRL2_AVB_TXC(3)
1152                | DRVCTRL2_AVB_TD0(3));
1153         pfc_reg_write(PFC_DRVCTRL2, reg);
1154         reg = mmio_read_32(PFC_DRVCTRL3);
1155         reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(3)
1156                | DRVCTRL3_AVB_TD2(3)
1157                | DRVCTRL3_AVB_TD3(3)
1158                | DRVCTRL3_AVB_TXCREFCLK(7)
1159                | DRVCTRL3_AVB_MDIO(7)
1160                | DRVCTRL3_AVB_MDC(7)
1161                | DRVCTRL3_AVB_MAGIC(7)
1162                | DRVCTRL3_AVB_PHY_INT(7));
1163         pfc_reg_write(PFC_DRVCTRL3, reg);
1164         reg = mmio_read_32(PFC_DRVCTRL4);
1165         reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7)
1166                | DRVCTRL4_AVB_AVTP_MATCH(7)
1167                | DRVCTRL4_AVB_AVTP_CAPTURE(7)
1168                | DRVCTRL4_IRQ0(7)
1169                | DRVCTRL4_IRQ1(7)
1170                | DRVCTRL4_IRQ2(7)
1171                | DRVCTRL4_IRQ3(7)
1172                | DRVCTRL4_IRQ4(7));
1173         pfc_reg_write(PFC_DRVCTRL4, reg);
1174         reg = mmio_read_32(PFC_DRVCTRL5);
1175         reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7)
1176                | DRVCTRL5_PWM0(7)
1177                | DRVCTRL5_PWM1(7)
1178                | DRVCTRL5_PWM2(7)
1179                | DRVCTRL5_A0(3)
1180                | DRVCTRL5_A1(3)
1181                | DRVCTRL5_A2(3)
1182                | DRVCTRL5_A3(3));
1183         pfc_reg_write(PFC_DRVCTRL5, reg);
1184         reg = mmio_read_32(PFC_DRVCTRL6);
1185         reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(3)
1186                | DRVCTRL6_A5(3)
1187                | DRVCTRL6_A6(3)
1188                | DRVCTRL6_A7(3)
1189                | DRVCTRL6_A8(7)
1190                | DRVCTRL6_A9(7)
1191                | DRVCTRL6_A10(7)
1192                | DRVCTRL6_A11(7));
1193         pfc_reg_write(PFC_DRVCTRL6, reg);
1194         reg = mmio_read_32(PFC_DRVCTRL7);
1195         reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(3)
1196                | DRVCTRL7_A13(3)
1197                | DRVCTRL7_A14(3)
1198                | DRVCTRL7_A15(3)
1199                | DRVCTRL7_A16(3)
1200                | DRVCTRL7_A17(3)
1201                | DRVCTRL7_A18(3)
1202                | DRVCTRL7_A19(3));
1203         pfc_reg_write(PFC_DRVCTRL7, reg);
1204         reg = mmio_read_32(PFC_DRVCTRL8);
1205         reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7)
1206                | DRVCTRL8_CS0(7)
1207                | DRVCTRL8_CS1_A2(7)
1208                | DRVCTRL8_BS(7)
1209                | DRVCTRL8_RD(7)
1210                | DRVCTRL8_RD_W(7)
1211                | DRVCTRL8_WE0(7)
1212                | DRVCTRL8_WE1(7));
1213         pfc_reg_write(PFC_DRVCTRL8, reg);
1214         reg = mmio_read_32(PFC_DRVCTRL9);
1215         reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7)
1216                | DRVCTRL9_PRESETOU(7)
1217                | DRVCTRL9_D0(7)
1218                | DRVCTRL9_D1(7)
1219                | DRVCTRL9_D2(7)
1220                | DRVCTRL9_D3(7)
1221                | DRVCTRL9_D4(7)
1222                | DRVCTRL9_D5(7));
1223         pfc_reg_write(PFC_DRVCTRL9, reg);
1224         reg = mmio_read_32(PFC_DRVCTRL10);
1225         reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7)
1226                | DRVCTRL10_D7(7)
1227                | DRVCTRL10_D8(3)
1228                | DRVCTRL10_D9(3)
1229                | DRVCTRL10_D10(3)
1230                | DRVCTRL10_D11(3)
1231                | DRVCTRL10_D12(3)
1232                | DRVCTRL10_D13(3));
1233         pfc_reg_write(PFC_DRVCTRL10, reg);
1234         reg = mmio_read_32(PFC_DRVCTRL11);
1235         reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(3)
1236                | DRVCTRL11_D15(3)
1237                | DRVCTRL11_AVS1(7)
1238                | DRVCTRL11_AVS2(7)
1239                | DRVCTRL11_HDMI0_CEC(7)
1240                | DRVCTRL11_HDMI1_CEC(7)
1241                | DRVCTRL11_DU_DOTCLKIN0(3)
1242                | DRVCTRL11_DU_DOTCLKIN1(3));
1243         pfc_reg_write(PFC_DRVCTRL11, reg);
1244         reg = mmio_read_32(PFC_DRVCTRL12);
1245         reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3)
1246                | DRVCTRL12_DU_DOTCLKIN3(3)
1247                | DRVCTRL12_DU_FSCLKST(3)
1248                | DRVCTRL12_DU_TMS(3));
1249         pfc_reg_write(PFC_DRVCTRL12, reg);
1250         reg = mmio_read_32(PFC_DRVCTRL13);
1251         reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3)
1252                | DRVCTRL13_ASEBRK(3)
1253                | DRVCTRL13_SD0_CLK(7)
1254                | DRVCTRL13_SD0_CMD(7)
1255                | DRVCTRL13_SD0_DAT0(7)
1256                | DRVCTRL13_SD0_DAT1(7)
1257                | DRVCTRL13_SD0_DAT2(7)
1258                | DRVCTRL13_SD0_DAT3(7));
1259         pfc_reg_write(PFC_DRVCTRL13, reg);
1260         reg = mmio_read_32(PFC_DRVCTRL14);
1261         reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7)
1262                | DRVCTRL14_SD1_CMD(7)
1263                | DRVCTRL14_SD1_DAT0(5)
1264                | DRVCTRL14_SD1_DAT1(5)
1265                | DRVCTRL14_SD1_DAT2(5)
1266                | DRVCTRL14_SD1_DAT3(5)
1267                | DRVCTRL14_SD2_CLK(5)
1268                | DRVCTRL14_SD2_CMD(5));
1269         pfc_reg_write(PFC_DRVCTRL14, reg);
1270         reg = mmio_read_32(PFC_DRVCTRL15);
1271         reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(5)
1272                | DRVCTRL15_SD2_DAT1(5)
1273                | DRVCTRL15_SD2_DAT2(5)
1274                | DRVCTRL15_SD2_DAT3(5)
1275                | DRVCTRL15_SD2_DS(5)
1276                | DRVCTRL15_SD3_CLK(7)
1277                | DRVCTRL15_SD3_CMD(7)
1278                | DRVCTRL15_SD3_DAT0(7));
1279         pfc_reg_write(PFC_DRVCTRL15, reg);
1280         reg = mmio_read_32(PFC_DRVCTRL16);
1281         reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7)
1282                | DRVCTRL16_SD3_DAT2(7)
1283                | DRVCTRL16_SD3_DAT3(7)
1284                | DRVCTRL16_SD3_DAT4(7)
1285                | DRVCTRL16_SD3_DAT5(7)
1286                | DRVCTRL16_SD3_DAT6(7)
1287                | DRVCTRL16_SD3_DAT7(7)
1288                | DRVCTRL16_SD3_DS(7));
1289         pfc_reg_write(PFC_DRVCTRL16, reg);
1290         reg = mmio_read_32(PFC_DRVCTRL17);
1291         reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7)
1292                | DRVCTRL17_SD0_WP(7)
1293                | DRVCTRL17_SD1_CD(7)
1294                | DRVCTRL17_SD1_WP(7)
1295                | DRVCTRL17_SCK0(7)
1296                | DRVCTRL17_RX0(7)
1297                | DRVCTRL17_TX0(7)
1298                | DRVCTRL17_CTS0(7));
1299         pfc_reg_write(PFC_DRVCTRL17, reg);
1300         reg = mmio_read_32(PFC_DRVCTRL18);
1301         reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7)
1302                | DRVCTRL18_RX1(7)
1303                | DRVCTRL18_TX1(7)
1304                | DRVCTRL18_CTS1(7)
1305                | DRVCTRL18_RTS1_TANS(7)
1306                | DRVCTRL18_SCK2(7)
1307                | DRVCTRL18_TX2(7)
1308                | DRVCTRL18_RX2(7));
1309         pfc_reg_write(PFC_DRVCTRL18, reg);
1310         reg = mmio_read_32(PFC_DRVCTRL19);
1311         reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7)
1312                | DRVCTRL19_HRX0(7)
1313                | DRVCTRL19_HTX0(7)
1314                | DRVCTRL19_HCTS0(7)
1315                | DRVCTRL19_HRTS0(7)
1316                | DRVCTRL19_MSIOF0_SCK(7)
1317                | DRVCTRL19_MSIOF0_SYNC(7)
1318                | DRVCTRL19_MSIOF0_SS1(7));
1319         pfc_reg_write(PFC_DRVCTRL19, reg);
1320         reg = mmio_read_32(PFC_DRVCTRL20);
1321         reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7)
1322                | DRVCTRL20_MSIOF0_SS2(7)
1323                | DRVCTRL20_MSIOF0_RXD(7)
1324                | DRVCTRL20_MLB_CLK(7)
1325                | DRVCTRL20_MLB_SIG(7)
1326                | DRVCTRL20_MLB_DAT(7)
1327                | DRVCTRL20_MLB_REF(7)
1328                | DRVCTRL20_SSI_SCK0129(7));
1329         pfc_reg_write(PFC_DRVCTRL20, reg);
1330         reg = mmio_read_32(PFC_DRVCTRL21);
1331         reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7)
1332                | DRVCTRL21_SSI_SDATA0(7)
1333                | DRVCTRL21_SSI_SDATA1(7)
1334                | DRVCTRL21_SSI_SDATA2(7)
1335                | DRVCTRL21_SSI_SCK34(7)
1336                | DRVCTRL21_SSI_WS34(7)
1337                | DRVCTRL21_SSI_SDATA3(7)
1338                | DRVCTRL21_SSI_SCK4(7));
1339         pfc_reg_write(PFC_DRVCTRL21, reg);
1340         reg = mmio_read_32(PFC_DRVCTRL22);
1341         reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7)
1342                | DRVCTRL22_SSI_SDATA4(7)
1343                | DRVCTRL22_SSI_SCK5(7)
1344                | DRVCTRL22_SSI_WS5(7)
1345                | DRVCTRL22_SSI_SDATA5(7)
1346                | DRVCTRL22_SSI_SCK6(7)
1347                | DRVCTRL22_SSI_WS6(7)
1348                | DRVCTRL22_SSI_SDATA6(7));
1349         pfc_reg_write(PFC_DRVCTRL22, reg);
1350         reg = mmio_read_32(PFC_DRVCTRL23);
1351         reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7)
1352                | DRVCTRL23_SSI_WS78(7)
1353                | DRVCTRL23_SSI_SDATA7(7)
1354                | DRVCTRL23_SSI_SDATA8(7)
1355                | DRVCTRL23_SSI_SDATA9(7)
1356                | DRVCTRL23_AUDIO_CLKA(7)
1357                | DRVCTRL23_AUDIO_CLKB(7)
1358                | DRVCTRL23_USB0_PWEN(7));
1359         pfc_reg_write(PFC_DRVCTRL23, reg);
1360         reg = mmio_read_32(PFC_DRVCTRL24);
1361         reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7)
1362                | DRVCTRL24_USB1_PWEN(7)
1363                | DRVCTRL24_USB1_OVC(7)
1364                | DRVCTRL24_USB30_PWEN(7)
1365                | DRVCTRL24_USB30_OVC(7)
1366                | DRVCTRL24_USB31_PWEN(7)
1367                | DRVCTRL24_USB31_OVC(7));
1368         pfc_reg_write(PFC_DRVCTRL24, reg);
1369
1370         /* initialize LSI pin pull-up/down control */
1371         pfc_reg_write(PFC_PUD0, 0x00005FBFU);
1372         pfc_reg_write(PFC_PUD1, 0x00300FFEU);
1373         pfc_reg_write(PFC_PUD2, 0x330001E6U);
1374         pfc_reg_write(PFC_PUD3, 0x000002E0U);
1375         pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
1376         pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
1377         pfc_reg_write(PFC_PUD6, 0x00000055U);
1378
1379         /* initialize LSI pin pull-enable register */
1380         pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
1381         pfc_reg_write(PFC_PUEN1, 0x00100234U);
1382         pfc_reg_write(PFC_PUEN2, 0x000004C4U);
1383         pfc_reg_write(PFC_PUEN3, 0x00000200U);
1384         pfc_reg_write(PFC_PUEN4, 0x3E000000U);
1385         pfc_reg_write(PFC_PUEN5, 0x1F000805U);
1386         pfc_reg_write(PFC_PUEN6, 0x00000006U);
1387
1388         /* initialize positive/negative logic select */
1389         mmio_write_32(GPIO_POSNEG0, 0x00000000U);
1390         mmio_write_32(GPIO_POSNEG1, 0x00000000U);
1391         mmio_write_32(GPIO_POSNEG2, 0x00000000U);
1392         mmio_write_32(GPIO_POSNEG3, 0x00000000U);
1393         mmio_write_32(GPIO_POSNEG4, 0x00000000U);
1394         mmio_write_32(GPIO_POSNEG5, 0x00000000U);
1395         mmio_write_32(GPIO_POSNEG6, 0x00000000U);
1396
1397         /* initialize general IO/interrupt switching */
1398         mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
1399         mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
1400         mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
1401         mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
1402         mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
1403         mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
1404         mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
1405
1406         /* initialize general output register */
1407         mmio_write_32(GPIO_OUTDT1, 0x00000000U);
1408         mmio_write_32(GPIO_OUTDT2, 0x00000400U);
1409         mmio_write_32(GPIO_OUTDT3, 0x0000C000U);
1410         mmio_write_32(GPIO_OUTDT5, 0x00000006U);
1411         mmio_write_32(GPIO_OUTDT6, 0x00003880U);
1412
1413         /* initialize general input/output switching */
1414         mmio_write_32(GPIO_INOUTSEL0, 0x00000000U);
1415         mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U);
1416         mmio_write_32(GPIO_INOUTSEL2, 0x00000400U);
1417         mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U);
1418         mmio_write_32(GPIO_INOUTSEL4, 0x00000000U);
1419         mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
1420         mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
1421 }