drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c

   1 /*
   2  * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <stdint.h>
   8
   9 #include <common/debug.h>
  10
  11 #include "../qos_common.h"
  12 #include "../qos_reg.h"
  13 #include "qos_init_e3_v10.h"
  14
  15 #define RCAR_QOS_VERSION                "rev.0.02"
  16
  17 #define QOSCTRL_EARLYR                  (QOS_BASE1 + 0x0060U)
  18 #define QOSCTRL_FSS                     (QOS_BASE1 + 0x0048U)
  19
  20 #define REF_ARS_ARBSTOPCYCLE_E3 (((SL_INIT_SSLOTCLK_E3) - 5U) << 16U)
  21
  22 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
  23
  24 #if RCAR_REF_INT == RCAR_REF_DEFAULT
  25 #include "qos_init_e3_v10_mstat390.h"
  26 #else
  27 #include "qos_init_e3_v10_mstat780.h"
  28 #endif
  29
  30 #endif
  31
  32 static void dbsc_setting(void)
  33 {
  34         /* Register write enable */
  35         io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
  36
  37         /* BUFCAM settings */
  38         io_write_32(DBSC_DBCAM0CNF1, 0x00043218);
  39         io_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
  40         io_write_32(DBSC_DBSCHCNT0, 0x000F0037);
  41         io_write_32(DBSC_DBSCHSZ0, 0x00000001);
  42         io_write_32(DBSC_DBSCHRW0, 0x22421111);
  43
  44         /* DDR3 */
  45         io_write_32(DBSC_SCFCTST2, 0x012F1123);
  46
  47         /* QoS Settings */
  48         io_write_32(DBSC_DBSCHQOS00, 0x00000F00);
  49         io_write_32(DBSC_DBSCHQOS01, 0x00000B00);
  50         io_write_32(DBSC_DBSCHQOS02, 0x00000000);
  51         io_write_32(DBSC_DBSCHQOS03, 0x00000000);
  52         io_write_32(DBSC_DBSCHQOS40, 0x00000300);
  53         io_write_32(DBSC_DBSCHQOS41, 0x000002F0);
  54         io_write_32(DBSC_DBSCHQOS42, 0x00000200);
  55         io_write_32(DBSC_DBSCHQOS43, 0x00000100);
  56         io_write_32(DBSC_DBSCHQOS90, 0x00000100);
  57         io_write_32(DBSC_DBSCHQOS91, 0x000000F0);
  58         io_write_32(DBSC_DBSCHQOS92, 0x000000A0);
  59         io_write_32(DBSC_DBSCHQOS93, 0x00000040);
  60         io_write_32(DBSC_DBSCHQOS130, 0x00000100);
  61         io_write_32(DBSC_DBSCHQOS131, 0x000000F0);
  62         io_write_32(DBSC_DBSCHQOS132, 0x000000A0);
  63         io_write_32(DBSC_DBSCHQOS133, 0x00000040);
  64         io_write_32(DBSC_DBSCHQOS140, 0x000000C0);
  65         io_write_32(DBSC_DBSCHQOS141, 0x000000B0);
  66         io_write_32(DBSC_DBSCHQOS142, 0x00000080);
  67         io_write_32(DBSC_DBSCHQOS143, 0x00000040);
  68         io_write_32(DBSC_DBSCHQOS150, 0x00000040);
  69         io_write_32(DBSC_DBSCHQOS151, 0x00000030);
  70         io_write_32(DBSC_DBSCHQOS152, 0x00000020);
  71         io_write_32(DBSC_DBSCHQOS153, 0x00000010);
  72
  73         /* Register write protect */
  74         io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
  75 }
  76
  77 void qos_init_e3_v10(void)
  78 {
  79         dbsc_setting();
  80
  81         /* DRAM Split Address mapping */
  82 #if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
  83 #if RCAR_LSI == RCAR_E3
  84 #error "Don't set DRAM Split 4ch(E3)"
  85 #else
  86         ERROR("DRAM Split 4ch not supported.(E3)");
  87         panic();
  88 #endif
  89 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
  90 #if RCAR_LSI == RCAR_E3
  91 #error "Don't set DRAM Split 2ch(E3)"
  92 #else
  93         ERROR("DRAM Split 2ch not supported.(E3)");
  94         panic();
  95 #endif
  96 #else
  97         NOTICE("BL2: DRAM Split is OFF\n");
  98 #endif
  99
 100 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
 101 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
 102         NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
 103 #endif
 104
 105 #if RCAR_REF_INT == RCAR_REF_DEFAULT
 106         NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
 107 #else
 108         NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
 109 #endif
 110
 111         io_write_32(QOSCTRL_RAS, 0x00000020U);
 112         io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
 113         io_write_32(QOSCTRL_DANT, 0x00100804U);
 114         io_write_32(QOSCTRL_FSS, 0x0000000AU);
 115         io_write_32(QOSCTRL_INSFC, 0x06330001U);
 116         io_write_32(QOSCTRL_EARLYR, 0x00000000U);
 117         io_write_32(QOSCTRL_RACNT0, 0x00010003U);
 118
 119         io_write_32(QOSCTRL_SL_INIT,
 120                     SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
 121                     SL_INIT_SSLOTCLK_E3);
 122         io_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_E3);
 123
 124         {
 125                 uint32_t i;
 126
 127                 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
 128                         io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
 129                         io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
 130                 }
 131                 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
 132                         io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
 133                         io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
 134                 }
 135         }
 136
 137         /* 3DG bus Leaf setting */
 138         io_write_32(GPU_ACT_GRD, 0x00001234U);
 139         io_write_32(GPU_ACT0, 0x00000000U);
 140         io_write_32(GPU_ACT1, 0x00000000U);
 141         io_write_32(GPU_ACT2, 0x00000000U);
 142         io_write_32(GPU_ACT3, 0x00000000U);
 143         io_write_32(GPU_ACT_GRD, 0x00000000U);
 144
 145         /* RT bus Leaf setting */
 146         io_write_32(RT_ACT0, 0x00000000U);
 147         io_write_32(RT_ACT1, 0x00000000U);
 148
 149         /* CCI bus Leaf setting */
 150         io_write_32(CPU_ACT0, 0x00000003U);
 151         io_write_32(CPU_ACT1, 0x00000003U);
 152
 153         io_write_32(QOSCTRL_RAEN, 0x00000001U);
 154
 155         io_write_32(QOSCTRL_STATQC, 0x00000001U);
 156 #else
 157         NOTICE("BL2: QoS is None\n");
 158
 159         io_write_32(QOSCTRL_RAEN, 0x00000001U);
 160 #endif
 161 }