drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c

   1 /*
   2  * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <stdint.h>
   8 #include <debug.h>
   9 #include "../qos_common.h"
  10 #include "../qos_reg.h"
  11 #include "qos_init_h3n_v30.h"
  12
  13 #define RCAR_QOS_VERSION                "rev.0.03"
  14
  15 #define QOSCTRL_FSS                     (QOS_BASE1 + 0x0048U)
  16
  17 #define QOSWT_TIME_BANK0                                (20000000U)     /* unit:ns */
  18
  19 #define QOSWT_WTEN_ENABLE                               (0x1U)
  20
  21 #define QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N        (SL_INIT_SSLOTCLK_H3N - 0x5U)
  22
  23 #define OSWT_WTREF_SLOT0_EN_REQ1_SLOT   (3U)
  24 #define OSWT_WTREF_SLOT0_EN_REQ2_SLOT   (9U)
  25 #define QOSWT_WTREF_SLOT0_EN                    ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
  26 #define QOSWT_WTREF_SLOT1_EN                    ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
  27
  28 #define QOSWT_WTSET0_REQ_SSLOT0                 (5U)
  29 #define WT_BASE_SUB_SLOT_NUM0                   (12U)
  30 #define QOSWT_WTSET0_PERIOD0_H3N                ((QOSWT_TIME_BANK0/QOSWT_WTSET0_CYCLE_H3N)-1U)
  31 #define QOSWT_WTSET0_SSLOT0                             (QOSWT_WTSET0_REQ_SSLOT0 -1U)
  32 #define QOSWT_WTSET0_SLOTSLOT0                  (WT_BASE_SUB_SLOT_NUM0 -1U)
  33
  34 #define QOSWT_WTSET1_PERIOD1_H3N                (QOSWT_WTSET0_PERIOD0_H3N)
  35 #define QOSWT_WTSET1_SSLOT1                             (QOSWT_WTSET0_SSLOT0)
  36 #define QOSWT_WTSET1_SLOTSLOT1                  (QOSWT_WTSET0_SLOTSLOT0)
  37
  38 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
  39
  40 #if RCAR_REF_INT == RCAR_REF_DEFAULT
  41 #include "qos_init_h3n_v30_mstat195.h"
  42 #else
  43 #include "qos_init_h3n_v30_mstat390.h"
  44 #endif
  45
  46 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
  47
  48 #if RCAR_REF_INT == RCAR_REF_DEFAULT
  49 #include "qos_init_h3n_v30_qoswt195.h"
  50 #else
  51 #include "qos_init_h3n_v30_qoswt390.h"
  52 #endif
  53
  54 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
  55
  56 #endif
  57
  58 static void dbsc_setting(void)
  59 {
  60         uint32_t md = 0;
  61
  62         /* Register write enable */
  63         io_write_32(DBSC_DBSYSCNT0, 0x00001234U);
  64
  65         /* BUFCAM settings */
  66         io_write_32(DBSC_DBCAM0CNF1, 0x00043218U);      /* dbcam0cnf1 */
  67         io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);      /* dbcam0cnf2 */
  68         io_write_32(DBSC_DBCAM0CNF3, 0x00000000U);      /* dbcam0cnf3 */
  69         io_write_32(DBSC_DBSCHCNT0, 0x000F0037U);       /* dbschcnt0 */
  70         io_write_32(DBSC_DBSCHSZ0, 0x00000001U);        /* dbschsz0 */
  71         io_write_32(DBSC_DBSCHRW0, 0x22421111U);        /* dbschrw0 */
  72
  73         md = (*((volatile uint32_t *)RST_MODEMR) & 0x000A0000) >> 17;
  74
  75         switch (md) {
  76         case 0x0:
  77                 /* DDR3200 */
  78                 io_write_32(DBSC_SCFCTST2, 0x012F1123U);
  79                 break;
  80         case 0x1:               /* MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) */
  81                 /* DDR2800 */
  82                 io_write_32(DBSC_SCFCTST2, 0x012F1123U);
  83                 break;
  84         case 0x4:               /* MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) */
  85                 /* DDR2400 */
  86                 io_write_32(DBSC_SCFCTST2, 0x012F1123U);
  87                 break;
  88         default:                /* MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) */
  89                 /* DDR1600 */
  90                 io_write_32(DBSC_SCFCTST2, 0x012F1123U);
  91                 break;
  92         }
  93
  94         /* QoS Settings */
  95         io_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
  96         io_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
  97         io_write_32(DBSC_DBSCHQOS02, 0x00000000U);
  98         io_write_32(DBSC_DBSCHQOS03, 0x00000000U);
  99         io_write_32(DBSC_DBSCHQOS40, 0x00000300U);
 100         io_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
 101         io_write_32(DBSC_DBSCHQOS42, 0x00000200U);
 102         io_write_32(DBSC_DBSCHQOS43, 0x00000100U);
 103         io_write_32(DBSC_DBSCHQOS90, 0x00000100U);
 104         io_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
 105         io_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
 106         io_write_32(DBSC_DBSCHQOS93, 0x00000040U);
 107         io_write_32(DBSC_DBSCHQOS120, 0x00000040U);
 108         io_write_32(DBSC_DBSCHQOS121, 0x00000030U);
 109         io_write_32(DBSC_DBSCHQOS122, 0x00000020U);
 110         io_write_32(DBSC_DBSCHQOS123, 0x00000010U);
 111         io_write_32(DBSC_DBSCHQOS130, 0x00000100U);
 112         io_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
 113         io_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
 114         io_write_32(DBSC_DBSCHQOS133, 0x00000040U);
 115         io_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
 116         io_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
 117         io_write_32(DBSC_DBSCHQOS142, 0x00000080U);
 118         io_write_32(DBSC_DBSCHQOS143, 0x00000040U);
 119         io_write_32(DBSC_DBSCHQOS150, 0x00000040U);
 120         io_write_32(DBSC_DBSCHQOS151, 0x00000030U);
 121         io_write_32(DBSC_DBSCHQOS152, 0x00000020U);
 122         io_write_32(DBSC_DBSCHQOS153, 0x00000010U);
 123
 124         /* Register write protect */
 125         io_write_32(DBSC_DBSYSCNT0, 0x00000000U);
 126 }
 127
 128 void qos_init_h3n_v30(void)
 129 {
 130         unsigned int split_area;
 131         dbsc_setting();
 132
 133         /* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for H3N */
 134         split_area = 0x1CU;
 135
 136         /* DRAM Split Address mapping */
 137 #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
 138 #if RCAR_LSI == RCAR_H3N
 139 #error "Don't set DRAM Split 4ch(H3N)"
 140 #else
 141         ERROR("DRAM Split 4ch not supported.(H3N)");
 142         panic();
 143 #endif
 144 #elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
 145     (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
 146         NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
 147
 148         io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
 149         io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT
 150                     | ADSPLCR0_SPLITSEL(0xFFU)
 151                     | ADSPLCR0_AREA(split_area)
 152                     | ADSPLCR0_SWP);
 153         io_write_32(AXI_ADSPLCR2, 0x00001004U);
 154         io_write_32(AXI_ADSPLCR3, 0x00000000U);
 155 #else
 156         io_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
 157         NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
 158 #endif
 159
 160 #if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
 161 #if RCAR_QOS_TYPE  == RCAR_QOS_TYPE_DEFAULT
 162         NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
 163 #endif
 164
 165 #if RCAR_REF_INT == RCAR_REF_DEFAULT
 166         NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
 167 #else
 168         NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
 169 #endif
 170
 171 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
 172         NOTICE("BL2: Periodic Write DQ Training\n");
 173 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
 174
 175         io_write_32(QOSCTRL_RAS, 0x00000044U);
 176         io_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
 177         io_write_32(QOSCTRL_DANT, 0x0020100AU);
 178         io_write_32(QOSCTRL_FSS, 0x0000000AU);
 179         io_write_32(QOSCTRL_INSFC, 0x06330001U);
 180         io_write_32(QOSCTRL_RACNT0, 0x00010003U);
 181
 182         /* GPU Boost Mode */
 183         io_write_32(QOSCTRL_STATGEN0, 0x00000001U);
 184
 185         io_write_32(QOSCTRL_SL_INIT,
 186                     SL_INIT_REFFSSLOT | SL_INIT_SLOTSSLOT |
 187                     SL_INIT_SSLOTCLK_H3N);
 188         io_write_32(QOSCTRL_REF_ARS,
 189                     ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_H3N << 16)));
 190
 191         {
 192                 uint32_t i;
 193
 194                 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
 195                         io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]);
 196                         io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]);
 197                 }
 198                 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
 199                         io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]);
 200                         io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]);
 201                 }
 202 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
 203                 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
 204                         io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8,
 205                                     qoswt_fix[i]);
 206                         io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8,
 207                                     qoswt_fix[i]);
 208                 }
 209                 for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
 210                         io_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8, qoswt_be[i]);
 211                         io_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8, qoswt_be[i]);
 212                 }
 213 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
 214         }
 215
 216         /* AXI setting */
 217         io_write_32(AXI_MMCR, 0x00010008U);
 218         io_write_32(AXI_TR3CR, 0x00010000U);
 219         io_write_32(AXI_TR4CR, 0x00010000U);
 220
 221         /* 3DG bus Leaf setting */
 222         io_write_32(GPU_ACT_GRD, 0x00001234U);
 223         io_write_32(GPU_ACT0, 0x00000000U);
 224         io_write_32(GPU_ACT1, 0x00000000U);
 225         io_write_32(GPU_ACT2, 0x00000000U);
 226         io_write_32(GPU_ACT3, 0x00000000U);
 227         io_write_32(GPU_ACT_GRD, 0x00000000U);
 228
 229         /* RT bus Leaf setting */
 230         io_write_32(RT_ACT0, 0x00000000U);
 231         io_write_32(RT_ACT1, 0x00000000U);
 232
 233         /* CCI bus Leaf setting */
 234         io_write_32(CPU_ACT0, 0x00000003U);
 235         io_write_32(CPU_ACT1, 0x00000003U);
 236         io_write_32(CPU_ACT2, 0x00000003U);
 237         io_write_32(CPU_ACT3, 0x00000003U);
 238
 239         io_write_32(QOSCTRL_RAEN, 0x00000001U);
 240
 241 #if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
 242         /*  re-write training setting */
 243         io_write_32(QOSWT_WTREF,
 244                     ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
 245         io_write_32(QOSWT_WTSET0,
 246                     ((QOSWT_WTSET0_PERIOD0_H3N << 16) |
 247                      (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
 248         io_write_32(QOSWT_WTSET1,
 249                     ((QOSWT_WTSET1_PERIOD1_H3N << 16) |
 250                      (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
 251
 252         io_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
 253 #endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
 254
 255         io_write_32(QOSCTRL_STATQC, 0x00000001U);
 256 #else
 257         NOTICE("BL2: QoS is None\n");
 258
 259         io_write_32(QOSCTRL_RAEN, 0x00000001U);
 260 #endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
 261 }