1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 #include <linux/compiler.h>
12 #include <usb/ehci-ci.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/sys_proto.h>
19 #include <asm/mach-types.h>
20 #include <power/regulator.h>
21 #include <linux/usb/otg.h>
25 DECLARE_GLOBAL_DATA_PTR
;
27 #define USB_OTGREGS_OFFSET 0x000
28 #define USB_H1REGS_OFFSET 0x200
29 #define USB_H2REGS_OFFSET 0x400
30 #define USB_H3REGS_OFFSET 0x600
31 #define USB_OTHERREGS_OFFSET 0x800
33 #define USB_H1_CTRL_OFFSET 0x04
35 #define USBPHY_CTRL 0x00000030
36 #define USBPHY_CTRL_SET 0x00000034
37 #define USBPHY_CTRL_CLR 0x00000038
38 #define USBPHY_CTRL_TOG 0x0000003c
40 #define USBPHY_PWD 0x00000000
41 #define USBPHY_CTRL_SFTRST 0x80000000
42 #define USBPHY_CTRL_CLKGATE 0x40000000
43 #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
44 #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
45 #define USBPHY_CTRL_OTG_ID 0x08000000
47 #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
48 #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
50 #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
51 #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
52 #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
53 #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
55 #define USBNC_OFFSET 0x200
56 #define USBNC_PHY_STATUS_OFFSET 0x23C
57 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
58 #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
59 #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
60 #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
61 #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
64 #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
65 #define UCMD_RESET (1 << 1) /* controller reset */
67 #if defined(CONFIG_MX6)
68 static const unsigned phy_bases
[] = {
73 static void usb_internal_phy_clock_gate(int index
, int on
)
75 void __iomem
*phy_reg
;
77 if (index
>= ARRAY_SIZE(phy_bases
))
80 phy_reg
= (void __iomem
*)phy_bases
[index
];
81 phy_reg
+= on
? USBPHY_CTRL_CLR
: USBPHY_CTRL_SET
;
82 writel(USBPHY_CTRL_CLKGATE
, phy_reg
);
85 static void usb_power_config(int index
)
87 struct anatop_regs __iomem
*anatop
=
88 (struct anatop_regs __iomem
*)ANATOP_BASE_ADDR
;
89 void __iomem
*chrg_detect
;
90 void __iomem
*pll_480_ctrl_clr
;
91 void __iomem
*pll_480_ctrl_set
;
95 chrg_detect
= &anatop
->usb1_chrg_detect
;
96 pll_480_ctrl_clr
= &anatop
->usb1_pll_480_ctrl_clr
;
97 pll_480_ctrl_set
= &anatop
->usb1_pll_480_ctrl_set
;
100 chrg_detect
= &anatop
->usb2_chrg_detect
;
101 pll_480_ctrl_clr
= &anatop
->usb2_pll_480_ctrl_clr
;
102 pll_480_ctrl_set
= &anatop
->usb2_pll_480_ctrl_set
;
108 * Some phy and power's special controls
109 * 1. The external charger detector needs to be disabled
110 * or the signal at DP will be poor
111 * 2. The PLL's power and output to usb
112 * is totally controlled by IC, so the Software only needs
113 * to enable them at initializtion.
115 writel(ANADIG_USB2_CHRG_DETECT_EN_B
|
116 ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B
,
119 writel(ANADIG_USB2_PLL_480_CTRL_BYPASS
,
122 writel(ANADIG_USB2_PLL_480_CTRL_ENABLE
|
123 ANADIG_USB2_PLL_480_CTRL_POWER
|
124 ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS
,
128 /* Return 0 : host node, <>0 : device mode */
129 static int usb_phy_enable(int index
, struct usb_ehci
*ehci
)
131 void __iomem
*phy_reg
;
132 void __iomem
*phy_ctrl
;
133 void __iomem
*usb_cmd
;
136 if (index
>= ARRAY_SIZE(phy_bases
))
139 phy_reg
= (void __iomem
*)phy_bases
[index
];
140 phy_ctrl
= (void __iomem
*)(phy_reg
+ USBPHY_CTRL
);
141 usb_cmd
= (void __iomem
*)&ehci
->usbcmd
;
143 /* Stop then Reset */
144 clrbits_le32(usb_cmd
, UCMD_RUN_STOP
);
145 ret
= wait_for_bit_le32(usb_cmd
, UCMD_RUN_STOP
, false, 10000, false);
149 setbits_le32(usb_cmd
, UCMD_RESET
);
150 ret
= wait_for_bit_le32(usb_cmd
, UCMD_RESET
, false, 10000, false);
154 /* Reset USBPHY module */
155 setbits_le32(phy_ctrl
, USBPHY_CTRL_SFTRST
);
158 /* Remove CLKGATE and SFTRST */
159 clrbits_le32(phy_ctrl
, USBPHY_CTRL_CLKGATE
| USBPHY_CTRL_SFTRST
);
162 /* Power up the PHY */
163 writel(0, phy_reg
+ USBPHY_PWD
);
164 /* enable FS/LS device */
165 setbits_le32(phy_ctrl
, USBPHY_CTRL_ENUTMILEVEL2
|
166 USBPHY_CTRL_ENUTMILEVEL3
);
171 int usb_phy_mode(int port
)
173 void __iomem
*phy_reg
;
174 void __iomem
*phy_ctrl
;
177 phy_reg
= (void __iomem
*)phy_bases
[port
];
178 phy_ctrl
= (void __iomem
*)(phy_reg
+ USBPHY_CTRL
);
180 val
= readl(phy_ctrl
);
182 if (val
& USBPHY_CTRL_OTG_ID
)
183 return USB_INIT_DEVICE
;
185 return USB_INIT_HOST
;
188 /* Base address for this IP block is 0x02184800 */
190 u32 ctrl
[4]; /* otg/host1-3 */
196 #elif defined(CONFIG_MX7)
211 static void usb_power_config(int index
)
213 struct usbnc_regs
*usbnc
= (struct usbnc_regs
*)(USB_BASE_ADDR
+
214 (0x10000 * index
) + USBNC_OFFSET
);
215 void __iomem
*phy_cfg2
= (void __iomem
*)(&usbnc
->phy_cfg2
);
216 void __iomem
*ctrl
= (void __iomem
*)(&usbnc
->ctrl1
);
219 * Clear the ACAENB to enable usb_otg_id detection,
220 * otherwise it is the ACA detection enabled.
222 clrbits_le32(phy_cfg2
, USBNC_PHYCFG2_ACAENB
);
224 /* Set power polarity to high active */
225 #ifdef CONFIG_MXC_USB_OTG_HACTIVE
226 setbits_le32(ctrl
, UCTRL_PWR_POL
);
228 clrbits_le32(ctrl
, UCTRL_PWR_POL
);
232 int usb_phy_mode(int port
)
234 struct usbnc_regs
*usbnc
= (struct usbnc_regs
*)(USB_BASE_ADDR
+
235 (0x10000 * port
) + USBNC_OFFSET
);
236 void __iomem
*status
= (void __iomem
*)(&usbnc
->phy_status
);
241 if (val
& USBNC_PHYSTATUS_ID_DIG
)
242 return USB_INIT_DEVICE
;
244 return USB_INIT_HOST
;
248 static void usb_oc_config(int index
)
250 #if defined(CONFIG_MX6)
251 struct usbnc_regs
*usbnc
= (struct usbnc_regs
*)(USB_BASE_ADDR
+
252 USB_OTHERREGS_OFFSET
);
253 void __iomem
*ctrl
= (void __iomem
*)(&usbnc
->ctrl
[index
]);
254 #elif defined(CONFIG_MX7)
255 struct usbnc_regs
*usbnc
= (struct usbnc_regs
*)(USB_BASE_ADDR
+
256 (0x10000 * index
) + USBNC_OFFSET
);
257 void __iomem
*ctrl
= (void __iomem
*)(&usbnc
->ctrl1
);
260 #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
261 /* mx6qarm2 seems to required a different setting*/
262 clrbits_le32(ctrl
, UCTRL_OVER_CUR_POL
);
264 setbits_le32(ctrl
, UCTRL_OVER_CUR_POL
);
267 setbits_le32(ctrl
, UCTRL_OVER_CUR_DIS
);
271 * board_usb_phy_mode - override usb phy mode
272 * @port: usb host/otg port
274 * Target board specific, override usb_phy_mode.
275 * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
276 * left disconnected in this case usb_phy_mode will not be able to identify
277 * the phy mode that usb port is used.
278 * Machine file overrides board_usb_phy_mode.
280 * Return: USB_INIT_DEVICE or USB_INIT_HOST
282 int __weak
board_usb_phy_mode(int port
)
284 return usb_phy_mode(port
);
288 * board_ehci_hcd_init - set usb vbus voltage
289 * @port: usb otg port
291 * Target board specific, setup iomux pad to setup supply vbus voltage
292 * for usb otg port. Machine board file overrides board_ehci_hcd_init
296 int __weak
board_ehci_hcd_init(int port
)
302 * board_ehci_power - enables/disables usb vbus voltage
303 * @port: usb otg port
304 * @on: on/off vbus voltage
306 * Enables/disables supply vbus voltage for usb otg port.
307 * Machine board file overrides board_ehci_power
311 int __weak
board_ehci_power(int port
, int on
)
316 int ehci_mx6_common_init(struct usb_ehci
*ehci
, int index
)
320 enable_usboh3_clk(1);
323 /* Do board specific initialization */
324 ret
= board_ehci_hcd_init(index
);
328 usb_power_config(index
);
329 usb_oc_config(index
);
331 #if defined(CONFIG_MX6)
332 usb_internal_phy_clock_gate(index
, 1);
333 usb_phy_enable(index
, ehci
);
339 #if !CONFIG_IS_ENABLED(DM_USB)
340 int ehci_hcd_init(int index
, enum usb_init_type init
,
341 struct ehci_hccr
**hccr
, struct ehci_hcor
**hcor
)
343 enum usb_init_type type
;
344 #if defined(CONFIG_MX6)
345 u32 controller_spacing
= 0x200;
346 #elif defined(CONFIG_MX7)
347 u32 controller_spacing
= 0x10000;
349 struct usb_ehci
*ehci
= (struct usb_ehci
*)(USB_BASE_ADDR
+
350 (controller_spacing
* index
));
356 ret
= ehci_mx6_common_init(ehci
, index
);
360 type
= board_usb_phy_mode(index
);
363 *hccr
= (struct ehci_hccr
*)((uint32_t)&ehci
->caplength
);
364 *hcor
= (struct ehci_hcor
*)((uint32_t)*hccr
+
365 HC_LENGTH(ehci_readl(&(*hccr
)->cr_capbase
)));
368 if ((type
== init
) || (type
== USB_INIT_DEVICE
))
369 board_ehci_power(index
, (type
== USB_INIT_DEVICE
) ? 0 : 1);
372 if (type
== USB_INIT_DEVICE
)
375 setbits_le32(&ehci
->usbmode
, CM_HOST
);
376 writel(CONFIG_MXC_USB_PORTSC
, &ehci
->portsc
);
377 setbits_le32(&ehci
->portsc
, USB_EN
);
384 int ehci_hcd_stop(int index
)
389 struct ehci_mx6_priv_data
{
390 struct ehci_ctrl ctrl
;
391 struct usb_ehci
*ehci
;
392 struct udevice
*vbus_supply
;
393 enum usb_init_type init_type
;
397 static int mx6_init_after_reset(struct ehci_ctrl
*dev
)
399 struct ehci_mx6_priv_data
*priv
= dev
->priv
;
400 enum usb_init_type type
= priv
->init_type
;
401 struct usb_ehci
*ehci
= priv
->ehci
;
404 ret
= ehci_mx6_common_init(priv
->ehci
, priv
->portnr
);
408 #if CONFIG_IS_ENABLED(DM_REGULATOR)
409 if (priv
->vbus_supply
) {
410 ret
= regulator_set_enable(priv
->vbus_supply
,
411 (type
== USB_INIT_DEVICE
) ?
414 puts("Error enabling VBUS supply\n");
420 if (type
== USB_INIT_DEVICE
)
423 setbits_le32(&ehci
->usbmode
, CM_HOST
);
424 writel(CONFIG_MXC_USB_PORTSC
, &ehci
->portsc
);
425 setbits_le32(&ehci
->portsc
, USB_EN
);
432 static const struct ehci_ops mx6_ehci_ops
= {
433 .init_after_reset
= mx6_init_after_reset
436 static int ehci_usb_phy_mode(struct udevice
*dev
)
438 struct usb_platdata
*plat
= dev_get_platdata(dev
);
439 void *__iomem addr
= (void *__iomem
)devfdt_get_addr(dev
);
440 void *__iomem phy_ctrl
, *__iomem phy_status
;
441 const void *blob
= gd
->fdt_blob
;
442 int offset
= dev_of_offset(dev
), phy_off
;
446 * About fsl,usbphy, Refer to
447 * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
450 phy_off
= fdtdec_lookup_phandle(blob
,
456 addr
= (void __iomem
*)fdtdec_get_addr(blob
, phy_off
,
458 if ((fdt_addr_t
)addr
== FDT_ADDR_T_NONE
)
461 phy_ctrl
= (void __iomem
*)(addr
+ USBPHY_CTRL
);
462 val
= readl(phy_ctrl
);
464 if (val
& USBPHY_CTRL_OTG_ID
)
465 plat
->init_type
= USB_INIT_DEVICE
;
467 plat
->init_type
= USB_INIT_HOST
;
468 } else if (is_mx7()) {
469 phy_status
= (void __iomem
*)(addr
+
470 USBNC_PHY_STATUS_OFFSET
);
471 val
= readl(phy_status
);
473 if (val
& USBNC_PHYSTATUS_ID_DIG
)
474 plat
->init_type
= USB_INIT_DEVICE
;
476 plat
->init_type
= USB_INIT_HOST
;
484 static int ehci_usb_ofdata_to_platdata(struct udevice
*dev
)
486 struct usb_platdata
*plat
= dev_get_platdata(dev
);
487 enum usb_dr_mode dr_mode
;
489 dr_mode
= usb_get_dr_mode(dev_of_offset(dev
));
492 case USB_DR_MODE_HOST
:
493 plat
->init_type
= USB_INIT_HOST
;
495 case USB_DR_MODE_PERIPHERAL
:
496 plat
->init_type
= USB_INIT_DEVICE
;
498 case USB_DR_MODE_OTG
:
499 case USB_DR_MODE_UNKNOWN
:
500 return ehci_usb_phy_mode(dev
);
506 static int ehci_usb_probe(struct udevice
*dev
)
508 struct usb_platdata
*plat
= dev_get_platdata(dev
);
509 struct usb_ehci
*ehci
= (struct usb_ehci
*)devfdt_get_addr(dev
);
510 struct ehci_mx6_priv_data
*priv
= dev_get_priv(dev
);
511 enum usb_init_type type
= plat
->init_type
;
512 struct ehci_hccr
*hccr
;
513 struct ehci_hcor
*hcor
;
517 priv
->portnr
= dev
->seq
;
518 priv
->init_type
= type
;
520 #if CONFIG_IS_ENABLED(DM_REGULATOR)
521 ret
= device_get_supply_regulator(dev
, "vbus-supply",
524 debug("%s: No vbus supply\n", dev
->name
);
526 ret
= ehci_mx6_common_init(ehci
, priv
->portnr
);
530 #if CONFIG_IS_ENABLED(DM_REGULATOR)
531 if (priv
->vbus_supply
) {
532 ret
= regulator_set_enable(priv
->vbus_supply
,
533 (type
== USB_INIT_DEVICE
) ?
536 puts("Error enabling VBUS supply\n");
542 if (priv
->init_type
== USB_INIT_HOST
) {
543 setbits_le32(&ehci
->usbmode
, CM_HOST
);
544 writel(CONFIG_MXC_USB_PORTSC
, &ehci
->portsc
);
545 setbits_le32(&ehci
->portsc
, USB_EN
);
550 hccr
= (struct ehci_hccr
*)((uint32_t)&ehci
->caplength
);
551 hcor
= (struct ehci_hcor
*)((uint32_t)hccr
+
552 HC_LENGTH(ehci_readl(&(hccr
)->cr_capbase
)));
554 return ehci_register(dev
, hccr
, hcor
, &mx6_ehci_ops
, 0, priv
->init_type
);
557 static const struct udevice_id mx6_usb_ids
[] = {
558 { .compatible
= "fsl,imx27-usb" },
562 U_BOOT_DRIVER(usb_mx6
) = {
565 .of_match
= mx6_usb_ids
,
566 .ofdata_to_platdata
= ehci_usb_ofdata_to_platdata
,
567 .probe
= ehci_usb_probe
,
568 .remove
= ehci_deregister
,
569 .ops
= &ehci_usb_ops
,
570 .platdata_auto_alloc_size
= sizeof(struct usb_platdata
),
571 .priv_auto_alloc_size
= sizeof(struct ehci_mx6_priv_data
),
572 .flags
= DM_FLAG_ALLOC_PRIV_DMA
,