2 * Copyright (c) 2019, Arm Limited. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
11 compatible = "arm,A5DS";
12 interrupt-parent = <&gic>;
20 compatible = "arm,cortex-a5";
26 device_type = "memory";
27 reg = <0x80000000 0x7F000000>;
30 refclk100mhz: refclk100mhz {
31 compatible = "fixed-clock";
33 clock-frequency = <100000000>;
34 clock-output-names = "apb_pclk";
37 smbclk: refclk24mhzx2 {
38 compatible = "fixed-clock";
40 clock-frequency = <48000000>;
41 clock-output-names = "smclk";
46 compatible = "arm,pl031", "arm,primecell";
47 reg = <0x1a220000 0x1000>;
48 clocks = <&refclk100mhz>;
49 interrupts = <0 6 0xf04>;
50 clock-names = "apb_pclk";
53 gic: interrupt-controller@1c001000 {
54 compatible = "arm,cortex-a9-gic";
55 #interrupt-cells = <3>;
58 reg = <0x1c001000 0x1000>,
60 interrupts = <1 9 0xf04>;
63 serial0: uart@1a200000 {
64 compatible = "arm,pl011", "arm,primecell";
65 reg = <0x1a200000 0x1000>;
66 interrupt-parent = <&gic>;
67 interrupts = <0 8 0xf04>;
68 clocks = <&refclk100mhz>;
69 clock-names = "apb_pclk";
72 serial1: uart@1a210000 {
73 compatible = "arm,pl011", "arm,primecell";
74 reg = <0x1a210000 0x1000>;
75 interrupt-parent = <&gic>;
76 interrupts = <0 9 0xf04>;
77 clocks = <&refclk100mhz>;
78 clock-names = "apb_pclk";
81 timer0: timer@1a040000 {
82 compatible = "arm,armv7-timer-mem";
86 reg = <0x1a040000 0x1000>;
87 clock-frequency = <50000000>;
91 interrupts = <0 2 0xf04>;
92 reg = <0x1a050000 0x1000>;