2 * Copyright (c) 2019, Arm Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
10 model = "corstone700";
11 compatible = "arm,Corstone-700";
12 interrupt-parent = <&gic>;
17 bootargs = "console=ttyAMA0 root=/dev/vda2 rw loglevel=9";
18 linux,initrd-start = <0x02a00000>;
19 linux,initrd-end = <0x04000000>;
28 compatible = "arm,armv8";
30 next-level-cache = <&L2_0>;
36 device_type = "memory";
37 reg = <0x02000000 0x02000000>;
40 gic: interrupt-controller@1c000000 {
41 compatible = "arm,gic-400";
42 #interrupt-cells = <3>;
45 reg = <0x1c010000 0x1000>,
49 interrupts = <1 9 0xf08>;
56 refclk100mhz: refclk100mhz {
57 compatible = "fixed-clock";
59 clock-frequency = <100000000>;
60 clock-output-names = "apb_pclk";
63 smbclk: refclk24mhzx2 {
64 /* Reference 24MHz clock x 2 */
65 compatible = "fixed-clock";
67 clock-frequency = <48000000>;
68 clock-output-names = "smclk";
72 serial0: uart@1a510000 {
73 compatible = "arm,pl011", "arm,primecell";
74 reg = <0x1a510000 0x1000>;
75 interrupt-parent = <&gic>;
76 interrupts = <0 19 4>;
77 clocks = <&refclk100mhz>, <&smbclk>;
78 clock-names = "apb_pclk", "smclk";
81 serial1: uart@1a520000 {
82 compatible = "arm,pl011", "arm,primecell";
83 reg = <0x1a520000 0x1000>;
84 interrupt-parent = <&gic>;
85 interrupts = <0 20 4>;
86 clocks = <&refclk100mhz>, <&smbclk>;
87 clock-names = "apb_pclk", "smclk";
91 compatible = "arm,armv8-timer";
92 interrupts = <1 13 0xf08>,
98 mbox_es0mhu0: mhu@1b000000 {
99 compatible = "arm,mhuv2","arm,primecell";
100 reg = <0x1b000000 0x1000>,
102 clocks = <&refclk100mhz>;
103 clock-names = "apb_pclk";
104 interrupts = <0 12 4>;
105 interrupt-names = "mhu_rx";
107 mbox-name = "arm-es0-mhu0";
110 mbox_es0mhu1: mhu@1b020000 {
111 compatible = "arm,mhuv2","arm,primecell";
112 reg = <0x1b020000 0x1000>,
114 clocks = <&refclk100mhz>;
115 clock-names = "apb_pclk";
116 interrupts = <0 47 4>;
117 interrupt-names = "mhu_rx";
119 mbox-name = "arm-es0-mhu1";
122 mbox_semhu1: mhu@1b820000 {
123 compatible = "arm,mhuv2","arm,primecell";
124 reg = <0x1b820000 0x1000>,
126 clocks = <&refclk100mhz>;
127 clock-names = "apb_pclk";
128 interrupts = <0 45 4>;
129 interrupt-names = "mhu_rx";
131 mbox-name = "arm-se-mhu1";
135 compatible = "arm,client";
136 mboxes = <&mbox_es0mhu0 0>, <&mbox_es0mhu1 0>, <&mbox_semhu1 0>;
137 mbox-names = "es0mhu0", "es0mhu1", "semhu1";
140 extsys0: extsys@1A010310 {
141 compatible = "arm,extsys_ctrl";
142 reg = <0x1A010310 0x4>,
144 reg-names = "rstreg", "streg";