2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
9 /memreserve/ 0x80000000 0x00010000;
16 compatible = "arm,vfp-base", "arm,vexpress";
17 interrupt-parent = <&gic>;
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
31 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
33 cpu_suspend = <0x84000001>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0x84000003>;
36 sys_poweroff = <0x84000008>;
37 sys_reset = <0x84000009>;
77 entry-method = "arm,psci";
79 CPU_SLEEP_0: cpu-sleep-0 {
80 compatible = "arm,idle-state";
82 arm,psci-suspend-param = <0x0010000>;
83 entry-latency-us = <40>;
84 exit-latency-us = <100>;
85 min-residency-us = <150>;
88 CLUSTER_SLEEP_0: cluster-sleep-0 {
89 compatible = "arm,idle-state";
91 arm,psci-suspend-param = <0x1010000>;
92 entry-latency-us = <500>;
93 exit-latency-us = <1000>;
94 min-residency-us = <2500>;
100 compatible = "arm,armv8";
102 enable-method = "psci";
103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
104 next-level-cache = <&L2_0>;
109 compatible = "arm,armv8";
111 enable-method = "psci";
112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
113 next-level-cache = <&L2_0>;
118 compatible = "arm,armv8";
120 enable-method = "psci";
121 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
122 next-level-cache = <&L2_0>;
127 compatible = "arm,armv8";
129 enable-method = "psci";
130 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
131 next-level-cache = <&L2_0>;
136 compatible = "arm,armv8";
138 enable-method = "psci";
139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
140 next-level-cache = <&L2_0>;
145 compatible = "arm,armv8";
147 enable-method = "psci";
148 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
149 next-level-cache = <&L2_0>;
154 compatible = "arm,armv8";
156 enable-method = "psci";
157 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
158 next-level-cache = <&L2_0>;
163 compatible = "arm,armv8";
165 enable-method = "psci";
166 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
167 next-level-cache = <&L2_0>;
171 compatible = "cache";
176 device_type = "memory";
177 reg = <0x00000000 0x80000000 0 0x7F000000>,
178 <0x00000008 0x80000000 0 0x80000000>;
181 gic: interrupt-controller@2f000000 {
182 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
183 #interrupt-cells = <3>;
184 #address-cells = <0>;
185 interrupt-controller;
186 reg = <0x0 0x2f000000 0 0x10000>,
187 <0x0 0x2c000000 0 0x2000>,
188 <0x0 0x2c010000 0 0x2000>,
189 <0x0 0x2c02F000 0 0x2000>;
190 interrupts = <1 9 0xf04>;
194 compatible = "arm,armv8-timer";
195 interrupts = <1 13 0xff01>,
199 clock-frequency = <100000000>;
203 compatible = "arm,armv7-timer-mem";
204 reg = <0x0 0x2a810000 0x0 0x10000>;
205 clock-frequency = <100000000>;
206 #address-cells = <2>;
211 interrupts = <0 26 4>;
212 reg = <0x0 0x2a830000 0x0 0x10000>;
217 compatible = "arm,armv8-pmuv3";
218 interrupts = <0 60 4>,
225 compatible = "simple-bus";
227 #address-cells = <2>;
229 ranges = <0 0 0 0x08000000 0x04000000>,
230 <1 0 0 0x14000000 0x04000000>,
231 <2 0 0 0x18000000 0x04000000>,
232 <3 0 0 0x1c000000 0x04000000>,
233 <4 0 0 0x0c000000 0x04000000>,
234 <5 0 0 0x10000000 0x04000000>;
236 #interrupt-cells = <1>;
237 interrupt-map-mask = <0 0 63>;
238 interrupt-map = <0 0 0 &gic 0 0 4>,
248 <0 0 10 &gic 0 10 4>,
249 <0 0 11 &gic 0 11 4>,
250 <0 0 12 &gic 0 12 4>,
251 <0 0 13 &gic 0 13 4>,
252 <0 0 14 &gic 0 14 4>,
253 <0 0 15 &gic 0 15 4>,
254 <0 0 16 &gic 0 16 4>,
255 <0 0 17 &gic 0 17 4>,
256 <0 0 18 &gic 0 18 4>,
257 <0 0 19 &gic 0 19 4>,
258 <0 0 20 &gic 0 20 4>,
259 <0 0 21 &gic 0 21 4>,
260 <0 0 22 &gic 0 22 4>,
261 <0 0 23 &gic 0 23 4>,
262 <0 0 24 &gic 0 24 4>,
263 <0 0 25 &gic 0 25 4>,
264 <0 0 26 &gic 0 26 4>,
265 <0 0 27 &gic 0 27 4>,
266 <0 0 28 &gic 0 28 4>,
267 <0 0 29 &gic 0 29 4>,
268 <0 0 30 &gic 0 30 4>,
269 <0 0 31 &gic 0 31 4>,
270 <0 0 32 &gic 0 32 4>,
271 <0 0 33 &gic 0 33 4>,
272 <0 0 34 &gic 0 34 4>,
273 <0 0 35 &gic 0 35 4>,
274 <0 0 36 &gic 0 36 4>,
275 <0 0 37 &gic 0 37 4>,
276 <0 0 38 &gic 0 38 4>,
277 <0 0 39 &gic 0 39 4>,
278 <0 0 40 &gic 0 40 4>,
279 <0 0 41 &gic 0 41 4>,
280 <0 0 42 &gic 0 42 4>;
282 /include/ "rtsm_ve-motherboard-aarch32.dtsi"
287 compatible = "panel";
300 vmode = "FB_VMODE_NONINTERLACED";
301 tim2 = "TIM2_BCD", "TIM2_IPC";
302 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
303 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";