2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
7 /memreserve/ 0x80000000 0x00010000;
14 compatible = "arm,vfp-base", "arm,vexpress";
15 interrupt-parent = <&gic>;
22 serial0 = &v2m_serial0;
23 serial1 = &v2m_serial1;
24 serial2 = &v2m_serial2;
25 serial3 = &v2m_serial3;
29 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
31 cpu_suspend = <0xc4000001>;
32 cpu_off = <0x84000002>;
33 cpu_on = <0xc4000003>;
34 sys_poweroff = <0x84000008>;
35 sys_reset = <0x84000009>;
75 entry-method = "arm,psci";
77 CPU_SLEEP_0: cpu-sleep-0 {
78 compatible = "arm,idle-state";
80 arm,psci-suspend-param = <0x0010000>;
81 entry-latency-us = <40>;
82 exit-latency-us = <100>;
83 min-residency-us = <150>;
86 CLUSTER_SLEEP_0: cluster-sleep-0 {
87 compatible = "arm,idle-state";
89 arm,psci-suspend-param = <0x1010000>;
90 entry-latency-us = <500>;
91 exit-latency-us = <1000>;
92 min-residency-us = <2500>;
98 compatible = "arm,armv8";
100 enable-method = "psci";
101 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
102 next-level-cache = <&L2_0>;
107 compatible = "arm,armv8";
109 enable-method = "psci";
110 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
111 next-level-cache = <&L2_0>;
116 compatible = "arm,armv8";
118 enable-method = "psci";
119 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
120 next-level-cache = <&L2_0>;
125 compatible = "arm,armv8";
127 enable-method = "psci";
128 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
129 next-level-cache = <&L2_0>;
134 compatible = "arm,armv8";
136 enable-method = "psci";
137 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
138 next-level-cache = <&L2_0>;
143 compatible = "arm,armv8";
145 enable-method = "psci";
146 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
147 next-level-cache = <&L2_0>;
152 compatible = "arm,armv8";
154 enable-method = "psci";
155 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
156 next-level-cache = <&L2_0>;
161 compatible = "arm,armv8";
163 enable-method = "psci";
164 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
165 next-level-cache = <&L2_0>;
169 compatible = "cache";
174 device_type = "memory";
175 reg = <0x00000000 0x80000000 0 0x7F000000>,
176 <0x00000008 0x80000000 0 0x80000000>;
179 gic: interrupt-controller@2f000000 {
180 compatible = "arm,gic-v3";
181 #interrupt-cells = <3>;
182 #address-cells = <2>;
185 interrupt-controller;
186 reg = <0x0 0x2f000000 0 0x10000>, // GICD
187 <0x0 0x2f100000 0 0x200000>, // GICR
188 <0x0 0x2c000000 0 0x2000>, // GICC
189 <0x0 0x2c010000 0 0x2000>, // GICH
190 <0x0 0x2c02f000 0 0x2000>; // GICV
191 interrupts = <1 9 4>;
194 compatible = "arm,gic-v3-its";
196 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
201 compatible = "arm,armv8-timer";
202 interrupts = <1 13 0xff01>,
206 clock-frequency = <100000000>;
210 compatible = "arm,armv7-timer-mem";
211 reg = <0x0 0x2a810000 0x0 0x10000>;
212 clock-frequency = <100000000>;
213 #address-cells = <2>;
218 interrupts = <0 26 4>;
219 reg = <0x0 0x2a830000 0x0 0x10000>;
224 compatible = "arm,armv8-pmuv3";
225 interrupts = <0 60 4>,
232 compatible = "simple-bus";
234 #address-cells = <2>;
236 ranges = <0 0 0 0x08000000 0x04000000>,
237 <1 0 0 0x14000000 0x04000000>,
238 <2 0 0 0x18000000 0x04000000>,
239 <3 0 0 0x1c000000 0x04000000>,
240 <4 0 0 0x0c000000 0x04000000>,
241 <5 0 0 0x10000000 0x04000000>;
243 /include/ "rtsm_ve-motherboard.dtsi"
248 compatible = "panel";
261 vmode = "FB_VMODE_NONINTERLACED";
262 tim2 = "TIM2_BCD", "TIM2_IPC";
263 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
264 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";