2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
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8 * list of conditions and the following disclaimer.
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33 /memreserve/ 0x80000000 0x00010000;
40 compatible = "arm,vfp-base", "arm,vexpress";
41 interrupt-parent = <&gic>;
48 serial0 = &v2m_serial0;
49 serial1 = &v2m_serial1;
50 serial2 = &v2m_serial2;
51 serial3 = &v2m_serial3;
55 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
57 cpu_suspend = <0xc4000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0xc4000003>;
99 entry-method = "arm,psci";
101 CPU_SLEEP_0: cpu-sleep-0 {
102 compatible = "arm,idle-state";
103 entry-method-param = <0x0010000>;
104 entry-latency-us = <40>;
105 exit-latency-us = <100>;
106 min-residency-us = <150>;
109 CLUSTER_SLEEP_0: cluster-sleep-0 {
110 compatible = "arm,idle-state";
111 entry-method-param = <0x1010000>;
112 entry-latency-us = <500>;
113 exit-latency-us = <1000>;
114 min-residency-us = <2500>;
120 compatible = "arm,armv8";
122 enable-method = "psci";
123 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
128 compatible = "arm,armv8";
130 enable-method = "psci";
131 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
136 compatible = "arm,armv8";
138 enable-method = "psci";
139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
144 compatible = "arm,armv8";
146 enable-method = "psci";
147 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
152 compatible = "arm,armv8";
154 enable-method = "psci";
155 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
160 compatible = "arm,armv8";
162 enable-method = "psci";
163 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
168 compatible = "arm,armv8";
170 enable-method = "psci";
171 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
176 compatible = "arm,armv8";
178 enable-method = "psci";
179 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
184 device_type = "memory";
185 reg = <0x00000000 0x80000000 0 0x7F000000>,
186 <0x00000008 0x80000000 0 0x80000000>;
189 gic: interrupt-controller@2f000000 {
190 compatible = "arm,gic-v3";
191 #interrupt-cells = <3>;
192 #address-cells = <2>;
195 interrupt-controller;
196 reg = <0x0 0x2f000000 0 0x10000>, // GICD
197 <0x0 0x2f100000 0 0x200000>, // GICR
198 <0x0 0x2c000000 0 0x2000>, // GICC
199 <0x0 0x2c010000 0 0x2000>, // GICH
200 <0x0 0x2c02f000 0 0x2000>; // GICV
201 interrupts = <1 9 4>;
204 compatible = "arm,gic-v3-its";
206 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
211 compatible = "arm,armv8-timer";
212 interrupts = <1 13 0xff01>,
216 clock-frequency = <100000000>;
220 compatible = "arm,armv7-timer-mem";
221 reg = <0x0 0x2a810000 0x0 0x10000>;
222 clock-frequency = <100000000>;
223 #address-cells = <2>;
228 interrupts = <0 26 4>;
229 reg = <0x0 0x2a830000 0x0 0x10000>;
234 compatible = "arm,armv8-pmuv3";
235 interrupts = <0 60 4>,
242 compatible = "simple-bus";
244 #address-cells = <2>;
246 ranges = <0 0 0 0x08000000 0x04000000>,
247 <1 0 0 0x14000000 0x04000000>,
248 <2 0 0 0x18000000 0x04000000>,
249 <3 0 0 0x1c000000 0x04000000>,
250 <4 0 0 0x0c000000 0x04000000>,
251 <5 0 0 0x10000000 0x04000000>;
253 #interrupt-cells = <1>;
254 interrupt-map-mask = <0 0 63>;
255 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
256 <0 0 1 &gic 0 0 0 1 4>,
257 <0 0 2 &gic 0 0 0 2 4>,
258 <0 0 3 &gic 0 0 0 3 4>,
259 <0 0 4 &gic 0 0 0 4 4>,
260 <0 0 5 &gic 0 0 0 5 4>,
261 <0 0 6 &gic 0 0 0 6 4>,
262 <0 0 7 &gic 0 0 0 7 4>,
263 <0 0 8 &gic 0 0 0 8 4>,
264 <0 0 9 &gic 0 0 0 9 4>,
265 <0 0 10 &gic 0 0 0 10 4>,
266 <0 0 11 &gic 0 0 0 11 4>,
267 <0 0 12 &gic 0 0 0 12 4>,
268 <0 0 13 &gic 0 0 0 13 4>,
269 <0 0 14 &gic 0 0 0 14 4>,
270 <0 0 15 &gic 0 0 0 15 4>,
271 <0 0 16 &gic 0 0 0 16 4>,
272 <0 0 17 &gic 0 0 0 17 4>,
273 <0 0 18 &gic 0 0 0 18 4>,
274 <0 0 19 &gic 0 0 0 19 4>,
275 <0 0 20 &gic 0 0 0 20 4>,
276 <0 0 21 &gic 0 0 0 21 4>,
277 <0 0 22 &gic 0 0 0 22 4>,
278 <0 0 23 &gic 0 0 0 23 4>,
279 <0 0 24 &gic 0 0 0 24 4>,
280 <0 0 25 &gic 0 0 0 25 4>,
281 <0 0 26 &gic 0 0 0 26 4>,
282 <0 0 27 &gic 0 0 0 27 4>,
283 <0 0 28 &gic 0 0 0 28 4>,
284 <0 0 29 &gic 0 0 0 29 4>,
285 <0 0 30 &gic 0 0 0 30 4>,
286 <0 0 31 &gic 0 0 0 31 4>,
287 <0 0 32 &gic 0 0 0 32 4>,
288 <0 0 33 &gic 0 0 0 33 4>,
289 <0 0 34 &gic 0 0 0 34 4>,
290 <0 0 35 &gic 0 0 0 35 4>,
291 <0 0 36 &gic 0 0 0 36 4>,
292 <0 0 37 &gic 0 0 0 37 4>,
293 <0 0 38 &gic 0 0 0 38 4>,
294 <0 0 39 &gic 0 0 0 39 4>,
295 <0 0 40 &gic 0 0 0 40 4>,
296 <0 0 41 &gic 0 0 0 41 4>,
297 <0 0 42 &gic 0 0 0 42 4>;
299 /include/ "rtsm_ve-motherboard-no_psci.dtsi"
304 compatible = "panel";
317 vmode = "FB_VMODE_NONINTERLACED";
318 tim2 = "TIM2_BCD", "TIM2_IPC";
319 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
320 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";