2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
33 /memreserve/ 0x80000000 0x00010000;
39 model = "FVP Foundation";
40 compatible = "arm,fvp-base", "arm,vexpress";
41 interrupt-parent = <&gic>;
48 serial0 = &v2m_serial0;
49 serial1 = &v2m_serial1;
50 serial2 = &v2m_serial2;
51 serial3 = &v2m_serial3;
55 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
57 cpu_suspend = <0xc4000001>;
58 cpu_off = <0x84000002>;
59 cpu_on = <0xc4000003>;
60 sys_poweroff = <0x84000008>;
61 sys_reset = <0x84000009>;
86 entry-method = "arm,psci";
88 CPU_SLEEP_0: cpu-sleep-0 {
89 compatible = "arm,idle-state";
91 arm,psci-suspend-param = <0x0010000>;
92 entry-latency-us = <40>;
93 exit-latency-us = <100>;
94 min-residency-us = <150>;
97 CLUSTER_SLEEP_0: cluster-sleep-0 {
98 compatible = "arm,idle-state";
100 arm,psci-suspend-param = <0x1010000>;
101 entry-latency-us = <500>;
102 exit-latency-us = <1000>;
103 min-residency-us = <2500>;
109 compatible = "arm,armv8";
111 enable-method = "psci";
112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
113 next-level-cache = <&L2_0>;
118 compatible = "arm,armv8";
120 enable-method = "psci";
121 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
122 next-level-cache = <&L2_0>;
127 compatible = "arm,armv8";
129 enable-method = "psci";
130 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
131 next-level-cache = <&L2_0>;
136 compatible = "arm,armv8";
138 enable-method = "psci";
139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
140 next-level-cache = <&L2_0>;
144 compatible = "cache";
149 device_type = "memory";
150 reg = <0x00000000 0x80000000 0 0x7F000000>,
151 <0x00000008 0x80000000 0 0x80000000>;
154 gic: interrupt-controller@2f000000 {
155 compatible = "arm,gic-v3";
156 #interrupt-cells = <3>;
157 #address-cells = <2>;
160 interrupt-controller;
161 reg = <0x0 0x2f000000 0 0x10000>, // GICD
162 <0x0 0x2f100000 0 0x200000>, // GICR
163 <0x0 0x2c000000 0 0x2000>, // GICC
164 <0x0 0x2c010000 0 0x2000>, // GICH
165 <0x0 0x2c02f000 0 0x2000>; // GICV
166 interrupts = <1 9 4>;
169 compatible = "arm,gic-v3-its";
171 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
176 compatible = "arm,armv8-timer";
177 interrupts = <1 13 0xff01>,
181 clock-frequency = <100000000>;
185 compatible = "arm,armv7-timer-mem";
186 reg = <0x0 0x2a810000 0x0 0x10000>;
187 clock-frequency = <100000000>;
188 #address-cells = <2>;
193 interrupts = <0 26 4>;
194 reg = <0x0 0x2a830000 0x0 0x10000>;
199 compatible = "arm,armv8-pmuv3";
200 interrupts = <0 60 4>,
207 compatible = "simple-bus";
209 #address-cells = <2>;
211 ranges = <0 0 0 0x08000000 0x04000000>,
212 <1 0 0 0x14000000 0x04000000>,
213 <2 0 0 0x18000000 0x04000000>,
214 <3 0 0 0x1c000000 0x04000000>,
215 <4 0 0 0x0c000000 0x04000000>,
216 <5 0 0 0x10000000 0x04000000>;
218 #interrupt-cells = <1>;
219 interrupt-map-mask = <0 0 63>;
220 interrupt-map = <0 0 0 &gic 0 0 0 0 4>,
221 <0 0 1 &gic 0 0 0 1 4>,
222 <0 0 2 &gic 0 0 0 2 4>,
223 <0 0 3 &gic 0 0 0 3 4>,
224 <0 0 4 &gic 0 0 0 4 4>,
225 <0 0 5 &gic 0 0 0 5 4>,
226 <0 0 6 &gic 0 0 0 6 4>,
227 <0 0 7 &gic 0 0 0 7 4>,
228 <0 0 8 &gic 0 0 0 8 4>,
229 <0 0 9 &gic 0 0 0 9 4>,
230 <0 0 10 &gic 0 0 0 10 4>,
231 <0 0 11 &gic 0 0 0 11 4>,
232 <0 0 12 &gic 0 0 0 12 4>,
233 <0 0 13 &gic 0 0 0 13 4>,
234 <0 0 14 &gic 0 0 0 14 4>,
235 <0 0 15 &gic 0 0 0 15 4>,
236 <0 0 16 &gic 0 0 0 16 4>,
237 <0 0 17 &gic 0 0 0 17 4>,
238 <0 0 18 &gic 0 0 0 18 4>,
239 <0 0 19 &gic 0 0 0 19 4>,
240 <0 0 20 &gic 0 0 0 20 4>,
241 <0 0 21 &gic 0 0 0 21 4>,
242 <0 0 22 &gic 0 0 0 22 4>,
243 <0 0 23 &gic 0 0 0 23 4>,
244 <0 0 24 &gic 0 0 0 24 4>,
245 <0 0 25 &gic 0 0 0 25 4>,
246 <0 0 26 &gic 0 0 0 26 4>,
247 <0 0 27 &gic 0 0 0 27 4>,
248 <0 0 28 &gic 0 0 0 28 4>,
249 <0 0 29 &gic 0 0 0 29 4>,
250 <0 0 30 &gic 0 0 0 30 4>,
251 <0 0 31 &gic 0 0 0 31 4>,
252 <0 0 32 &gic 0 0 0 32 4>,
253 <0 0 33 &gic 0 0 0 33 4>,
254 <0 0 34 &gic 0 0 0 34 4>,
255 <0 0 35 &gic 0 0 0 35 4>,
256 <0 0 36 &gic 0 0 0 36 4>,
257 <0 0 37 &gic 0 0 0 37 4>,
258 <0 0 38 &gic 0 0 0 38 4>,
259 <0 0 39 &gic 0 0 0 39 4>,
260 <0 0 40 &gic 0 0 0 40 4>,
261 <0 0 41 &gic 0 0 0 41 4>,
262 <0 0 42 &gic 0 0 0 42 4>;
264 /include/ "fvp-foundation-motherboard.dtsi"