2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
8 arm,v2m-memory-map = "rs1";
9 compatible = "arm,vexpress,v2m-p1", "simple-bus";
10 #address-cells = <2>; /* SMB chipselect number and offset */
12 #interrupt-cells = <1>;
16 compatible = "arm,vexpress-flash", "cfi-flash";
17 reg = <0 0x00000000 0x04000000>,
18 <4 0x00000000 0x04000000>;
23 compatible = "arm,vexpress-vram";
24 reg = <2 0x00000000 0x00800000>;
28 compatible = "smsc,lan91c111";
29 reg = <2 0x02000000 0x10000>;
33 v2m_clk24mhz: clk24mhz {
34 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 clock-output-names = "v2m:clk24mhz";
40 v2m_refclk1mhz: refclk1mhz {
41 compatible = "fixed-clock";
43 clock-frequency = <1000000>;
44 clock-output-names = "v2m:refclk1mhz";
47 v2m_refclk32khz: refclk32khz {
48 compatible = "fixed-clock";
50 clock-frequency = <32768>;
51 clock-output-names = "v2m:refclk32khz";
55 compatible = "arm,amba-bus", "simple-bus";
58 ranges = <0 3 0 0x200000>;
60 v2m_sysreg: sysreg@10000 {
61 compatible = "arm,vexpress-sysreg";
62 reg = <0x010000 0x1000>;
67 v2m_sysctl: sysctl@20000 {
68 compatible = "arm,sp810", "arm,primecell";
69 reg = <0x020000 0x1000>;
70 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
71 clock-names = "refclk", "timclk", "apb_pclk";
73 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
77 compatible = "arm,pl041", "arm,primecell";
78 reg = <0x040000 0x1000>;
80 clocks = <&v2m_clk24mhz>;
81 clock-names = "apb_pclk";
85 compatible = "arm,pl180", "arm,primecell";
86 reg = <0x050000 0x1000>;
88 cd-gpios = <&v2m_sysreg 0 0>;
89 wp-gpios = <&v2m_sysreg 1 0>;
90 max-frequency = <12000000>;
91 vmmc-supply = <&v2m_fixed_3v3>;
92 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
93 clock-names = "mclk", "apb_pclk";
97 compatible = "arm,pl050", "arm,primecell";
98 reg = <0x060000 0x1000>;
100 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
101 clock-names = "KMIREFCLK", "apb_pclk";
105 compatible = "arm,pl050", "arm,primecell";
106 reg = <0x070000 0x1000>;
108 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
109 clock-names = "KMIREFCLK", "apb_pclk";
112 v2m_serial0: uart@90000 {
113 compatible = "arm,pl011", "arm,primecell";
114 reg = <0x090000 0x1000>;
116 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
117 clock-names = "uartclk", "apb_pclk";
120 v2m_serial1: uart@a0000 {
121 compatible = "arm,pl011", "arm,primecell";
122 reg = <0x0a0000 0x1000>;
124 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
125 clock-names = "uartclk", "apb_pclk";
128 v2m_serial2: uart@b0000 {
129 compatible = "arm,pl011", "arm,primecell";
130 reg = <0x0b0000 0x1000>;
132 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
133 clock-names = "uartclk", "apb_pclk";
136 v2m_serial3: uart@c0000 {
137 compatible = "arm,pl011", "arm,primecell";
138 reg = <0x0c0000 0x1000>;
140 clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
141 clock-names = "uartclk", "apb_pclk";
145 compatible = "arm,sp805", "arm,primecell";
146 reg = <0x0f0000 0x1000>;
148 clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
149 clock-names = "wdogclk", "apb_pclk";
152 v2m_timer01: timer@110000 {
153 compatible = "arm,sp804", "arm,primecell";
154 reg = <0x110000 0x1000>;
156 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
157 clock-names = "timclken1", "timclken2", "apb_pclk";
160 v2m_timer23: timer@120000 {
161 compatible = "arm,sp804", "arm,primecell";
162 reg = <0x120000 0x1000>;
164 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
165 clock-names = "timclken1", "timclken2", "apb_pclk";
169 compatible = "arm,pl031", "arm,primecell";
170 reg = <0x170000 0x1000>;
172 clocks = <&v2m_clk24mhz>;
173 clock-names = "apb_pclk";
177 compatible = "arm,pl111", "arm,primecell";
178 reg = <0x1f0000 0x1000>;
180 clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
181 clock-names = "clcdclk", "apb_pclk";
184 framebuffer = <0x18000000 0x00180000>;
187 virtio_block@130000 {
188 compatible = "virtio,mmio";
189 reg = <0x130000 0x1000>;
194 v2m_fixed_3v3: fixedregulator@0 {
195 compatible = "regulator-fixed";
196 regulator-name = "3V3";
197 regulator-min-microvolt = <3300000>;
198 regulator-max-microvolt = <3300000>;
203 compatible = "arm,vexpress,config-bus", "simple-bus";
204 arm,vexpress,config-bridge = <&v2m_sysreg>;
208 compatible = "arm,vexpress-osc";
209 arm,vexpress-sysreg,func = <1 1>;
210 freq-range = <23750000 63500000>;
212 clock-output-names = "v2m:oscclk1";
216 * Not supported in FVP models
219 * compatible = "arm,vexpress-reset";
220 * arm,vexpress-sysreg,func = <5 0>;
225 compatible = "arm,vexpress-muxfpga";
226 arm,vexpress-sysreg,func = <7 0>;
230 * Not used - Superseded by PSCI sys_poweroff
233 * compatible = "arm,vexpress-shutdown";
234 * arm,vexpress-sysreg,func = <8 0>;
239 * Not used - Superseded by PSCI sys_reset
242 * compatible = "arm,vexpress-reboot";
243 * arm,vexpress-sysreg,func = <9 0>;
248 compatible = "arm,vexpress-dvimode";
249 arm,vexpress-sysreg,func = <11 0>;