1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
13 compatible = "st,stm32mp157-pinctrl";
14 ranges = <0 0x50002000 0xa400>;
17 gpioa: gpio@50002000 {
21 #interrupt-cells = <2>;
23 clocks = <&rcc GPIOA>;
24 st,bank-name = "GPIOA";
28 gpiob: gpio@50003000 {
32 #interrupt-cells = <2>;
34 clocks = <&rcc GPIOB>;
35 st,bank-name = "GPIOB";
39 gpioc: gpio@50004000 {
43 #interrupt-cells = <2>;
45 clocks = <&rcc GPIOC>;
46 st,bank-name = "GPIOC";
50 gpiod: gpio@50005000 {
54 #interrupt-cells = <2>;
56 clocks = <&rcc GPIOD>;
57 st,bank-name = "GPIOD";
61 gpioe: gpio@50006000 {
65 #interrupt-cells = <2>;
67 clocks = <&rcc GPIOE>;
68 st,bank-name = "GPIOE";
72 gpiof: gpio@50007000 {
76 #interrupt-cells = <2>;
78 clocks = <&rcc GPIOF>;
79 st,bank-name = "GPIOF";
83 gpiog: gpio@50008000 {
87 #interrupt-cells = <2>;
89 clocks = <&rcc GPIOG>;
90 st,bank-name = "GPIOG";
94 gpioh: gpio@50009000 {
98 #interrupt-cells = <2>;
100 clocks = <&rcc GPIOH>;
101 st,bank-name = "GPIOH";
105 gpioi: gpio@5000a000 {
108 interrupt-controller;
109 #interrupt-cells = <2>;
110 reg = <0x8000 0x400>;
111 clocks = <&rcc GPIOI>;
112 st,bank-name = "GPIOI";
116 gpioj: gpio@5000b000 {
119 interrupt-controller;
120 #interrupt-cells = <2>;
121 reg = <0x9000 0x400>;
122 clocks = <&rcc GPIOJ>;
123 st,bank-name = "GPIOJ";
127 gpiok: gpio@5000c000 {
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 reg = <0xa000 0x400>;
133 clocks = <&rcc GPIOK>;
134 st,bank-name = "GPIOK";
138 qspi_bk1_pins_a: qspi-bk1-0 {
140 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
141 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
142 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
143 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
149 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
156 qspi_bk2_pins_a: qspi-bk2-0 {
158 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
159 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
160 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
161 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
167 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
174 qspi_clk_pins_a: qspi-clk-0 {
176 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
183 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
185 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
186 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
187 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
188 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
189 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
195 pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
202 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
204 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
205 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
206 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
212 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
217 sdmmc2_b4_pins_a: sdmmc2-b4-0 {
219 pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */
220 <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */
221 <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */
222 <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */
223 <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */
229 pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */
236 sdmmc2_d47_pins_a: sdmmc2-d47-0 {
238 pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
239 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
240 <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
241 <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */
248 uart4_pins_a: uart4-0 {
250 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
256 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
261 uart4_pins_b: uart4-1 {
263 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
269 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
274 uart7_pins_a: uart7-0 {
276 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* USART7_TX */
282 pinmux = <STM32_PINMUX('E', 7, AF7)>; /* USART7_RX */
287 usart3_pins_a: usart3-0 {
289 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
290 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
296 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
297 <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */
302 usart3_pins_b: usart3-1 {
304 pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */
305 <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */
311 pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */
312 <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */
318 pinctrl_z: pin-controller-z@54004000 {
319 #address-cells = <1>;
321 compatible = "st,stm32mp157-z-pinctrl";
322 ranges = <0 0x54004000 0x400>;
325 gpioz: gpio@54004000 {
328 interrupt-controller;
329 #interrupt-cells = <2>;
331 clocks = <&rcc GPIOZ>;
332 st,bank-name = "GPIOZ";
333 st,bank-ioport = <11>;
337 i2c4_pins_a: i2c4-0 {
339 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
340 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */