8260c549196bde2d7f6d66bfc43e60b21b90c2fe
2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
10 #include <utils_def.h>
12 /*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
15 #define MIDR_IMPL_MASK U(0xff)
16 #define MIDR_IMPL_SHIFT U(24)
17 #define MIDR_VAR_SHIFT U(20)
18 #define MIDR_VAR_BITS U(4)
19 #define MIDR_REV_SHIFT U(0)
20 #define MIDR_REV_BITS U(4)
21 #define MIDR_PN_MASK U(0xfff)
22 #define MIDR_PN_SHIFT U(4)
24 /*******************************************************************************
26 ******************************************************************************/
27 #define MPIDR_MT_MASK (U(1) << 24)
28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
30 #define MPIDR_AFFINITY_BITS U(8)
31 #define MPIDR_AFFLVL_MASK U(0xff)
32 #define MPIDR_AFFLVL_SHIFT U(3)
33 #define MPIDR_AFF0_SHIFT U(0)
34 #define MPIDR_AFF1_SHIFT U(8)
35 #define MPIDR_AFF2_SHIFT U(16)
36 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
37 #define MPIDR_AFFINITY_MASK U(0x00ffffff)
38 #define MPIDR_AFFLVL0 U(0)
39 #define MPIDR_AFFLVL1 U(1)
40 #define MPIDR_AFFLVL2 U(2)
41 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
43 #define MPIDR_AFFLVL0_VAL(mpidr) \
44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
45 #define MPIDR_AFFLVL1_VAL(mpidr) \
46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
47 #define MPIDR_AFFLVL2_VAL(mpidr) \
48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
49 #define MPIDR_AFFLVL3_VAL(mpidr) U(0)
51 #define MPIDR_AFF_ID(mpid, n) \
52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
54 #define MPID_MASK (MPIDR_MT_MASK |\
55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
60 * An invalid MPID. This value can be used by functions that return an MPID to
63 #define INVALID_MPID U(0xFFFFFFFF)
66 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
67 * add one while using this macro to define array sizes.
69 #define MPIDR_MAX_AFFLVL U(2)
71 /* Data Cache set/way op type defines */
72 #define DC_OP_ISW U(0x0)
73 #define DC_OP_CISW U(0x1)
74 #define DC_OP_CSW U(0x2)
76 /*******************************************************************************
77 * Generic timer memory mapped registers & offsets
78 ******************************************************************************/
79 #define CNTCR_OFF U(0x000)
80 #define CNTFID_OFF U(0x020)
82 #define CNTCR_EN (U(1) << 0)
83 #define CNTCR_HDBG (U(1) << 1)
84 #define CNTCR_FCREQ(x) ((x) << 8)
86 /*******************************************************************************
87 * System register bit definitions
88 ******************************************************************************/
89 /* CLIDR definitions */
90 #define LOUIS_SHIFT U(21)
91 #define LOC_SHIFT U(24)
92 #define CLIDR_FIELD_WIDTH U(3)
94 /* CSSELR definitions */
95 #define LEVEL_SHIFT U(1)
97 /* ID_PFR0 AMU definitions */
98 #define ID_PFR0_AMU_SHIFT U(20)
99 #define ID_PFR0_AMU_LENGTH U(4)
100 #define ID_PFR0_AMU_MASK U(0xf)
102 /* ID_PFR0 DIT definitions */
103 #define ID_PFR0_DIT_SHIFT U(24)
104 #define ID_PFR0_DIT_LENGTH U(4)
105 #define ID_PFR0_DIT_MASK U(0xf)
106 #define ID_PFR0_DIT_SUPPORTED (U(1) << ID_PFR0_DIT_SHIFT)
108 /* ID_PFR1 definitions */
109 #define ID_PFR1_VIRTEXT_SHIFT U(12)
110 #define ID_PFR1_VIRTEXT_MASK U(0xf)
111 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
112 & ID_PFR1_VIRTEXT_MASK)
113 #define ID_PFR1_GIC_SHIFT U(28)
114 #define ID_PFR1_GIC_MASK U(0xf)
116 /* SCTLR definitions */
117 #define SCTLR_RES1_DEF ((U(1) << 23) | (U(1) << 22) | (U(1) << 4) | \
119 #if ARM_ARCH_MAJOR == 7
120 #define SCTLR_RES1 SCTLR_RES1_DEF
122 #define SCTLR_RES1 (SCTLR_RES1_DEF | (U(1) << 11))
124 #define SCTLR_M_BIT (U(1) << 0)
125 #define SCTLR_A_BIT (U(1) << 1)
126 #define SCTLR_C_BIT (U(1) << 2)
127 #define SCTLR_CP15BEN_BIT (U(1) << 5)
128 #define SCTLR_ITD_BIT (U(1) << 7)
129 #define SCTLR_Z_BIT (U(1) << 11)
130 #define SCTLR_I_BIT (U(1) << 12)
131 #define SCTLR_V_BIT (U(1) << 13)
132 #define SCTLR_RR_BIT (U(1) << 14)
133 #define SCTLR_NTWI_BIT (U(1) << 16)
134 #define SCTLR_NTWE_BIT (U(1) << 18)
135 #define SCTLR_WXN_BIT (U(1) << 19)
136 #define SCTLR_UWXN_BIT (U(1) << 20)
137 #define SCTLR_EE_BIT (U(1) << 25)
138 #define SCTLR_TRE_BIT (U(1) << 28)
139 #define SCTLR_AFE_BIT (U(1) << 29)
140 #define SCTLR_TE_BIT (U(1) << 30)
141 #define SCTLR_DSSBS_BIT (U(1) << 31)
142 #define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
143 SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
145 /* SDCR definitions */
146 #define SDCR_SPD(x) ((x) << 14)
147 #define SDCR_SPD_LEGACY U(0x0)
148 #define SDCR_SPD_DISABLE U(0x2)
149 #define SDCR_SPD_ENABLE U(0x3)
150 #define SDCR_RESET_VAL U(0x0)
152 /* HSCTLR definitions */
153 #define HSCTLR_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
154 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
155 (U(1) << 11) | (U(1) << 4) | (U(1) << 3))
157 #define HSCTLR_M_BIT (U(1) << 0)
158 #define HSCTLR_A_BIT (U(1) << 1)
159 #define HSCTLR_C_BIT (U(1) << 2)
160 #define HSCTLR_CP15BEN_BIT (U(1) << 5)
161 #define HSCTLR_ITD_BIT (U(1) << 7)
162 #define HSCTLR_SED_BIT (U(1) << 8)
163 #define HSCTLR_I_BIT (U(1) << 12)
164 #define HSCTLR_WXN_BIT (U(1) << 19)
165 #define HSCTLR_EE_BIT (U(1) << 25)
166 #define HSCTLR_TE_BIT (U(1) << 30)
168 /* CPACR definitions */
169 #define CPACR_FPEN(x) ((x) << 20)
170 #define CPACR_FP_TRAP_PL0 U(0x1)
171 #define CPACR_FP_TRAP_ALL U(0x2)
172 #define CPACR_FP_TRAP_NONE U(0x3)
174 /* SCR definitions */
175 #define SCR_TWE_BIT (U(1) << 13)
176 #define SCR_TWI_BIT (U(1) << 12)
177 #define SCR_SIF_BIT (U(1) << 9)
178 #define SCR_HCE_BIT (U(1) << 8)
179 #define SCR_SCD_BIT (U(1) << 7)
180 #define SCR_NET_BIT (U(1) << 6)
181 #define SCR_AW_BIT (U(1) << 5)
182 #define SCR_FW_BIT (U(1) << 4)
183 #define SCR_EA_BIT (U(1) << 3)
184 #define SCR_FIQ_BIT (U(1) << 2)
185 #define SCR_IRQ_BIT (U(1) << 1)
186 #define SCR_NS_BIT (U(1) << 0)
187 #define SCR_VALID_BIT_MASK U(0x33ff)
188 #define SCR_RESET_VAL U(0x0)
190 #define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
192 /* HCR definitions */
193 #define HCR_TGE_BIT (U(1) << 27)
194 #define HCR_AMO_BIT (U(1) << 5)
195 #define HCR_IMO_BIT (U(1) << 4)
196 #define HCR_FMO_BIT (U(1) << 3)
197 #define HCR_RESET_VAL U(0x0)
199 /* CNTHCTL definitions */
200 #define CNTHCTL_RESET_VAL U(0x0)
201 #define PL1PCEN_BIT (U(1) << 1)
202 #define PL1PCTEN_BIT (U(1) << 0)
204 /* CNTKCTL definitions */
205 #define PL0PTEN_BIT (U(1) << 9)
206 #define PL0VTEN_BIT (U(1) << 8)
207 #define PL0PCTEN_BIT (U(1) << 0)
208 #define PL0VCTEN_BIT (U(1) << 1)
209 #define EVNTEN_BIT (U(1) << 2)
210 #define EVNTDIR_BIT (U(1) << 3)
211 #define EVNTI_SHIFT U(4)
212 #define EVNTI_MASK U(0xf)
214 /* HCPTR definitions */
215 #define HCPTR_RES1 ((U(1) << 13) | (U(1) << 12) | U(0x3ff))
216 #define TCPAC_BIT (U(1) << 31)
217 #define TAM_BIT (U(1) << 30)
218 #define TTA_BIT (U(1) << 20)
219 #define TCP11_BIT (U(1) << 11)
220 #define TCP10_BIT (U(1) << 10)
221 #define HCPTR_RESET_VAL HCPTR_RES1
223 /* VTTBR defintions */
224 #define VTTBR_RESET_VAL ULL(0x0)
225 #define VTTBR_VMID_MASK ULL(0xff)
226 #define VTTBR_VMID_SHIFT U(48)
227 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)
228 #define VTTBR_BADDR_SHIFT U(0)
230 /* HDCR definitions */
231 #define HDCR_RESET_VAL U(0x0)
233 /* HSTR definitions */
234 #define HSTR_RESET_VAL U(0x0)
236 /* CNTHP_CTL definitions */
237 #define CNTHP_CTL_RESET_VAL U(0x0)
239 /* NSACR definitions */
240 #define NSASEDIS_BIT (U(1) << 15)
241 #define NSTRCDIS_BIT (U(1) << 20)
242 #define NSACR_CP11_BIT (U(1) << 11)
243 #define NSACR_CP10_BIT (U(1) << 10)
244 #define NSACR_IMP_DEF_MASK (U(0x7) << 16)
245 #define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
246 #define NSACR_RESET_VAL U(0x0)
248 /* CPACR definitions */
249 #define ASEDIS_BIT (U(1) << 31)
250 #define TRCDIS_BIT (U(1) << 28)
251 #define CPACR_CP11_SHIFT U(22)
252 #define CPACR_CP10_SHIFT U(20)
253 #define CPACR_ENABLE_FP_ACCESS ((U(0x3) << CPACR_CP11_SHIFT) |\
254 (U(0x3) << CPACR_CP10_SHIFT))
255 #define CPACR_RESET_VAL U(0x0)
257 /* FPEXC definitions */
258 #define FPEXC_RES1 ((U(1) << 10) | (U(1) << 9) | (U(1) << 8))
259 #define FPEXC_EN_BIT (U(1) << 30)
260 #define FPEXC_RESET_VAL FPEXC_RES1
262 /* SPSR/CPSR definitions */
263 #define SPSR_FIQ_BIT (U(1) << 0)
264 #define SPSR_IRQ_BIT (U(1) << 1)
265 #define SPSR_ABT_BIT (U(1) << 2)
266 #define SPSR_AIF_SHIFT U(6)
267 #define SPSR_AIF_MASK U(0x7)
269 #define SPSR_E_SHIFT U(9)
270 #define SPSR_E_MASK U(0x1)
271 #define SPSR_E_LITTLE U(0)
272 #define SPSR_E_BIG U(1)
274 #define SPSR_T_SHIFT U(5)
275 #define SPSR_T_MASK U(0x1)
276 #define SPSR_T_ARM U(0)
277 #define SPSR_T_THUMB U(1)
279 #define SPSR_MODE_SHIFT U(0)
280 #define SPSR_MODE_MASK U(0x7)
282 #define DISABLE_ALL_EXCEPTIONS \
283 (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
285 #define CPSR_DIT_BIT (U(1) << 21)
289 #define TTBCR_EAE_BIT (U(1) << 31)
291 #define TTBCR_SH1_NON_SHAREABLE (U(0x0) << 28)
292 #define TTBCR_SH1_OUTER_SHAREABLE (U(0x2) << 28)
293 #define TTBCR_SH1_INNER_SHAREABLE (U(0x3) << 28)
295 #define TTBCR_RGN1_OUTER_NC (U(0x0) << 26)
296 #define TTBCR_RGN1_OUTER_WBA (U(0x1) << 26)
297 #define TTBCR_RGN1_OUTER_WT (U(0x2) << 26)
298 #define TTBCR_RGN1_OUTER_WBNA (U(0x3) << 26)
300 #define TTBCR_RGN1_INNER_NC (U(0x0) << 24)
301 #define TTBCR_RGN1_INNER_WBA (U(0x1) << 24)
302 #define TTBCR_RGN1_INNER_WT (U(0x2) << 24)
303 #define TTBCR_RGN1_INNER_WBNA (U(0x3) << 24)
305 #define TTBCR_EPD1_BIT (U(1) << 23)
306 #define TTBCR_A1_BIT (U(1) << 22)
308 #define TTBCR_T1SZ_SHIFT U(16)
309 #define TTBCR_T1SZ_MASK U(0x7)
310 #define TTBCR_TxSZ_MIN U(0)
311 #define TTBCR_TxSZ_MAX U(7)
313 #define TTBCR_SH0_NON_SHAREABLE (U(0x0) << 12)
314 #define TTBCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
315 #define TTBCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
317 #define TTBCR_RGN0_OUTER_NC (U(0x0) << 10)
318 #define TTBCR_RGN0_OUTER_WBA (U(0x1) << 10)
319 #define TTBCR_RGN0_OUTER_WT (U(0x2) << 10)
320 #define TTBCR_RGN0_OUTER_WBNA (U(0x3) << 10)
322 #define TTBCR_RGN0_INNER_NC (U(0x0) << 8)
323 #define TTBCR_RGN0_INNER_WBA (U(0x1) << 8)
324 #define TTBCR_RGN0_INNER_WT (U(0x2) << 8)
325 #define TTBCR_RGN0_INNER_WBNA (U(0x3) << 8)
327 #define TTBCR_EPD0_BIT (U(1) << 7)
328 #define TTBCR_T0SZ_SHIFT U(0)
329 #define TTBCR_T0SZ_MASK U(0x7)
334 #define HTCR_RES1 ((U(1) << 31) | (U(1) << 23))
336 #define HTCR_SH0_NON_SHAREABLE (U(0x0) << 12)
337 #define HTCR_SH0_OUTER_SHAREABLE (U(0x2) << 12)
338 #define HTCR_SH0_INNER_SHAREABLE (U(0x3) << 12)
340 #define HTCR_RGN0_OUTER_NC (U(0x0) << 10)
341 #define HTCR_RGN0_OUTER_WBA (U(0x1) << 10)
342 #define HTCR_RGN0_OUTER_WT (U(0x2) << 10)
343 #define HTCR_RGN0_OUTER_WBNA (U(0x3) << 10)
345 #define HTCR_RGN0_INNER_NC (U(0x0) << 8)
346 #define HTCR_RGN0_INNER_WBA (U(0x1) << 8)
347 #define HTCR_RGN0_INNER_WT (U(0x2) << 8)
348 #define HTCR_RGN0_INNER_WBNA (U(0x3) << 8)
350 #define HTCR_T0SZ_SHIFT U(0)
351 #define HTCR_T0SZ_MASK U(0x7)
353 #define MODE_RW_SHIFT U(0x4)
354 #define MODE_RW_MASK U(0x1)
355 #define MODE_RW_32 U(0x1)
357 #define MODE32_SHIFT U(0)
358 #define MODE32_MASK U(0x1f)
359 #define MODE32_usr U(0x10)
360 #define MODE32_fiq U(0x11)
361 #define MODE32_irq U(0x12)
362 #define MODE32_svc U(0x13)
363 #define MODE32_mon U(0x16)
364 #define MODE32_abt U(0x17)
365 #define MODE32_hyp U(0x1a)
366 #define MODE32_und U(0x1b)
367 #define MODE32_sys U(0x1f)
369 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
371 #define SPSR_MODE32(mode, isa, endian, aif) \
372 (MODE_RW_32 << MODE_RW_SHIFT | \
373 ((mode) & MODE32_MASK) << MODE32_SHIFT | \
374 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
375 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
376 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
381 #define TTBR_CNP_BIT ULL(0x1)
386 #define CTR_CWG_SHIFT U(24)
387 #define CTR_CWG_MASK U(0xf)
388 #define CTR_ERG_SHIFT U(20)
389 #define CTR_ERG_MASK U(0xf)
390 #define CTR_DMINLINE_SHIFT U(16)
391 #define CTR_DMINLINE_WIDTH U(4)
392 #define CTR_DMINLINE_MASK ((U(1) << 4) - U(1))
393 #define CTR_L1IP_SHIFT U(14)
394 #define CTR_L1IP_MASK U(0x3)
395 #define CTR_IMINLINE_SHIFT U(0)
396 #define CTR_IMINLINE_MASK U(0xf)
398 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
400 /* PMCR definitions */
401 #define PMCR_N_SHIFT U(11)
402 #define PMCR_N_MASK U(0x1f)
403 #define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
404 #define PMCR_LC_BIT (U(1) << 6)
405 #define PMCR_DP_BIT (U(1) << 5)
407 /*******************************************************************************
408 * Definitions of register offsets, fields and macros for CPU system
410 ******************************************************************************/
412 #define TLBI_ADDR_SHIFT U(0)
413 #define TLBI_ADDR_MASK U(0xFFFFF000)
414 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
416 /*******************************************************************************
417 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
418 * system level implementation of the Generic Timer.
419 ******************************************************************************/
420 #define CNTCTLBASE_CNTFRQ U(0x0)
421 #define CNTNSAR U(0x4)
422 #define CNTNSAR_NS_SHIFT(x) (x)
424 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
425 #define CNTACR_RPCT_SHIFT U(0x0)
426 #define CNTACR_RVCT_SHIFT U(0x1)
427 #define CNTACR_RFRQ_SHIFT U(0x2)
428 #define CNTACR_RVOFF_SHIFT U(0x3)
429 #define CNTACR_RWVT_SHIFT U(0x4)
430 #define CNTACR_RWPT_SHIFT U(0x5)
432 /*******************************************************************************
433 * Definitions of register offsets and fields in the CNTBaseN Frame of the
434 * system level implementation of the Generic Timer.
435 ******************************************************************************/
436 /* Physical Count register. */
437 #define CNTPCT_LO U(0x0)
438 /* Counter Frequency register. */
439 #define CNTBASEN_CNTFRQ U(0x10)
440 /* Physical Timer CompareValue register. */
441 #define CNTP_CVAL_LO U(0x20)
442 /* Physical Timer Control register. */
443 #define CNTP_CTL U(0x2c)
445 /* Physical timer control register bit fields shifts and masks */
446 #define CNTP_CTL_ENABLE_SHIFT 0
447 #define CNTP_CTL_IMASK_SHIFT 1
448 #define CNTP_CTL_ISTATUS_SHIFT 2
450 #define CNTP_CTL_ENABLE_MASK U(1)
451 #define CNTP_CTL_IMASK_MASK U(1)
452 #define CNTP_CTL_ISTATUS_MASK U(1)
455 #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3)))
456 #define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3)))
458 /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
459 #define SCR p15, 0, c1, c1, 0
460 #define SCTLR p15, 0, c1, c0, 0
461 #define ACTLR p15, 0, c1, c0, 1
462 #define SDCR p15, 0, c1, c3, 1
463 #define MPIDR p15, 0, c0, c0, 5
464 #define MIDR p15, 0, c0, c0, 0
465 #define HVBAR p15, 4, c12, c0, 0
466 #define VBAR p15, 0, c12, c0, 0
467 #define MVBAR p15, 0, c12, c0, 1
468 #define NSACR p15, 0, c1, c1, 2
469 #define CPACR p15, 0, c1, c0, 2
470 #define DCCIMVAC p15, 0, c7, c14, 1
471 #define DCCMVAC p15, 0, c7, c10, 1
472 #define DCIMVAC p15, 0, c7, c6, 1
473 #define DCCISW p15, 0, c7, c14, 2
474 #define DCCSW p15, 0, c7, c10, 2
475 #define DCISW p15, 0, c7, c6, 2
476 #define CTR p15, 0, c0, c0, 1
477 #define CNTFRQ p15, 0, c14, c0, 0
478 #define ID_PFR0 p15, 0, c0, c1, 0
479 #define ID_PFR1 p15, 0, c0, c1, 1
480 #define MAIR0 p15, 0, c10, c2, 0
481 #define MAIR1 p15, 0, c10, c2, 1
482 #define TTBCR p15, 0, c2, c0, 2
483 #define TTBR0 p15, 0, c2, c0, 0
484 #define TTBR1 p15, 0, c2, c0, 1
485 #define TLBIALL p15, 0, c8, c7, 0
486 #define TLBIALLH p15, 4, c8, c7, 0
487 #define TLBIALLIS p15, 0, c8, c3, 0
488 #define TLBIMVA p15, 0, c8, c7, 1
489 #define TLBIMVAA p15, 0, c8, c7, 3
490 #define TLBIMVAAIS p15, 0, c8, c3, 3
491 #define TLBIMVAHIS p15, 4, c8, c3, 1
492 #define BPIALLIS p15, 0, c7, c1, 6
493 #define BPIALL p15, 0, c7, c5, 6
494 #define ICIALLU p15, 0, c7, c5, 0
495 #define HSCTLR p15, 4, c1, c0, 0
496 #define HCR p15, 4, c1, c1, 0
497 #define HCPTR p15, 4, c1, c1, 2
498 #define HSTR p15, 4, c1, c1, 3
499 #define CNTHCTL p15, 4, c14, c1, 0
500 #define CNTKCTL p15, 0, c14, c1, 0
501 #define VPIDR p15, 4, c0, c0, 0
502 #define VMPIDR p15, 4, c0, c0, 5
503 #define ISR p15, 0, c12, c1, 0
504 #define CLIDR p15, 1, c0, c0, 1
505 #define CSSELR p15, 2, c0, c0, 0
506 #define CCSIDR p15, 1, c0, c0, 0
507 #define HTCR p15, 4, c2, c0, 2
508 #define HMAIR0 p15, 4, c10, c2, 0
509 #define ATS1CPR p15, 0, c7, c8, 0
510 #define ATS1HR p15, 4, c7, c8, 0
511 #define DBGOSDLR p14, 0, c1, c3, 4
513 /* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
514 #define HDCR p15, 4, c1, c1, 1
515 #define PMCR p15, 0, c9, c12, 0
516 #define CNTHP_TVAL p15, 4, c14, c2, 0
517 #define CNTHP_CTL p15, 4, c14, c2, 1
519 /* AArch32 coproc registers for 32bit MMU descriptor support */
520 #define PRRR p15, 0, c10, c2, 0
521 #define NMRR p15, 0, c10, c2, 1
522 #define DACR p15, 0, c3, c0, 0
524 /* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
525 #define ICC_IAR1 p15, 0, c12, c12, 0
526 #define ICC_IAR0 p15, 0, c12, c8, 0
527 #define ICC_EOIR1 p15, 0, c12, c12, 1
528 #define ICC_EOIR0 p15, 0, c12, c8, 1
529 #define ICC_HPPIR1 p15, 0, c12, c12, 2
530 #define ICC_HPPIR0 p15, 0, c12, c8, 2
531 #define ICC_BPR1 p15, 0, c12, c12, 3
532 #define ICC_BPR0 p15, 0, c12, c8, 3
533 #define ICC_DIR p15, 0, c12, c11, 1
534 #define ICC_PMR p15, 0, c4, c6, 0
535 #define ICC_RPR p15, 0, c12, c11, 3
536 #define ICC_CTLR p15, 0, c12, c12, 4
537 #define ICC_MCTLR p15, 6, c12, c12, 4
538 #define ICC_SRE p15, 0, c12, c12, 5
539 #define ICC_HSRE p15, 4, c12, c9, 5
540 #define ICC_MSRE p15, 6, c12, c12, 5
541 #define ICC_IGRPEN0 p15, 0, c12, c12, 6
542 #define ICC_IGRPEN1 p15, 0, c12, c12, 7
543 #define ICC_MGRPEN1 p15, 6, c12, c12, 7
545 /* 64 bit system register defines The format is: coproc, opt1, CRm */
546 #define TTBR0_64 p15, 0, c2
547 #define TTBR1_64 p15, 1, c2
548 #define CNTVOFF_64 p15, 4, c14
549 #define VTTBR_64 p15, 6, c2
550 #define CNTPCT_64 p15, 0, c14
551 #define HTTBR_64 p15, 4, c2
552 #define CNTHP_CVAL_64 p15, 6, c14
553 #define PAR_64 p15, 0, c7
555 /* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
556 #define ICC_SGI1R_EL1_64 p15, 0, c12
557 #define ICC_ASGI1R_EL1_64 p15, 1, c12
558 #define ICC_SGI0R_EL1_64 p15, 2, c12
560 /*******************************************************************************
561 * Definitions of MAIR encodings for device and normal memory
562 ******************************************************************************/
564 * MAIR encodings for device memory attributes.
566 #define MAIR_DEV_nGnRnE U(0x0)
567 #define MAIR_DEV_nGnRE U(0x4)
568 #define MAIR_DEV_nGRE U(0x8)
569 #define MAIR_DEV_GRE U(0xc)
572 * MAIR encodings for normal memory attributes.
586 * RWA: Read and Write Allocate
589 #define MAIR_NORM_WT_TR_WA U(0x1)
590 #define MAIR_NORM_WT_TR_RA U(0x2)
591 #define MAIR_NORM_WT_TR_RWA U(0x3)
592 #define MAIR_NORM_NC U(0x4)
593 #define MAIR_NORM_WB_TR_WA U(0x5)
594 #define MAIR_NORM_WB_TR_RA U(0x6)
595 #define MAIR_NORM_WB_TR_RWA U(0x7)
596 #define MAIR_NORM_WT_NTR_NA U(0x8)
597 #define MAIR_NORM_WT_NTR_WA U(0x9)
598 #define MAIR_NORM_WT_NTR_RA U(0xa)
599 #define MAIR_NORM_WT_NTR_RWA U(0xb)
600 #define MAIR_NORM_WB_NTR_NA U(0xc)
601 #define MAIR_NORM_WB_NTR_WA U(0xd)
602 #define MAIR_NORM_WB_NTR_RA U(0xe)
603 #define MAIR_NORM_WB_NTR_RWA U(0xf)
605 #define MAIR_NORM_OUTER_SHIFT U(4)
607 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
608 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
611 #define PAR_F_SHIFT U(0)
612 #define PAR_F_MASK ULL(0x1)
613 #define PAR_ADDR_SHIFT U(12)
614 #define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
616 /*******************************************************************************
617 * Definitions for system register interface to AMU for ARMv8.4 onwards
618 ******************************************************************************/
619 #define AMCR p15, 0, c13, c2, 0
620 #define AMCFGR p15, 0, c13, c2, 1
621 #define AMCGCR p15, 0, c13, c2, 2
622 #define AMUSERENR p15, 0, c13, c2, 3
623 #define AMCNTENCLR0 p15, 0, c13, c2, 4
624 #define AMCNTENSET0 p15, 0, c13, c2, 5
625 #define AMCNTENCLR1 p15, 0, c13, c3, 0
626 #define AMCNTENSET1 p15, 0, c13, c3, 1
628 /* Activity Monitor Group 0 Event Counter Registers */
629 #define AMEVCNTR00 p15, 0, c0
630 #define AMEVCNTR01 p15, 1, c0
631 #define AMEVCNTR02 p15, 2, c0
632 #define AMEVCNTR03 p15, 3, c0
634 /* Activity Monitor Group 0 Event Type Registers */
635 #define AMEVTYPER00 p15, 0, c13, c6, 0
636 #define AMEVTYPER01 p15, 0, c13, c6, 1
637 #define AMEVTYPER02 p15, 0, c13, c6, 2
638 #define AMEVTYPER03 p15, 0, c13, c6, 3
640 /* Activity Monitor Group 1 Event Counter Registers */
641 #define AMEVCNTR10 p15, 0, c4
642 #define AMEVCNTR11 p15, 1, c4
643 #define AMEVCNTR12 p15, 2, c4
644 #define AMEVCNTR13 p15, 3, c4
645 #define AMEVCNTR14 p15, 4, c4
646 #define AMEVCNTR15 p15, 5, c4
647 #define AMEVCNTR16 p15, 6, c4
648 #define AMEVCNTR17 p15, 7, c4
649 #define AMEVCNTR18 p15, 0, c5
650 #define AMEVCNTR19 p15, 1, c5
651 #define AMEVCNTR1A p15, 2, c5
652 #define AMEVCNTR1B p15, 3, c5
653 #define AMEVCNTR1C p15, 4, c5
654 #define AMEVCNTR1D p15, 5, c5
655 #define AMEVCNTR1E p15, 6, c5
656 #define AMEVCNTR1F p15, 7, c5
658 /* Activity Monitor Group 1 Event Type Registers */
659 #define AMEVTYPER10 p15, 0, c13, c14, 0
660 #define AMEVTYPER11 p15, 0, c13, c14, 1
661 #define AMEVTYPER12 p15, 0, c13, c14, 2
662 #define AMEVTYPER13 p15, 0, c13, c14, 3
663 #define AMEVTYPER14 p15, 0, c13, c14, 4
664 #define AMEVTYPER15 p15, 0, c13, c14, 5
665 #define AMEVTYPER16 p15, 0, c13, c14, 6
666 #define AMEVTYPER17 p15, 0, c13, c14, 7
667 #define AMEVTYPER18 p15, 0, c13, c15, 0
668 #define AMEVTYPER19 p15, 0, c13, c15, 1
669 #define AMEVTYPER1A p15, 0, c13, c15, 2
670 #define AMEVTYPER1B p15, 0, c13, c15, 3
671 #define AMEVTYPER1C p15, 0, c13, c15, 4
672 #define AMEVTYPER1D p15, 0, c13, c15, 5
673 #define AMEVTYPER1E p15, 0, c13, c15, 6
674 #define AMEVTYPER1F p15, 0, c13, c15, 7
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