72a14dcfa811d3bab08511439d2a5e7ba60270e0
2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
4 * SPDX-License-Identifier: BSD-3-Clause
10 #include <utils_def.h>
12 /*******************************************************************************
13 * MIDR bit definitions
14 ******************************************************************************/
15 #define MIDR_IMPL_MASK U(0xff)
16 #define MIDR_IMPL_SHIFT U(0x18)
17 #define MIDR_VAR_SHIFT U(20)
18 #define MIDR_VAR_BITS U(4)
19 #define MIDR_VAR_MASK U(0xf)
20 #define MIDR_REV_SHIFT U(0)
21 #define MIDR_REV_BITS U(4)
22 #define MIDR_REV_MASK U(0xf)
23 #define MIDR_PN_MASK U(0xfff)
24 #define MIDR_PN_SHIFT U(0x4)
26 /*******************************************************************************
28 ******************************************************************************/
29 #define MPIDR_MT_MASK (ULL(1) << 24)
30 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
31 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
32 #define MPIDR_AFFINITY_BITS U(8)
33 #define MPIDR_AFFLVL_MASK ULL(0xff)
34 #define MPIDR_AFF0_SHIFT U(0)
35 #define MPIDR_AFF1_SHIFT U(8)
36 #define MPIDR_AFF2_SHIFT U(16)
37 #define MPIDR_AFF3_SHIFT U(32)
38 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
39 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
40 #define MPIDR_AFFLVL_SHIFT U(3)
41 #define MPIDR_AFFLVL0 ULL(0x0)
42 #define MPIDR_AFFLVL1 ULL(0x1)
43 #define MPIDR_AFFLVL2 ULL(0x2)
44 #define MPIDR_AFFLVL3 ULL(0x3)
45 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
46 #define MPIDR_AFFLVL0_VAL(mpidr) \
47 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
48 #define MPIDR_AFFLVL1_VAL(mpidr) \
49 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
50 #define MPIDR_AFFLVL2_VAL(mpidr) \
51 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
52 #define MPIDR_AFFLVL3_VAL(mpidr) \
53 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
55 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
56 * add one while using this macro to define array sizes.
57 * TODO: Support only the first 3 affinity levels for now.
59 #define MPIDR_MAX_AFFLVL U(2)
61 #define MPID_MASK (MPIDR_MT_MASK | \
62 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67 #define MPIDR_AFF_ID(mpid, n) \
68 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
71 * An invalid MPID. This value can be used by functions that return an MPID to
74 #define INVALID_MPID U(0xFFFFFFFF)
76 /*******************************************************************************
77 * Definitions for CPU system register interface to GICv3
78 ******************************************************************************/
79 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
80 #define ICC_SGI1R S3_0_C12_C11_5
81 #define ICC_SRE_EL1 S3_0_C12_C12_5
82 #define ICC_SRE_EL2 S3_4_C12_C9_5
83 #define ICC_SRE_EL3 S3_6_C12_C12_5
84 #define ICC_CTLR_EL1 S3_0_C12_C12_4
85 #define ICC_CTLR_EL3 S3_6_C12_C12_4
86 #define ICC_PMR_EL1 S3_0_C4_C6_0
87 #define ICC_RPR_EL1 S3_0_C12_C11_3
88 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
89 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
90 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2
91 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2
92 #define ICC_IAR0_EL1 S3_0_c12_c8_0
93 #define ICC_IAR1_EL1 S3_0_c12_c12_0
94 #define ICC_EOIR0_EL1 S3_0_c12_c8_1
95 #define ICC_EOIR1_EL1 S3_0_c12_c12_1
96 #define ICC_SGI0R_EL1 S3_0_c12_c11_7
98 /*******************************************************************************
99 * Generic timer memory mapped registers & offsets
100 ******************************************************************************/
101 #define CNTCR_OFF U(0x000)
102 #define CNTFID_OFF U(0x020)
104 #define CNTCR_EN (U(1) << 0)
105 #define CNTCR_HDBG (U(1) << 1)
106 #define CNTCR_FCREQ(x) ((x) << 8)
108 /*******************************************************************************
109 * System register bit definitions
110 ******************************************************************************/
111 /* CLIDR definitions */
112 #define LOUIS_SHIFT U(21)
113 #define LOC_SHIFT U(24)
114 #define CLIDR_FIELD_WIDTH U(3)
116 /* CSSELR definitions */
117 #define LEVEL_SHIFT U(1)
119 /* Data cache set/way op type defines */
121 #define DCCISW U(0x1)
124 /* ID_AA64PFR0_EL1 definitions */
125 #define ID_AA64PFR0_EL0_SHIFT U(0)
126 #define ID_AA64PFR0_EL1_SHIFT U(4)
127 #define ID_AA64PFR0_EL2_SHIFT U(8)
128 #define ID_AA64PFR0_EL3_SHIFT U(12)
129 #define ID_AA64PFR0_AMU_SHIFT U(44)
130 #define ID_AA64PFR0_AMU_LENGTH U(4)
131 #define ID_AA64PFR0_AMU_MASK ULL(0xf)
132 #define ID_AA64PFR0_ELX_MASK ULL(0xf)
133 #define ID_AA64PFR0_SVE_SHIFT U(32)
134 #define ID_AA64PFR0_SVE_MASK ULL(0xf)
135 #define ID_AA64PFR0_SVE_LENGTH U(4)
136 #define ID_AA64PFR0_MPAM_SHIFT U(40)
137 #define ID_AA64PFR0_MPAM_MASK ULL(0xf)
138 #define ID_AA64PFR0_DIT_SHIFT U(48)
139 #define ID_AA64PFR0_DIT_MASK ULL(0xf)
140 #define ID_AA64PFR0_DIT_LENGTH U(4)
141 #define ID_AA64PFR0_DIT_SUPPORTED U(1)
142 #define ID_AA64PFR0_CSV2_SHIFT U(56)
143 #define ID_AA64PFR0_CSV2_MASK ULL(0xf)
144 #define ID_AA64PFR0_CSV2_LENGTH U(4)
146 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
147 #define ID_AA64DFR0_PMS_SHIFT U(32)
148 #define ID_AA64DFR0_PMS_LENGTH U(4)
149 #define ID_AA64DFR0_PMS_MASK ULL(0xf)
151 #define EL_IMPL_NONE ULL(0)
152 #define EL_IMPL_A64ONLY ULL(1)
153 #define EL_IMPL_A64_A32 ULL(2)
155 #define ID_AA64PFR0_GIC_SHIFT U(24)
156 #define ID_AA64PFR0_GIC_WIDTH U(4)
157 #define ID_AA64PFR0_GIC_MASK ((ULL(1) << ID_AA64PFR0_GIC_WIDTH) - ULL(1))
159 /* ID_AA64MMFR0_EL1 definitions */
160 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
161 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
163 /* ID_AA64ISAR1_EL1 definitions */
164 #define ID_AA64ISAR1_GPI_SHIFT U(28)
165 #define ID_AA64ISAR1_GPI_WIDTH U(4)
166 #define ID_AA64ISAR1_GPA_SHIFT U(24)
167 #define ID_AA64ISAR1_GPA_WIDTH U(4)
168 #define ID_AA64ISAR1_API_SHIFT U(8)
169 #define ID_AA64ISAR1_API_WIDTH U(4)
170 #define ID_AA64ISAR1_APA_SHIFT U(4)
171 #define ID_AA64ISAR1_APA_WIDTH U(4)
173 #define ID_AA64ISAR1_GPI_MASK \
174 (((ULL(1) << ID_AA64ISAR1_GPI_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPI_SHIFT)
175 #define ID_AA64ISAR1_GPA_MASK \
176 (((ULL(1) << ID_AA64ISAR1_GPA_WIDTH) - ULL(1)) << ID_AA64ISAR1_GPA_SHIFT)
177 #define ID_AA64ISAR1_API_MASK \
178 (((ULL(1) << ID_AA64ISAR1_API_WIDTH) - ULL(1)) << ID_AA64ISAR1_API_SHIFT)
179 #define ID_AA64ISAR1_APA_MASK \
180 (((ULL(1) << ID_AA64ISAR1_APA_WIDTH) - ULL(1)) << ID_AA64ISAR1_APA_SHIFT)
182 #define PARANGE_0000 U(32)
183 #define PARANGE_0001 U(36)
184 #define PARANGE_0010 U(40)
185 #define PARANGE_0011 U(42)
186 #define PARANGE_0100 U(44)
187 #define PARANGE_0101 U(48)
188 #define PARANGE_0110 U(52)
190 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
191 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
192 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
193 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
195 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
196 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
197 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
198 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
200 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
201 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
202 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
203 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
205 /* ID_AA64PFR1_EL1 definitions */
206 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
207 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
209 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
211 /* ID_PFR1_EL1 definitions */
212 #define ID_PFR1_VIRTEXT_SHIFT U(12)
213 #define ID_PFR1_VIRTEXT_MASK U(0xf)
214 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
215 & ID_PFR1_VIRTEXT_MASK)
217 /* SCTLR definitions */
218 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
219 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
220 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
222 #define SCTLR_EL1_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
223 (U(1) << 22) | (U(1) << 20) | (U(1) << 11))
224 #define SCTLR_AARCH32_EL1_RES1 \
225 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
226 (U(1) << 4) | (U(1) << 3))
228 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
229 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
230 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
232 #define SCTLR_M_BIT (ULL(1) << 0)
233 #define SCTLR_A_BIT (ULL(1) << 1)
234 #define SCTLR_C_BIT (ULL(1) << 2)
235 #define SCTLR_SA_BIT (ULL(1) << 3)
236 #define SCTLR_SA0_BIT (ULL(1) << 4)
237 #define SCTLR_CP15BEN_BIT (ULL(1) << 5)
238 #define SCTLR_ITD_BIT (ULL(1) << 7)
239 #define SCTLR_SED_BIT (ULL(1) << 8)
240 #define SCTLR_UMA_BIT (ULL(1) << 9)
241 #define SCTLR_I_BIT (ULL(1) << 12)
242 #define SCTLR_V_BIT (ULL(1) << 13)
243 #define SCTLR_DZE_BIT (ULL(1) << 14)
244 #define SCTLR_UCT_BIT (ULL(1) << 15)
245 #define SCTLR_NTWI_BIT (ULL(1) << 16)
246 #define SCTLR_NTWE_BIT (ULL(1) << 18)
247 #define SCTLR_WXN_BIT (ULL(1) << 19)
248 #define SCTLR_UWXN_BIT (ULL(1) << 20)
249 #define SCTLR_E0E_BIT (ULL(1) << 24)
250 #define SCTLR_EE_BIT (ULL(1) << 25)
251 #define SCTLR_UCI_BIT (ULL(1) << 26)
252 #define SCTLR_TRE_BIT (ULL(1) << 28)
253 #define SCTLR_AFE_BIT (ULL(1) << 29)
254 #define SCTLR_TE_BIT (ULL(1) << 30)
255 #define SCTLR_DSSBS_BIT (ULL(1) << 44)
256 #define SCTLR_RESET_VAL SCTLR_EL3_RES1
258 /* CPACR_El1 definitions */
259 #define CPACR_EL1_FPEN(x) ((x) << 20)
260 #define CPACR_EL1_FP_TRAP_EL0 U(0x1)
261 #define CPACR_EL1_FP_TRAP_ALL U(0x2)
262 #define CPACR_EL1_FP_TRAP_NONE U(0x3)
264 /* SCR definitions */
265 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
266 #define SCR_FIEN_BIT (U(1) << 21)
267 #define SCR_API_BIT (U(1) << 17)
268 #define SCR_APK_BIT (U(1) << 16)
269 #define SCR_TWE_BIT (U(1) << 13)
270 #define SCR_TWI_BIT (U(1) << 12)
271 #define SCR_ST_BIT (U(1) << 11)
272 #define SCR_RW_BIT (U(1) << 10)
273 #define SCR_SIF_BIT (U(1) << 9)
274 #define SCR_HCE_BIT (U(1) << 8)
275 #define SCR_SMD_BIT (U(1) << 7)
276 #define SCR_EA_BIT (U(1) << 3)
277 #define SCR_FIQ_BIT (U(1) << 2)
278 #define SCR_IRQ_BIT (U(1) << 1)
279 #define SCR_NS_BIT (U(1) << 0)
280 #define SCR_VALID_BIT_MASK U(0x2f8f)
281 #define SCR_RESET_VAL SCR_RES1_BITS
283 /* MDCR_EL3 definitions */
284 #define MDCR_SPD32(x) ((x) << 14)
285 #define MDCR_SPD32_LEGACY U(0x0)
286 #define MDCR_SPD32_DISABLE U(0x2)
287 #define MDCR_SPD32_ENABLE U(0x3)
288 #define MDCR_SDD_BIT (U(1) << 16)
289 #define MDCR_NSPB(x) ((x) << 12)
290 #define MDCR_NSPB_EL1 U(0x3)
291 #define MDCR_TDOSA_BIT (U(1) << 10)
292 #define MDCR_TDA_BIT (U(1) << 9)
293 #define MDCR_TPM_BIT (U(1) << 6)
294 #define MDCR_EL3_RESET_VAL U(0x0)
296 /* MDCR_EL2 definitions */
297 #define MDCR_EL2_TPMS (U(1) << 14)
298 #define MDCR_EL2_E2PB(x) ((x) << 12)
299 #define MDCR_EL2_E2PB_EL1 U(0x3)
300 #define MDCR_EL2_TDRA_BIT (U(1) << 11)
301 #define MDCR_EL2_TDOSA_BIT (U(1) << 10)
302 #define MDCR_EL2_TDA_BIT (U(1) << 9)
303 #define MDCR_EL2_TDE_BIT (U(1) << 8)
304 #define MDCR_EL2_HPME_BIT (U(1) << 7)
305 #define MDCR_EL2_TPM_BIT (U(1) << 6)
306 #define MDCR_EL2_TPMCR_BIT (U(1) << 5)
307 #define MDCR_EL2_RESET_VAL U(0x0)
309 /* HSTR_EL2 definitions */
310 #define HSTR_EL2_RESET_VAL U(0x0)
311 #define HSTR_EL2_T_MASK U(0xff)
313 /* CNTHP_CTL_EL2 definitions */
314 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
315 #define CNTHP_CTL_RESET_VAL U(0x0)
317 /* VTTBR_EL2 definitions */
318 #define VTTBR_RESET_VAL ULL(0x0)
319 #define VTTBR_VMID_MASK ULL(0xff)
320 #define VTTBR_VMID_SHIFT U(48)
321 #define VTTBR_BADDR_MASK ULL(0xffffffffffff)
322 #define VTTBR_BADDR_SHIFT U(0)
324 /* HCR definitions */
325 #define HCR_API_BIT (ULL(1) << 41)
326 #define HCR_APK_BIT (ULL(1) << 40)
327 #define HCR_TGE_BIT (ULL(1) << 27)
328 #define HCR_RW_SHIFT U(31)
329 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
330 #define HCR_AMO_BIT (ULL(1) << 5)
331 #define HCR_IMO_BIT (ULL(1) << 4)
332 #define HCR_FMO_BIT (ULL(1) << 3)
334 /* ISR definitions */
335 #define ISR_A_SHIFT U(8)
336 #define ISR_I_SHIFT U(7)
337 #define ISR_F_SHIFT U(6)
339 /* CNTHCTL_EL2 definitions */
340 #define CNTHCTL_RESET_VAL U(0x0)
341 #define EVNTEN_BIT (U(1) << 2)
342 #define EL1PCEN_BIT (U(1) << 1)
343 #define EL1PCTEN_BIT (U(1) << 0)
345 /* CNTKCTL_EL1 definitions */
346 #define EL0PTEN_BIT (U(1) << 9)
347 #define EL0VTEN_BIT (U(1) << 8)
348 #define EL0PCTEN_BIT (U(1) << 0)
349 #define EL0VCTEN_BIT (U(1) << 1)
350 #define EVNTEN_BIT (U(1) << 2)
351 #define EVNTDIR_BIT (U(1) << 3)
352 #define EVNTI_SHIFT U(4)
353 #define EVNTI_MASK U(0xf)
355 /* CPTR_EL3 definitions */
356 #define TCPAC_BIT (U(1) << 31)
357 #define TAM_BIT (U(1) << 30)
358 #define TTA_BIT (U(1) << 20)
359 #define TFP_BIT (U(1) << 10)
360 #define CPTR_EZ_BIT (U(1) << 8)
361 #define CPTR_EL3_RESET_VAL U(0x0)
363 /* CPTR_EL2 definitions */
364 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
365 #define CPTR_EL2_TCPAC_BIT (U(1) << 31)
366 #define CPTR_EL2_TAM_BIT (U(1) << 30)
367 #define CPTR_EL2_TTA_BIT (U(1) << 20)
368 #define CPTR_EL2_TFP_BIT (U(1) << 10)
369 #define CPTR_EL2_TZ_BIT (U(1) << 8)
370 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
372 /* CPSR/SPSR definitions */
373 #define DAIF_FIQ_BIT (U(1) << 0)
374 #define DAIF_IRQ_BIT (U(1) << 1)
375 #define DAIF_ABT_BIT (U(1) << 2)
376 #define DAIF_DBG_BIT (U(1) << 3)
377 #define SPSR_DAIF_SHIFT U(6)
378 #define SPSR_DAIF_MASK U(0xf)
380 #define SPSR_AIF_SHIFT U(6)
381 #define SPSR_AIF_MASK U(0x7)
383 #define SPSR_E_SHIFT U(9)
384 #define SPSR_E_MASK U(0x1)
385 #define SPSR_E_LITTLE U(0x0)
386 #define SPSR_E_BIG U(0x1)
388 #define SPSR_T_SHIFT U(5)
389 #define SPSR_T_MASK U(0x1)
390 #define SPSR_T_ARM U(0x0)
391 #define SPSR_T_THUMB U(0x1)
393 #define SPSR_M_SHIFT U(4)
394 #define SPSR_M_MASK U(0x1)
395 #define SPSR_M_AARCH64 U(0x0)
396 #define SPSR_M_AARCH32 U(0x1)
398 #define DISABLE_ALL_EXCEPTIONS \
399 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
401 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
404 * RMR_EL3 definitions
406 #define RMR_EL3_RR_BIT (U(1) << 1)
407 #define RMR_EL3_AA64_BIT (U(1) << 0)
410 * HI-VECTOR address for AArch32 state
412 #define HI_VECTOR_BASE U(0xFFFF0000)
417 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
418 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
419 #define TCR_EL1_IPS_SHIFT U(32)
420 #define TCR_EL2_PS_SHIFT U(16)
421 #define TCR_EL3_PS_SHIFT U(16)
423 #define TCR_TxSZ_MIN ULL(16)
424 #define TCR_TxSZ_MAX ULL(39)
426 /* (internal) physical address size bits in EL3/EL1 */
427 #define TCR_PS_BITS_4GB ULL(0x0)
428 #define TCR_PS_BITS_64GB ULL(0x1)
429 #define TCR_PS_BITS_1TB ULL(0x2)
430 #define TCR_PS_BITS_4TB ULL(0x3)
431 #define TCR_PS_BITS_16TB ULL(0x4)
432 #define TCR_PS_BITS_256TB ULL(0x5)
434 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
435 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
436 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
437 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
438 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
439 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
441 #define TCR_RGN_INNER_NC (ULL(0x0) << 8)
442 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
443 #define TCR_RGN_INNER_WT (ULL(0x2) << 8)
444 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
446 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
447 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
448 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
449 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
451 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
452 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
453 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
455 #define TCR_TG0_SHIFT U(14)
456 #define TCR_TG0_MASK ULL(3)
457 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
458 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
459 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
461 #define TCR_EPD0_BIT (ULL(1) << 7)
462 #define TCR_EPD1_BIT (ULL(1) << 23)
464 #define MODE_SP_SHIFT U(0x0)
465 #define MODE_SP_MASK U(0x1)
466 #define MODE_SP_EL0 U(0x0)
467 #define MODE_SP_ELX U(0x1)
469 #define MODE_RW_SHIFT U(0x4)
470 #define MODE_RW_MASK U(0x1)
471 #define MODE_RW_64 U(0x0)
472 #define MODE_RW_32 U(0x1)
474 #define MODE_EL_SHIFT U(0x2)
475 #define MODE_EL_MASK U(0x3)
476 #define MODE_EL3 U(0x3)
477 #define MODE_EL2 U(0x2)
478 #define MODE_EL1 U(0x1)
479 #define MODE_EL0 U(0x0)
481 #define MODE32_SHIFT U(0)
482 #define MODE32_MASK U(0xf)
483 #define MODE32_usr U(0x0)
484 #define MODE32_fiq U(0x1)
485 #define MODE32_irq U(0x2)
486 #define MODE32_svc U(0x3)
487 #define MODE32_mon U(0x6)
488 #define MODE32_abt U(0x7)
489 #define MODE32_hyp U(0xa)
490 #define MODE32_und U(0xb)
491 #define MODE32_sys U(0xf)
493 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
494 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
495 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
496 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
498 #define SPSR_64(el, sp, daif) \
499 ((MODE_RW_64 << MODE_RW_SHIFT) | \
500 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
501 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
502 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT))
504 #define SPSR_MODE32(mode, isa, endian, aif) \
505 ((MODE_RW_32 << MODE_RW_SHIFT) | \
506 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
507 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
508 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
509 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT))
514 #define TTBR_CNP_BIT ULL(0x1)
517 * CTR_EL0 definitions
519 #define CTR_CWG_SHIFT U(24)
520 #define CTR_CWG_MASK U(0xf)
521 #define CTR_ERG_SHIFT U(20)
522 #define CTR_ERG_MASK U(0xf)
523 #define CTR_DMINLINE_SHIFT U(16)
524 #define CTR_DMINLINE_MASK U(0xf)
525 #define CTR_L1IP_SHIFT U(14)
526 #define CTR_L1IP_MASK U(0x3)
527 #define CTR_IMINLINE_SHIFT U(0)
528 #define CTR_IMINLINE_MASK U(0xf)
530 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
532 /* Physical timer control register bit fields shifts and masks */
533 #define CNTP_CTL_ENABLE_SHIFT U(0)
534 #define CNTP_CTL_IMASK_SHIFT U(1)
535 #define CNTP_CTL_ISTATUS_SHIFT U(2)
537 #define CNTP_CTL_ENABLE_MASK U(1)
538 #define CNTP_CTL_IMASK_MASK U(1)
539 #define CNTP_CTL_ISTATUS_MASK U(1)
541 /* Exception Syndrome register bits and bobs */
542 #define ESR_EC_SHIFT U(26)
543 #define ESR_EC_MASK U(0x3f)
544 #define ESR_EC_LENGTH U(6)
545 #define EC_UNKNOWN U(0x0)
546 #define EC_WFE_WFI U(0x1)
547 #define EC_AARCH32_CP15_MRC_MCR U(0x3)
548 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
549 #define EC_AARCH32_CP14_MRC_MCR U(0x5)
550 #define EC_AARCH32_CP14_LDC_STC U(0x6)
551 #define EC_FP_SIMD U(0x7)
552 #define EC_AARCH32_CP10_MRC U(0x8)
553 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
554 #define EC_ILLEGAL U(0xe)
555 #define EC_AARCH32_SVC U(0x11)
556 #define EC_AARCH32_HVC U(0x12)
557 #define EC_AARCH32_SMC U(0x13)
558 #define EC_AARCH64_SVC U(0x15)
559 #define EC_AARCH64_HVC U(0x16)
560 #define EC_AARCH64_SMC U(0x17)
561 #define EC_AARCH64_SYS U(0x18)
562 #define EC_IABORT_LOWER_EL U(0x20)
563 #define EC_IABORT_CUR_EL U(0x21)
564 #define EC_PC_ALIGN U(0x22)
565 #define EC_DABORT_LOWER_EL U(0x24)
566 #define EC_DABORT_CUR_EL U(0x25)
567 #define EC_SP_ALIGN U(0x26)
568 #define EC_AARCH32_FP U(0x28)
569 #define EC_AARCH64_FP U(0x2c)
570 #define EC_SERROR U(0x2f)
573 * External Abort bit in Instruction and Data Aborts synchronous exception
576 #define ESR_ISS_EABORT_EA_BIT U(9)
578 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
580 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
581 #define RMR_RESET_REQUEST_SHIFT U(0x1)
582 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
584 /*******************************************************************************
585 * Definitions of register offsets, fields and macros for CPU system
587 ******************************************************************************/
589 #define TLBI_ADDR_SHIFT U(12)
590 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
591 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
593 /*******************************************************************************
594 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
595 * system level implementation of the Generic Timer.
596 ******************************************************************************/
597 #define CNTCTLBASE_CNTFRQ U(0x0)
598 #define CNTNSAR U(0x4)
599 #define CNTNSAR_NS_SHIFT(x) (x)
601 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
602 #define CNTACR_RPCT_SHIFT U(0x0)
603 #define CNTACR_RVCT_SHIFT U(0x1)
604 #define CNTACR_RFRQ_SHIFT U(0x2)
605 #define CNTACR_RVOFF_SHIFT U(0x3)
606 #define CNTACR_RWVT_SHIFT U(0x4)
607 #define CNTACR_RWPT_SHIFT U(0x5)
609 /*******************************************************************************
610 * Definitions of register offsets and fields in the CNTBaseN Frame of the
611 * system level implementation of the Generic Timer.
612 ******************************************************************************/
613 /* Physical Count register. */
614 #define CNTPCT_LO U(0x0)
615 /* Counter Frequency register. */
616 #define CNTBASEN_CNTFRQ U(0x10)
617 /* Physical Timer CompareValue register. */
618 #define CNTP_CVAL_LO U(0x20)
619 /* Physical Timer Control register. */
620 #define CNTP_CTL U(0x2c)
622 /* PMCR_EL0 definitions */
623 #define PMCR_EL0_RESET_VAL U(0x0)
624 #define PMCR_EL0_N_SHIFT U(11)
625 #define PMCR_EL0_N_MASK U(0x1f)
626 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
627 #define PMCR_EL0_LC_BIT (U(1) << 6)
628 #define PMCR_EL0_DP_BIT (U(1) << 5)
629 #define PMCR_EL0_X_BIT (U(1) << 4)
630 #define PMCR_EL0_D_BIT (U(1) << 3)
632 /*******************************************************************************
633 * Definitions for system register interface to SVE
634 ******************************************************************************/
635 #define ZCR_EL3 S3_6_C1_C2_0
636 #define ZCR_EL2 S3_4_C1_C2_0
638 /* ZCR_EL3 definitions */
639 #define ZCR_EL3_LEN_MASK U(0xf)
641 /* ZCR_EL2 definitions */
642 #define ZCR_EL2_LEN_MASK U(0xf)
644 /*******************************************************************************
645 * Definitions of MAIR encodings for device and normal memory
646 ******************************************************************************/
648 * MAIR encodings for device memory attributes.
650 #define MAIR_DEV_nGnRnE ULL(0x0)
651 #define MAIR_DEV_nGnRE ULL(0x4)
652 #define MAIR_DEV_nGRE ULL(0x8)
653 #define MAIR_DEV_GRE ULL(0xc)
656 * MAIR encodings for normal memory attributes.
670 * RWA: Read and Write Allocate
673 #define MAIR_NORM_WT_TR_WA ULL(0x1)
674 #define MAIR_NORM_WT_TR_RA ULL(0x2)
675 #define MAIR_NORM_WT_TR_RWA ULL(0x3)
676 #define MAIR_NORM_NC ULL(0x4)
677 #define MAIR_NORM_WB_TR_WA ULL(0x5)
678 #define MAIR_NORM_WB_TR_RA ULL(0x6)
679 #define MAIR_NORM_WB_TR_RWA ULL(0x7)
680 #define MAIR_NORM_WT_NTR_NA ULL(0x8)
681 #define MAIR_NORM_WT_NTR_WA ULL(0x9)
682 #define MAIR_NORM_WT_NTR_RA ULL(0xa)
683 #define MAIR_NORM_WT_NTR_RWA ULL(0xb)
684 #define MAIR_NORM_WB_NTR_NA ULL(0xc)
685 #define MAIR_NORM_WB_NTR_WA ULL(0xd)
686 #define MAIR_NORM_WB_NTR_RA ULL(0xe)
687 #define MAIR_NORM_WB_NTR_RWA ULL(0xf)
689 #define MAIR_NORM_OUTER_SHIFT U(4)
691 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
692 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
695 #define PAR_F_SHIFT U(0)
696 #define PAR_F_MASK ULL(0x1)
697 #define PAR_ADDR_SHIFT U(12)
698 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
700 /*******************************************************************************
701 * Definitions for system register interface to SPE
702 ******************************************************************************/
703 #define PMBLIMITR_EL1 S3_0_C9_C10_0
705 /*******************************************************************************
706 * Definitions for system register interface to MPAM
707 ******************************************************************************/
708 #define MPAMIDR_EL1 S3_0_C10_C4_4
709 #define MPAM2_EL2 S3_4_C10_C5_0
710 #define MPAMHCR_EL2 S3_4_C10_C4_0
711 #define MPAM3_EL3 S3_6_C10_C5_0
713 /*******************************************************************************
714 * Definitions for system register interface to AMU for ARMv8.4 onwards
715 ******************************************************************************/
716 #define AMCR_EL0 S3_3_C13_C2_0
717 #define AMCFGR_EL0 S3_3_C13_C2_1
718 #define AMCGCR_EL0 S3_3_C13_C2_2
719 #define AMUSERENR_EL0 S3_3_C13_C2_3
720 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4
721 #define AMCNTENSET0_EL0 S3_3_C13_C2_5
722 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0
723 #define AMCNTENSET1_EL0 S3_3_C13_C3_1
725 /* Activity Monitor Group 0 Event Counter Registers */
726 #define AMEVCNTR00_EL0 S3_3_C13_C4_0
727 #define AMEVCNTR01_EL0 S3_3_C13_C4_1
728 #define AMEVCNTR02_EL0 S3_3_C13_C4_2
729 #define AMEVCNTR03_EL0 S3_3_C13_C4_3
731 /* Activity Monitor Group 0 Event Type Registers */
732 #define AMEVTYPER00_EL0 S3_3_C13_C6_0
733 #define AMEVTYPER01_EL0 S3_3_C13_C6_1
734 #define AMEVTYPER02_EL0 S3_3_C13_C6_2
735 #define AMEVTYPER03_EL0 S3_3_C13_C6_3
737 /* Activity Monitor Group 1 Event Counter Registers */
738 #define AMEVCNTR10_EL0 S3_3_C13_C12_0
739 #define AMEVCNTR11_EL0 S3_3_C13_C12_1
740 #define AMEVCNTR12_EL0 S3_3_C13_C12_2
741 #define AMEVCNTR13_EL0 S3_3_C13_C12_3
742 #define AMEVCNTR14_EL0 S3_3_C13_C12_4
743 #define AMEVCNTR15_EL0 S3_3_C13_C12_5
744 #define AMEVCNTR16_EL0 S3_3_C13_C12_6
745 #define AMEVCNTR17_EL0 S3_3_C13_C12_7
746 #define AMEVCNTR18_EL0 S3_3_C13_C13_0
747 #define AMEVCNTR19_EL0 S3_3_C13_C13_1
748 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2
749 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3
750 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4
751 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5
752 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6
753 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7
755 /* Activity Monitor Group 1 Event Type Registers */
756 #define AMEVTYPER10_EL0 S3_3_C13_C14_0
757 #define AMEVTYPER11_EL0 S3_3_C13_C14_1
758 #define AMEVTYPER12_EL0 S3_3_C13_C14_2
759 #define AMEVTYPER13_EL0 S3_3_C13_C14_3
760 #define AMEVTYPER14_EL0 S3_3_C13_C14_4
761 #define AMEVTYPER15_EL0 S3_3_C13_C14_5
762 #define AMEVTYPER16_EL0 S3_3_C13_C14_6
763 #define AMEVTYPER17_EL0 S3_3_C13_C14_7
764 #define AMEVTYPER18_EL0 S3_3_C13_C15_0
765 #define AMEVTYPER19_EL0 S3_3_C13_C15_1
766 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2
767 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3
768 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4
769 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5
770 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6
771 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7
773 /* AMCGCR_EL0 definitions */
774 #define AMCGCR_EL0_CG1NC_SHIFT U(8)
775 #define AMCGCR_EL0_CG1NC_LENGTH U(8)
776 #define AMCGCR_EL0_CG1NC_MASK U(0xff)
778 /* MPAM register definitions */
779 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
781 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
783 /*******************************************************************************
784 * RAS system registers
785 ******************************************************************************/
786 #define DISR_EL1 S3_0_C12_C1_1
787 #define DISR_A_BIT U(31)
789 #define ERRIDR_EL1 S3_0_C5_C3_0
790 #define ERRIDR_MASK U(0xffff)
792 #define ERRSELR_EL1 S3_0_C5_C3_1
794 /* System register access to Standard Error Record registers */
795 #define ERXFR_EL1 S3_0_C5_C4_0
796 #define ERXCTLR_EL1 S3_0_C5_C4_1
797 #define ERXSTATUS_EL1 S3_0_C5_C4_2
798 #define ERXADDR_EL1 S3_0_C5_C4_3
799 #define ERXPFGF_EL1 S3_0_C5_C4_4
800 #define ERXPFGCTL_EL1 S3_0_C5_C4_5
801 #define ERXPFGCDN_EL1 S3_0_C5_C4_6
802 #define ERXMISC0_EL1 S3_0_C5_C5_0
803 #define ERXMISC1_EL1 S3_0_C5_C5_1
805 #define ERXCTLR_ED_BIT (U(1) << 0)
806 #define ERXCTLR_UE_BIT (U(1) << 4)
808 #define ERXPFGCTL_UC_BIT (U(1) << 1)
809 #define ERXPFGCTL_UEU_BIT (U(1) << 2)
810 #define ERXPFGCTL_CDEN_BIT (U(1) << 31)
812 /*******************************************************************************
813 * Armv8.3 Pointer Authentication Registers
814 ******************************************************************************/
815 #define APGAKeyLo_EL1 S3_0_C2_C3_0
817 /*******************************************************************************
818 * Armv8.4 Data Independent Timing Registers
819 ******************************************************************************/
820 #define DIT S3_3_C4_C2_5
821 #define DIT_BIT BIT(24)
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