include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T2080 RDB/PCIe board configuration file
   8  */
   9
  10 #ifndef __T2080RDB_H
  11 #define __T2080RDB_H
  12
  13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  14 #define CONFIG_FSL_SATA_V2
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #ifdef CONFIG_PHYS_64BIT
  21 #define CONFIG_ADDR_MAP 1
  22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  23 #endif
  24
  25 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  26 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  31
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_PAD_TO               0x40000
  34 #define CONFIG_SPL_MAX_SIZE             0x28000
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_SKIP_RELOCATE
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41 #endif
  42
  43 #ifdef CONFIG_NAND
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  48 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  50 #endif
  51
  52 #ifdef CONFIG_SPIFLASH
  53 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  59 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  60 #ifndef CONFIG_SPL_BUILD
  61 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  62 #endif
  63 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  64 #endif
  65
  66 #ifdef CONFIG_SDCARD
  67 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  68 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  69 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  70 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  71 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  72 #define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  73 #ifndef CONFIG_SPL_BUILD
  74 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  75 #endif
  76 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  77 #endif
  78
  79 #endif /* CONFIG_RAMBOOT_PBL */
  80
  81 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  82 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  83 /* Set 1M boot space */
  84 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  85 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  86                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  87 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  88 #endif
  89
  90 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  91 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  92 #endif
  93
  94 /*
  95  * These can be toggled for performance analysis, otherwise use default.
  96  */
  97 #define CONFIG_SYS_CACHE_STASHING
  98 #define CONFIG_BTB              /* toggle branch predition */
  99 #define CONFIG_DDR_ECC
 100 #ifdef CONFIG_DDR_ECC
 101 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 102 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 103 #endif
 104
 105 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 106 #define CONFIG_SYS_MEMTEST_END          0x00400000
 107
 108 #if defined(CONFIG_SPIFLASH)
 109 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 110 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 111 #define CONFIG_ENV_SECT_SIZE    0x10000
 112 #elif defined(CONFIG_SDCARD)
 113 #define CONFIG_SYS_MMC_ENV_DEV  0
 114 #define CONFIG_ENV_SIZE         0x2000
 115 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 116 #elif defined(CONFIG_NAND)
 117 #define CONFIG_ENV_SIZE         0x2000
 118 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 120 #define CONFIG_ENV_ADDR         0xffe20000
 121 #define CONFIG_ENV_SIZE         0x2000
 122 #elif defined(CONFIG_ENV_IS_NOWHERE)
 123 #define CONFIG_ENV_SIZE         0x2000
 124 #else
 125 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 126 #define CONFIG_ENV_SIZE         0x2000
 127 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 128 #endif
 129
 130 #ifndef __ASSEMBLY__
 131 unsigned long get_board_sys_clk(void);
 132 unsigned long get_board_ddr_clk(void);
 133 #endif
 134
 135 #define CONFIG_SYS_CLK_FREQ     66660000
 136 #define CONFIG_DDR_CLK_FREQ     133330000
 137
 138 /*
 139  * Config the L3 Cache as L3 SRAM
 140  */
 141 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 142 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 143 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 144 #ifdef CONFIG_RAMBOOT_PBL
 145 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 146 #endif
 147 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 148 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 149 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 150
 151 #define CONFIG_SYS_DCSRBAR      0xf0000000
 152 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 153
 154 /* EEPROM */
 155 #define CONFIG_ID_EEPROM
 156 #define CONFIG_SYS_I2C_EEPROM_NXID
 157 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 158 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 160
 161 /*
 162  * DDR Setup
 163  */
 164 #define CONFIG_VERY_BIG_RAM
 165 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 166 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 167 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 168 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 169 #define CONFIG_DDR_SPD
 170 #define CONFIG_SYS_SPD_BUS_NUM  0
 171 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 172 #define SPD_EEPROM_ADDRESS1     0x51
 173 #define SPD_EEPROM_ADDRESS2     0x52
 174 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 175 #define CTRL_INTLV_PREFERED     cacheline
 176
 177 /*
 178  * IFC Definitions
 179  */
 180 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 181 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 182 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 183 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 184                                 CSPR_PORT_SIZE_16 | \
 185                                 CSPR_MSEL_NOR | \
 186                                 CSPR_V)
 187 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 188
 189 /* NOR Flash Timing Params */
 190 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 191
 192 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 193                                 FTIM0_NOR_TEADC(0x5) | \
 194                                 FTIM0_NOR_TEAHC(0x5))
 195 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 196                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 197                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 198 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 199                                 FTIM2_NOR_TCH(0x4) | \
 200                                 FTIM2_NOR_TWPH(0x0E) | \
 201                                 FTIM2_NOR_TWP(0x1c))
 202 #define CONFIG_SYS_NOR_FTIM3    0x0
 203
 204 #define CONFIG_SYS_FLASH_QUIET_TEST
 205 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 206
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 209 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 210 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 211 #define CONFIG_SYS_FLASH_EMPTY_INFO
 212 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 213
 214 /* CPLD on IFC */
 215 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 216 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 217 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 218 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 219                                 | CSPR_PORT_SIZE_8 \
 220                                 | CSPR_MSEL_GPCM \
 221                                 | CSPR_V)
 222 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 223 #define CONFIG_SYS_CSOR2        0x0
 224
 225 /* CPLD Timing parameters for IFC CS2 */
 226 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 227                                         FTIM0_GPCM_TEADC(0x0e) | \
 228                                         FTIM0_GPCM_TEAHC(0x0e))
 229 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 230                                         FTIM1_GPCM_TRAD(0x1f))
 231 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 232                                         FTIM2_GPCM_TCH(0x8) | \
 233                                         FTIM2_GPCM_TWP(0x1f))
 234 #define CONFIG_SYS_CS2_FTIM3            0x0
 235
 236 /* NAND Flash on IFC */
 237 #define CONFIG_NAND_FSL_IFC
 238 #define CONFIG_SYS_NAND_BASE            0xff800000
 239 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 240
 241 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 242 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 243                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 244                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 245                                 | CSPR_V)
 246 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 247
 248 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 249                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 250                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 251                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 252                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 253                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 254                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 255
 256 #define CONFIG_SYS_NAND_ONFI_DETECTION
 257
 258 /* ONFI NAND Flash mode0 Timing Params */
 259 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 260                                         FTIM0_NAND_TWP(0x18)    | \
 261                                         FTIM0_NAND_TWCHT(0x07)  | \
 262                                         FTIM0_NAND_TWH(0x0a))
 263 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 264                                         FTIM1_NAND_TWBE(0x39)   | \
 265                                         FTIM1_NAND_TRR(0x0e)    | \
 266                                         FTIM1_NAND_TRP(0x18))
 267 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 268                                         FTIM2_NAND_TREH(0x0a)   | \
 269                                         FTIM2_NAND_TWHRE(0x1e))
 270 #define CONFIG_SYS_NAND_FTIM3           0x0
 271
 272 #define CONFIG_SYS_NAND_DDR_LAW         11
 273 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 274 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 275 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 276
 277 #if defined(CONFIG_NAND)
 278 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 279 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 280 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 281 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 282 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 283 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 284 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 285 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 286 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 287 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 288 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 289 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 290 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 291 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 292 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 293 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 294 #else
 295 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 296 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 297 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 298 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 299 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 300 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 301 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 302 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 303 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 304 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 305 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 306 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 307 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 308 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 309 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 310 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 311 #endif
 312
 313 #if defined(CONFIG_RAMBOOT_PBL)
 314 #define CONFIG_SYS_RAMBOOT
 315 #endif
 316
 317 #ifdef CONFIG_SPL_BUILD
 318 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 319 #else
 320 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 321 #endif
 322
 323 #define CONFIG_HWCONFIG
 324
 325 /* define to use L1 as initial stack */
 326 #define CONFIG_L1_INIT_RAM
 327 #define CONFIG_SYS_INIT_RAM_LOCK
 328 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 329 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 330 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 331 /* The assembler doesn't like typecast */
 332 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 333                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 334                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 335 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 336 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 337                                                 GENERATED_GBL_DATA_SIZE)
 338 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 339 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 340 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 341
 342 /*
 343  * Serial Port
 344  */
 345 #define CONFIG_SYS_NS16550_SERIAL
 346 #define CONFIG_SYS_NS16550_REG_SIZE     1
 347 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 348 #define CONFIG_SYS_BAUDRATE_TABLE       \
 349         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 350 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 351 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 352 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 353 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 354
 355 /*
 356  * I2C
 357  */
 358 #define CONFIG_SYS_I2C
 359 #define CONFIG_SYS_I2C_FSL
 360 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 361 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 362 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 363 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 364 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 365 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 366 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 367 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 368 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 369 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 370 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 371 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 372 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 373 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 374 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 375 #define I2C_MUX_CH_DEFAULT      0x8
 376
 377 #define I2C_MUX_CH_VOL_MONITOR  0xa
 378
 379 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 380 #ifndef CONFIG_SPL_BUILD
 381 #define CONFIG_VID
 382 #endif
 383 #define CONFIG_VOL_MONITOR_IR36021_SET
 384 #define CONFIG_VOL_MONITOR_IR36021_READ
 385 /* The lowest and highest voltage allowed for T208xRDB */
 386 #define VDD_MV_MIN                      819
 387 #define VDD_MV_MAX                      1212
 388
 389 /*
 390  * RapidIO
 391  */
 392 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 393 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 394 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 395 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 396 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 397 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 398 /*
 399  * for slave u-boot IMAGE instored in master memory space,
 400  * PHYS must be aligned based on the SIZE
 401  */
 402 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 403 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 404 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 405 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 406 /*
 407  * for slave UCODE and ENV instored in master memory space,
 408  * PHYS must be aligned based on the SIZE
 409  */
 410 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 411 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 412 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 413
 414 /* slave core release by master*/
 415 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 416 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 417
 418 /*
 419  * SRIO_PCIE_BOOT - SLAVE
 420  */
 421 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 422 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 423 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 424                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 425 #endif
 426
 427 /*
 428  * eSPI - Enhanced SPI
 429  */
 430
 431 /*
 432  * General PCI
 433  * Memory space is mapped 1-1, but I/O space must start from 0.
 434  */
 435 #define CONFIG_PCIE1            /* PCIE controller 1 */
 436 #define CONFIG_PCIE2            /* PCIE controller 2 */
 437 #define CONFIG_PCIE3            /* PCIE controller 3 */
 438 #define CONFIG_PCIE4            /* PCIE controller 4 */
 439 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 440 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 441 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 442 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 443 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 444 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 445 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 446 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 447 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 448 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 449 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 450
 451 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 452 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 453 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 454 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 455 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 456 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 457 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 458 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 459 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 460
 461 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 462 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 463 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 464 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 465 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 466 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 467 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 468 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 469 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 470
 471 /* controller 4, Base address 203000 */
 472 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 473 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 474 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 475 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 476 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 477 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 478 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 479
 480 #ifdef CONFIG_PCI
 481 #define CONFIG_PCI_INDIRECT_BRIDGE
 482 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 483 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 484 #endif
 485
 486 /* Qman/Bman */
 487 #ifndef CONFIG_NOBQFMAN
 488 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 489 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 490 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 491 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 492 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 493 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 494 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 495 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 496 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 497                                         CONFIG_SYS_BMAN_CENA_SIZE)
 498 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 499 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 500 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 501 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 502 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 503 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 504 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 505 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 506 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 507 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 508 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 509                                         CONFIG_SYS_QMAN_CENA_SIZE)
 510 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 511 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 512
 513 #define CONFIG_SYS_DPAA_FMAN
 514 #define CONFIG_SYS_DPAA_PME
 515 #define CONFIG_SYS_PMAN
 516 #define CONFIG_SYS_DPAA_DCE
 517 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 518 #define CONFIG_SYS_INTERLAKEN
 519
 520 /* Default address of microcode for the Linux Fman driver */
 521 #if defined(CONFIG_SPIFLASH)
 522 /*
 523  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 524  * env, so we got 0x110000.
 525  */
 526 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 527 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 528 #define CONFIG_CORTINA_FW_ADDR          0x120000
 529
 530 #elif defined(CONFIG_SDCARD)
 531 /*
 532  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 533  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 534  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 535  */
 536 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 537 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 538 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 539
 540 #elif defined(CONFIG_NAND)
 541 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 542 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 543 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 544 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 545 /*
 546  * Slave has no ucode locally, it can fetch this from remote. When implementing
 547  * in two corenet boards, slave's ucode could be stored in master's memory
 548  * space, the address can be mapped from slave TLB->slave LAW->
 549  * slave SRIO or PCIE outbound window->master inbound window->
 550  * master LAW->the ucode address in master's memory space.
 551  */
 552 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 553 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 554 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 555 #else
 556 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 557 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 558 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 559 #endif
 560 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 561 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 562 #endif /* CONFIG_NOBQFMAN */
 563
 564 #ifdef CONFIG_SYS_DPAA_FMAN
 565 #define CONFIG_PHY_CORTINA
 566 #define CONFIG_PHY_REALTEK
 567 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 568 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 569 #define RGMII_PHY2_ADDR         0x02
 570 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 571 #define CORTINA_PHY_ADDR2       0x0d
 572 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 573 #define FM1_10GEC4_PHY_ADDR     0x01
 574 #endif
 575
 576 #ifdef CONFIG_FMAN_ENET
 577 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 578 #endif
 579
 580 /*
 581  * SATA
 582  */
 583 #ifdef CONFIG_FSL_SATA_V2
 584 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 585 #define CONFIG_SATA1
 586 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 587 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 588 #define CONFIG_SATA2
 589 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 590 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 591 #define CONFIG_LBA48
 592 #endif
 593
 594 /*
 595  * USB
 596  */
 597 #ifdef CONFIG_USB_EHCI_HCD
 598 #define CONFIG_USB_EHCI_FSL
 599 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 600 #define CONFIG_HAS_FSL_DR_USB
 601 #endif
 602
 603 /*
 604  * SDHC
 605  */
 606 #ifdef CONFIG_MMC
 607 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 608 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 609 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 610 #endif
 611
 612 /*
 613  * Dynamic MTD Partition support with mtdparts
 614  */
 615
 616 /*
 617  * Environment
 618  */
 619
 620 /*
 621  * Miscellaneous configurable options
 622  */
 623 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 624
 625 /*
 626  * For booting Linux, the board info and command line data
 627  * have to be in the first 64 MB of memory, since this is
 628  * the maximum mapped by the Linux kernel during initialization.
 629  */
 630 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 631 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 632
 633 #ifdef CONFIG_CMD_KGDB
 634 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 635 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 636 #endif
 637
 638 /*
 639  * Environment Configuration
 640  */
 641 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 642 #define CONFIG_BOOTFILE  "uImage"
 643 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 644
 645 /* default location for tftp and bootm */
 646 #define CONFIG_LOADADDR         1000000
 647 #define __USB_PHY_TYPE          utmi
 648
 649 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 650         "hwconfig=fsl_ddr:"                                     \
 651         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 652         "bank_intlv=auto;"                                      \
 653         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 654         "netdev=eth0\0"                                         \
 655         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 656         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 657         "tftpflash=tftpboot $loadaddr $uboot && "               \
 658         "protect off $ubootaddr +$filesize && "                 \
 659         "erase $ubootaddr +$filesize && "                       \
 660         "cp.b $loadaddr $ubootaddr $filesize && "               \
 661         "protect on $ubootaddr +$filesize && "                  \
 662         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 663         "consoledev=ttyS0\0"                                    \
 664         "ramdiskaddr=2000000\0"                                 \
 665         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 666         "fdtaddr=1e00000\0"                                     \
 667         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 668         "bdev=sda3\0"
 669
 670 /*
 671  * For emulation this causes u-boot to jump to the start of the
 672  * proof point app code automatically
 673  */
 674 #define CONFIG_PROOF_POINTS                             \
 675         "setenv bootargs root=/dev/$bdev rw "           \
 676         "console=$consoledev,$baudrate $othbootargs;"   \
 677         "cpu 1 release 0x29000000 - - -;"               \
 678         "cpu 2 release 0x29000000 - - -;"               \
 679         "cpu 3 release 0x29000000 - - -;"               \
 680         "cpu 4 release 0x29000000 - - -;"               \
 681         "cpu 5 release 0x29000000 - - -;"               \
 682         "cpu 6 release 0x29000000 - - -;"               \
 683         "cpu 7 release 0x29000000 - - -;"               \
 684         "go 0x29000000"
 685
 686 #define CONFIG_HVBOOT                           \
 687         "setenv bootargs config-addr=0x60000000; "      \
 688         "bootm 0x01000000 - 0x00f00000"
 689
 690 #define CONFIG_ALU                              \
 691         "setenv bootargs root=/dev/$bdev rw "           \
 692         "console=$consoledev,$baudrate $othbootargs;"   \
 693         "cpu 1 release 0x01000000 - - -;"               \
 694         "cpu 2 release 0x01000000 - - -;"               \
 695         "cpu 3 release 0x01000000 - - -;"               \
 696         "cpu 4 release 0x01000000 - - -;"               \
 697         "cpu 5 release 0x01000000 - - -;"               \
 698         "cpu 6 release 0x01000000 - - -;"               \
 699         "cpu 7 release 0x01000000 - - -;"               \
 700         "go 0x01000000"
 701
 702 #define CONFIG_LINUX                            \
 703         "setenv bootargs root=/dev/ram rw "             \
 704         "console=$consoledev,$baudrate $othbootargs;"   \
 705         "setenv ramdiskaddr 0x02000000;"                \
 706         "setenv fdtaddr 0x00c00000;"                    \
 707         "setenv loadaddr 0x1000000;"                    \
 708         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 709
 710 #define CONFIG_HDBOOT                                   \
 711         "setenv bootargs root=/dev/$bdev rw "           \
 712         "console=$consoledev,$baudrate $othbootargs;"   \
 713         "tftp $loadaddr $bootfile;"                     \
 714         "tftp $fdtaddr $fdtfile;"                       \
 715         "bootm $loadaddr - $fdtaddr"
 716
 717 #define CONFIG_NFSBOOTCOMMAND                   \
 718         "setenv bootargs root=/dev/nfs rw "     \
 719         "nfsroot=$serverip:$rootpath "          \
 720         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 721         "console=$consoledev,$baudrate $othbootargs;"   \
 722         "tftp $loadaddr $bootfile;"             \
 723         "tftp $fdtaddr $fdtfile;"               \
 724         "bootm $loadaddr - $fdtaddr"
 725
 726 #define CONFIG_RAMBOOTCOMMAND                           \
 727         "setenv bootargs root=/dev/ram rw "             \
 728         "console=$consoledev,$baudrate $othbootargs;"   \
 729         "tftp $ramdiskaddr $ramdiskfile;"               \
 730         "tftp $loadaddr $bootfile;"                     \
 731         "tftp $fdtaddr $fdtfile;"                       \
 732         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 733
 734 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 735
 736 #include <asm/fsl_secure_boot.h>
 737
 738 #endif  /* __T2080RDB_H */