include/configs/T208xRDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * T2080 RDB/PCIe board configuration file
   8  */
   9
  10 #ifndef __T2080RDB_H
  11 #define __T2080RDB_H
  12
  13 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  14 #define CONFIG_FSL_SATA_V2
  15
  16 /* High Level Configuration Options */
  17 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  18 #define CONFIG_ENABLE_36BIT_PHYS
  19
  20 #ifdef CONFIG_PHYS_64BIT
  21 #define CONFIG_ADDR_MAP 1
  22 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  23 #endif
  24
  25 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  26 #define CONFIG_SYS_NUM_CPC      CONFIG_SYS_NUM_DDR_CTLRS
  27 #define CONFIG_ENV_OVERWRITE
  28
  29 #ifdef CONFIG_RAMBOOT_PBL
  30 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
  31
  32 #define CONFIG_SPL_FLUSH_IMAGE
  33 #define CONFIG_SPL_PAD_TO               0x40000
  34 #define CONFIG_SPL_MAX_SIZE             0x28000
  35 #define RESET_VECTOR_OFFSET             0x27FFC
  36 #define BOOT_PAGE_OFFSET                0x27000
  37 #ifdef CONFIG_SPL_BUILD
  38 #define CONFIG_SPL_SKIP_RELOCATE
  39 #define CONFIG_SPL_COMMON_INIT_DDR
  40 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  41 #endif
  42
  43 #ifdef CONFIG_NAND
  44 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  45 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  46 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  47 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  48 #define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  49 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
  50 #endif
  51
  52 #ifdef CONFIG_SPIFLASH
  53 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  54 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  55 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
  56 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
  57 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
  58 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
  59 #ifndef CONFIG_SPL_BUILD
  60 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  61 #endif
  62 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
  63 #endif
  64
  65 #ifdef CONFIG_SDCARD
  66 #define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  67 #define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
  68 #define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
  69 #define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
  70 #define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
  71 #ifndef CONFIG_SPL_BUILD
  72 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  73 #endif
  74 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
  75 #endif
  76
  77 #endif /* CONFIG_RAMBOOT_PBL */
  78
  79 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  80 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  81 /* Set 1M boot space */
  82 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  83 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  84                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  85 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  86 #endif
  87
  88 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  89 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  90 #endif
  91
  92 /*
  93  * These can be toggled for performance analysis, otherwise use default.
  94  */
  95 #define CONFIG_SYS_CACHE_STASHING
  96 #define CONFIG_BTB              /* toggle branch predition */
  97 #define CONFIG_DDR_ECC
  98 #ifdef CONFIG_DDR_ECC
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 100 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 101 #endif
 102
 103 #define CONFIG_SYS_MEMTEST_START        0x00200000 /* memtest works on */
 104 #define CONFIG_SYS_MEMTEST_END          0x00400000
 105
 106 #if defined(CONFIG_SPIFLASH)
 107 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 108 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 109 #define CONFIG_ENV_SECT_SIZE    0x10000
 110 #elif defined(CONFIG_SDCARD)
 111 #define CONFIG_SYS_MMC_ENV_DEV  0
 112 #define CONFIG_ENV_SIZE         0x2000
 113 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 114 #elif defined(CONFIG_NAND)
 115 #define CONFIG_ENV_SIZE         0x2000
 116 #define CONFIG_ENV_OFFSET       (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 117 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 118 #define CONFIG_ENV_ADDR         0xffe20000
 119 #define CONFIG_ENV_SIZE         0x2000
 120 #elif defined(CONFIG_ENV_IS_NOWHERE)
 121 #define CONFIG_ENV_SIZE         0x2000
 122 #else
 123 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 124 #define CONFIG_ENV_SIZE         0x2000
 125 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 126 #endif
 127
 128 #ifndef __ASSEMBLY__
 129 unsigned long get_board_sys_clk(void);
 130 unsigned long get_board_ddr_clk(void);
 131 #endif
 132
 133 #define CONFIG_SYS_CLK_FREQ     66660000
 134 #define CONFIG_DDR_CLK_FREQ     133330000
 135
 136 /*
 137  * Config the L3 Cache as L3 SRAM
 138  */
 139 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 140 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 141 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 142 #ifdef CONFIG_RAMBOOT_PBL
 143 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 144 #endif
 145 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 146 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 147 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 148
 149 #define CONFIG_SYS_DCSRBAR      0xf0000000
 150 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 151
 152 /* EEPROM */
 153 #define CONFIG_ID_EEPROM
 154 #define CONFIG_SYS_I2C_EEPROM_NXID
 155 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 156 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 158
 159 /*
 160  * DDR Setup
 161  */
 162 #define CONFIG_VERY_BIG_RAM
 163 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 164 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 165 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 166 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 167 #define CONFIG_DDR_SPD
 168 #define CONFIG_SYS_SPD_BUS_NUM  0
 169 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 170 #define SPD_EEPROM_ADDRESS1     0x51
 171 #define SPD_EEPROM_ADDRESS2     0x52
 172 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 173 #define CTRL_INTLV_PREFERED     cacheline
 174
 175 /*
 176  * IFC Definitions
 177  */
 178 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 179 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 180 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 181 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 182                                 CSPR_PORT_SIZE_16 | \
 183                                 CSPR_MSEL_NOR | \
 184                                 CSPR_V)
 185 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 186
 187 /* NOR Flash Timing Params */
 188 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 189
 190 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 191                                 FTIM0_NOR_TEADC(0x5) | \
 192                                 FTIM0_NOR_TEAHC(0x5))
 193 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 194                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 195                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 196 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 197                                 FTIM2_NOR_TCH(0x4) | \
 198                                 FTIM2_NOR_TWPH(0x0E) | \
 199                                 FTIM2_NOR_TWP(0x1c))
 200 #define CONFIG_SYS_NOR_FTIM3    0x0
 201
 202 #define CONFIG_SYS_FLASH_QUIET_TEST
 203 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 204
 205 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 206 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 207 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 208 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 209 #define CONFIG_SYS_FLASH_EMPTY_INFO
 210 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS }
 211
 212 /* CPLD on IFC */
 213 #define CONFIG_SYS_CPLD_BASE    0xffdf0000
 214 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
 215 #define CONFIG_SYS_CSPR2_EXT    (0xf)
 216 #define CONFIG_SYS_CSPR2        (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
 217                                 | CSPR_PORT_SIZE_8 \
 218                                 | CSPR_MSEL_GPCM \
 219                                 | CSPR_V)
 220 #define CONFIG_SYS_AMASK2       IFC_AMASK(64*1024)
 221 #define CONFIG_SYS_CSOR2        0x0
 222
 223 /* CPLD Timing parameters for IFC CS2 */
 224 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 225                                         FTIM0_GPCM_TEADC(0x0e) | \
 226                                         FTIM0_GPCM_TEAHC(0x0e))
 227 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 228                                         FTIM1_GPCM_TRAD(0x1f))
 229 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 230                                         FTIM2_GPCM_TCH(0x8) | \
 231                                         FTIM2_GPCM_TWP(0x1f))
 232 #define CONFIG_SYS_CS2_FTIM3            0x0
 233
 234 /* NAND Flash on IFC */
 235 #define CONFIG_NAND_FSL_IFC
 236 #define CONFIG_SYS_NAND_BASE            0xff800000
 237 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 238
 239 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 240 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 241                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 242                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 243                                 | CSPR_V)
 244 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 245
 246 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 247                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 248                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 249                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 250                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 251                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 252                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 253
 254 #define CONFIG_SYS_NAND_ONFI_DETECTION
 255
 256 /* ONFI NAND Flash mode0 Timing Params */
 257 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 258                                         FTIM0_NAND_TWP(0x18)    | \
 259                                         FTIM0_NAND_TWCHT(0x07)  | \
 260                                         FTIM0_NAND_TWH(0x0a))
 261 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 262                                         FTIM1_NAND_TWBE(0x39)   | \
 263                                         FTIM1_NAND_TRR(0x0e)    | \
 264                                         FTIM1_NAND_TRP(0x18))
 265 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 266                                         FTIM2_NAND_TREH(0x0a)   | \
 267                                         FTIM2_NAND_TWHRE(0x1e))
 268 #define CONFIG_SYS_NAND_FTIM3           0x0
 269
 270 #define CONFIG_SYS_NAND_DDR_LAW         11
 271 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 272 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 273 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 274
 275 #if defined(CONFIG_NAND)
 276 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 277 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 278 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 279 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 280 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 281 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 282 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 283 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 284 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 285 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 286 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 287 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 288 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 289 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 290 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 291 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 292 #else
 293 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 294 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 295 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 296 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 297 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 298 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 299 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 300 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 301 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
 302 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 303 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 304 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 305 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 306 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 307 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 308 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 309 #endif
 310
 311 #if defined(CONFIG_RAMBOOT_PBL)
 312 #define CONFIG_SYS_RAMBOOT
 313 #endif
 314
 315 #ifdef CONFIG_SPL_BUILD
 316 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
 317 #else
 318 #define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
 319 #endif
 320
 321 #define CONFIG_HWCONFIG
 322
 323 /* define to use L1 as initial stack */
 324 #define CONFIG_L1_INIT_RAM
 325 #define CONFIG_SYS_INIT_RAM_LOCK
 326 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 327 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 328 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 329 /* The assembler doesn't like typecast */
 330 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 331                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 332                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 333 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 334 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 335                                                 GENERATED_GBL_DATA_SIZE)
 336 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 337 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 338 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 339
 340 /*
 341  * Serial Port
 342  */
 343 #define CONFIG_SYS_NS16550_SERIAL
 344 #define CONFIG_SYS_NS16550_REG_SIZE     1
 345 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 346 #define CONFIG_SYS_BAUDRATE_TABLE       \
 347         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 348 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 349 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 350 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 351 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 352
 353 /*
 354  * I2C
 355  */
 356 #define CONFIG_SYS_I2C
 357 #define CONFIG_SYS_I2C_FSL
 358 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 359 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 360 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 361 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 362 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 363 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 364 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 365 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 366 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 367 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 368 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 369 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 370 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 371 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 372 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 373 #define I2C_MUX_CH_DEFAULT      0x8
 374
 375 #define I2C_MUX_CH_VOL_MONITOR  0xa
 376
 377 #define CONFIG_VID_FLS_ENV              "t208xrdb_vdd_mv"
 378 #ifndef CONFIG_SPL_BUILD
 379 #define CONFIG_VID
 380 #endif
 381 #define CONFIG_VOL_MONITOR_IR36021_SET
 382 #define CONFIG_VOL_MONITOR_IR36021_READ
 383 /* The lowest and highest voltage allowed for T208xRDB */
 384 #define VDD_MV_MIN                      819
 385 #define VDD_MV_MAX                      1212
 386
 387 /*
 388  * RapidIO
 389  */
 390 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 391 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 392 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 393 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 394 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 395 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 396 /*
 397  * for slave u-boot IMAGE instored in master memory space,
 398  * PHYS must be aligned based on the SIZE
 399  */
 400 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 401 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 402 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 403 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 404 /*
 405  * for slave UCODE and ENV instored in master memory space,
 406  * PHYS must be aligned based on the SIZE
 407  */
 408 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 409 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 410 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 411
 412 /* slave core release by master*/
 413 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 414 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 415
 416 /*
 417  * SRIO_PCIE_BOOT - SLAVE
 418  */
 419 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 420 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 421 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 422                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 423 #endif
 424
 425 /*
 426  * eSPI - Enhanced SPI
 427  */
 428
 429 /*
 430  * General PCI
 431  * Memory space is mapped 1-1, but I/O space must start from 0.
 432  */
 433 #define CONFIG_PCIE1            /* PCIE controller 1 */
 434 #define CONFIG_PCIE2            /* PCIE controller 2 */
 435 #define CONFIG_PCIE3            /* PCIE controller 3 */
 436 #define CONFIG_PCIE4            /* PCIE controller 4 */
 437 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 438 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 439 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 440 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 441 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 442 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 443 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 444 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 445 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 446 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 447 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 448
 449 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 450 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 451 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 452 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 453 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 454 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 455 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 456 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 457 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 458
 459 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 460 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 461 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 462 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 463 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 464 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 465 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 466 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 467 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 468
 469 /* controller 4, Base address 203000 */
 470 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 471 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 472 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 473 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 474 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 475 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 476 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 477
 478 #ifdef CONFIG_PCI
 479 #define CONFIG_PCI_INDIRECT_BRIDGE
 480 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
 481 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 482 #endif
 483
 484 /* Qman/Bman */
 485 #ifndef CONFIG_NOBQFMAN
 486 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 487 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 488 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 489 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 490 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 491 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 492 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 493 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 494 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 495                                         CONFIG_SYS_BMAN_CENA_SIZE)
 496 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 497 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 498 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 499 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 500 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 501 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 502 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 503 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 504 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 505 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 506 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 507                                         CONFIG_SYS_QMAN_CENA_SIZE)
 508 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 509 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 510
 511 #define CONFIG_SYS_DPAA_FMAN
 512 #define CONFIG_SYS_DPAA_PME
 513 #define CONFIG_SYS_PMAN
 514 #define CONFIG_SYS_DPAA_DCE
 515 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 516 #define CONFIG_SYS_INTERLAKEN
 517
 518 /* Default address of microcode for the Linux Fman driver */
 519 #if defined(CONFIG_SPIFLASH)
 520 /*
 521  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 522  * env, so we got 0x110000.
 523  */
 524 #define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
 525 #define CONFIG_SYS_FMAN_FW_ADDR         0x110000
 526 #define CONFIG_CORTINA_FW_ADDR          0x120000
 527
 528 #elif defined(CONFIG_SDCARD)
 529 /*
 530  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 531  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 532  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 533  */
 534 #define CONFIG_SYS_CORTINA_FW_IN_MMC
 535 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
 536 #define CONFIG_CORTINA_FW_ADDR          (512 * 0x8a0)
 537
 538 #elif defined(CONFIG_NAND)
 539 #define CONFIG_SYS_CORTINA_FW_IN_NAND
 540 #define CONFIG_SYS_FMAN_FW_ADDR         (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
 541 #define CONFIG_CORTINA_FW_ADDR          (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 542 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 543 /*
 544  * Slave has no ucode locally, it can fetch this from remote. When implementing
 545  * in two corenet boards, slave's ucode could be stored in master's memory
 546  * space, the address can be mapped from slave TLB->slave LAW->
 547  * slave SRIO or PCIE outbound window->master inbound window->
 548  * master LAW->the ucode address in master's memory space.
 549  */
 550 #define CONFIG_SYS_CORTINA_FW_IN_REMOTE
 551 #define CONFIG_SYS_FMAN_FW_ADDR         0xFFE00000
 552 #define CONFIG_CORTINA_FW_ADDR          0xFFE10000
 553 #else
 554 #define CONFIG_SYS_CORTINA_FW_IN_NOR
 555 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 556 #define CONFIG_CORTINA_FW_ADDR          0xEFE00000
 557 #endif
 558 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 559 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 560 #endif /* CONFIG_NOBQFMAN */
 561
 562 #ifdef CONFIG_SYS_DPAA_FMAN
 563 #define CONFIG_PHY_CORTINA
 564 #define CONFIG_PHY_REALTEK
 565 #define CONFIG_CORTINA_FW_LENGTH        0x40000
 566 #define RGMII_PHY1_ADDR         0x01  /* RealTek RTL8211E */
 567 #define RGMII_PHY2_ADDR         0x02
 568 #define CORTINA_PHY_ADDR1       0x0c  /* Cortina CS4315 */
 569 #define CORTINA_PHY_ADDR2       0x0d
 570 #define FM1_10GEC3_PHY_ADDR     0x00  /* Aquantia AQ1202 10G Base-T */
 571 #define FM1_10GEC4_PHY_ADDR     0x01
 572 #endif
 573
 574 #ifdef CONFIG_FMAN_ENET
 575 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 576 #endif
 577
 578 /*
 579  * SATA
 580  */
 581 #ifdef CONFIG_FSL_SATA_V2
 582 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 583 #define CONFIG_SATA1
 584 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 585 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 586 #define CONFIG_SATA2
 587 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 588 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 589 #define CONFIG_LBA48
 590 #endif
 591
 592 /*
 593  * USB
 594  */
 595 #ifdef CONFIG_USB_EHCI_HCD
 596 #define CONFIG_USB_EHCI_FSL
 597 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 598 #define CONFIG_HAS_FSL_DR_USB
 599 #endif
 600
 601 /*
 602  * SDHC
 603  */
 604 #ifdef CONFIG_MMC
 605 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 606 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 607 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 608 #endif
 609
 610 /*
 611  * Dynamic MTD Partition support with mtdparts
 612  */
 613
 614 /*
 615  * Environment
 616  */
 617
 618 /*
 619  * Miscellaneous configurable options
 620  */
 621 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 622
 623 /*
 624  * For booting Linux, the board info and command line data
 625  * have to be in the first 64 MB of memory, since this is
 626  * the maximum mapped by the Linux kernel during initialization.
 627  */
 628 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 629 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 630
 631 #ifdef CONFIG_CMD_KGDB
 632 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 633 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 634 #endif
 635
 636 /*
 637  * Environment Configuration
 638  */
 639 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 640 #define CONFIG_BOOTFILE  "uImage"
 641 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 642
 643 /* default location for tftp and bootm */
 644 #define CONFIG_LOADADDR         1000000
 645 #define __USB_PHY_TYPE          utmi
 646
 647 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 648         "hwconfig=fsl_ddr:"                                     \
 649         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 650         "bank_intlv=auto;"                                      \
 651         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 652         "netdev=eth0\0"                                         \
 653         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 654         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 655         "tftpflash=tftpboot $loadaddr $uboot && "               \
 656         "protect off $ubootaddr +$filesize && "                 \
 657         "erase $ubootaddr +$filesize && "                       \
 658         "cp.b $loadaddr $ubootaddr $filesize && "               \
 659         "protect on $ubootaddr +$filesize && "                  \
 660         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 661         "consoledev=ttyS0\0"                                    \
 662         "ramdiskaddr=2000000\0"                                 \
 663         "ramdiskfile=t2080rdb/ramdisk.uboot\0"                  \
 664         "fdtaddr=1e00000\0"                                     \
 665         "fdtfile=t2080rdb/t2080rdb.dtb\0"                       \
 666         "bdev=sda3\0"
 667
 668 /*
 669  * For emulation this causes u-boot to jump to the start of the
 670  * proof point app code automatically
 671  */
 672 #define CONFIG_PROOF_POINTS                             \
 673         "setenv bootargs root=/dev/$bdev rw "           \
 674         "console=$consoledev,$baudrate $othbootargs;"   \
 675         "cpu 1 release 0x29000000 - - -;"               \
 676         "cpu 2 release 0x29000000 - - -;"               \
 677         "cpu 3 release 0x29000000 - - -;"               \
 678         "cpu 4 release 0x29000000 - - -;"               \
 679         "cpu 5 release 0x29000000 - - -;"               \
 680         "cpu 6 release 0x29000000 - - -;"               \
 681         "cpu 7 release 0x29000000 - - -;"               \
 682         "go 0x29000000"
 683
 684 #define CONFIG_HVBOOT                           \
 685         "setenv bootargs config-addr=0x60000000; "      \
 686         "bootm 0x01000000 - 0x00f00000"
 687
 688 #define CONFIG_ALU                              \
 689         "setenv bootargs root=/dev/$bdev rw "           \
 690         "console=$consoledev,$baudrate $othbootargs;"   \
 691         "cpu 1 release 0x01000000 - - -;"               \
 692         "cpu 2 release 0x01000000 - - -;"               \
 693         "cpu 3 release 0x01000000 - - -;"               \
 694         "cpu 4 release 0x01000000 - - -;"               \
 695         "cpu 5 release 0x01000000 - - -;"               \
 696         "cpu 6 release 0x01000000 - - -;"               \
 697         "cpu 7 release 0x01000000 - - -;"               \
 698         "go 0x01000000"
 699
 700 #define CONFIG_LINUX                            \
 701         "setenv bootargs root=/dev/ram rw "             \
 702         "console=$consoledev,$baudrate $othbootargs;"   \
 703         "setenv ramdiskaddr 0x02000000;"                \
 704         "setenv fdtaddr 0x00c00000;"                    \
 705         "setenv loadaddr 0x1000000;"                    \
 706         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 707
 708 #define CONFIG_HDBOOT                                   \
 709         "setenv bootargs root=/dev/$bdev rw "           \
 710         "console=$consoledev,$baudrate $othbootargs;"   \
 711         "tftp $loadaddr $bootfile;"                     \
 712         "tftp $fdtaddr $fdtfile;"                       \
 713         "bootm $loadaddr - $fdtaddr"
 714
 715 #define CONFIG_NFSBOOTCOMMAND                   \
 716         "setenv bootargs root=/dev/nfs rw "     \
 717         "nfsroot=$serverip:$rootpath "          \
 718         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 719         "console=$consoledev,$baudrate $othbootargs;"   \
 720         "tftp $loadaddr $bootfile;"             \
 721         "tftp $fdtaddr $fdtfile;"               \
 722         "bootm $loadaddr - $fdtaddr"
 723
 724 #define CONFIG_RAMBOOTCOMMAND                           \
 725         "setenv bootargs root=/dev/ram rw "             \
 726         "console=$consoledev,$baudrate $othbootargs;"   \
 727         "tftp $ramdiskaddr $ramdiskfile;"               \
 728         "tftp $loadaddr $bootfile;"                     \
 729         "tftp $fdtaddr $fdtfile;"                       \
 730         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 731
 732 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 733
 734 #include <asm/fsl_secure_boot.h>
 735
 736 #endif  /* __T2080RDB_H */