Add Broadcom / Netgear changes from RAXE 1.0.0.48
[project/bcm63xx/u-boot.git] / include / configs / bcm963158.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
4 *
5 * Copyright 2019 Broadcom Ltd.
6 */
7
8 #include <linux/sizes.h>
9
10 /*
11 * common
12 */
13
14 /* UART */
15 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
16 230400, 500000, 1500000 }
17 /* Memory usage */
18 #define CONFIG_SYS_MAXARGS 24
19 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 32)
20 #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024)
21
22 #define CPU_RELEASE_ADDR 0x1000
23 #define CONFIG_GICV2 1
24 #define GICD_BASE 0x81001000
25 #define GICC_BASE 0x81002000
26
27 #define CONFIG_ENV_CALLBACK_LIST_STATIC "boardid:boardid,voiceboardid:voiceboardid,"
28
29 /*
30 * 63158
31 */
32
33 #define CONFIG_SYS_INIT_STD_32K_ADDR 0xfff80000
34 #define CONFIG_SYS_SEC_CRED_ADDR (CONFIG_SYS_INIT_STD_32K_ADDR + 0x7000)
35 /* RAM */
36 #define PHYS_SDRAM_1 0x00000000UL
37 #define PHYS_SDRAM_2 0x100000000UL
38 #define PHYS_SDRAM_1_SIZE (2UL * SZ_1G) /* Maximum possible bnk 0 size */
39 #define PHYS_SDRAM_2_SIZE (2UL * SZ_1G) /* Maximum possible bnk 1 size */
40 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
41
42 /* U-Boot */
43 #ifdef CONFIG_TPL_BUILD
44 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
45 #define CONFIG_SYS_PAGETBL_BASE CONFIG_SYS_INIT_SP_ADDR
46 #define CONFIG_SYS_PAGETBL_SIZE 0x10000
47 #elif CONFIG_SPL_BUILD
48 #define CONFIG_SYS_INIT_RAM_ADDR 0x80800000
49 #define CONFIG_SYS_INIT_RAM_SIZE 0x000a0000
50 #define CONFIG_SYS_INIT_SP_OFFSET \
51 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
52 #define CONFIG_SYS_INIT_SP_ADDR \
53 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
54
55 #define CONFIG_SYS_PAGETBL_BASE 0x808a0000
56 #define CONFIG_SYS_PAGETBL_SIZE 0x10000
57
58 #define CONFIG_SPL_MAX_SIZE 0x00020000
59 #define CONFIG_SPL_BSS_START_ADDR 0x80840000
60 #define CONFIG_SPL_BSS_MAX_SIZE 0x8000
61
62 #define CONFIG_SYS_MALLOC_SIMPLE
63 #else
64 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M)
65 #endif
66
67 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_TEXT_BASE)
68
69 #define CONFIG_SKIP_LOWLEVEL_INIT
70
71 #define CONFIG_SPL_LOAD_FIT_ADDRESS (CONFIG_TPL_TEXT_BASE + 0x2000000)
72
73 #ifdef CONFIG_NAND
74 #define CONFIG_SYS_NAND_BASE 0xff801800
75 #define CONFIG_SYS_MAX_NAND_DEVICE 1
76 #define CONFIG_SYS_NAND_SELF_INIT
77 #define CONFIG_SYS_NAND_ONFI_DETECTION
78
79 /* dummy definition to make spl nand image loader happy */
80 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000
81 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
82 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
83 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
84 #define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) // max possible size
85
86
87 #define CONFIG_TPL_UBI
88 #define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
89 #define CONFIG_SPL_UBI_MAX_PEB_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
90 #define CONFIG_SPL_UBI_IMG_OFFSET 0x100000
91 #define CONFIG_SPL_UBI_MAX_PEBS 4096
92 #define CONFIG_SPL_UBI_VOL_IDS 8
93 #define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
94 #define CONFIG_SPL_UBI_PEB_OFFSET 4
95 #define CONFIG_SPL_UBI_VID_OFFSET 4096
96 #define CONFIG_SPL_UBI_LEB_START 8192
97 #define CONFIG_SPL_UBI_INFO_ADDR (CONFIG_SPL_LOAD_FIT_ADDRESS - 0x1000000)
98 #endif /* CONFIG_NAND */
99
100 #ifdef CONFIG_MMC
101 #ifdef CONFIG_TPL_BUILD
102 #elif CONFIG_SPL_BUILD
103 #endif
104 #endif /* CONFIG_MMC */
105
106 #ifdef CONFIG_USB_OHCI_HCD
107 #define CONFIG_USB_OHCI_NEW
108 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
109 #endif /* CONFIG_USB_OHCI_HCD */
110
111 #define CONFIG_SYS_MTDPARTS_RUNTIME
112
113 /*
114 * bcm963158
115 */
116
117 #define CONFIG_ARCH_CPU_INIT
118 #define COUNTER_FREQUENCY 50000000
119 #define CONFIG_ENV_SIZE (8 * 1024)
120
121 #define CONFIG_SYS_BOOTMAPSZ (128 << 20)
122 #define CONFIG_SYS_FDT_PAD 0x80000