1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
10 #define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
11 #define MAX_PLUGIN_CODE_SIZE (64 * 1024)
12 #define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
13 #define APP_CODE_BARKER 0xB1
14 #define DCD_BARKER 0xB17219E9
16 /* Specify the offset of the IVT in the IMX header as expected by BootROM */
17 #define BOOTROM_IVT_HDR_OFFSET 0xC00
20 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
21 * mach-imx/imximage.cfg because tools/imximage.c can not
22 * cross-include headers from arch/arm/ and vice-versa.
24 #define CMD_DATA_STR "DATA"
26 /* Initial Vector Table Offset */
27 #define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
28 #define FLASH_OFFSET_STANDARD 0x400
29 #define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
30 #define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
31 #define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
32 #define FLASH_OFFSET_ONENAND 0x100
33 #define FLASH_OFFSET_NOR 0x1000
34 #define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
35 #define FLASH_OFFSET_QSPI 0x1000
36 #define FLASH_OFFSET_FLEXSPI 0x1000
38 /* Initial Load Region Size */
39 #define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
40 #define FLASH_LOADSIZE_STANDARD 0x1000
41 #define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
42 #define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
43 #define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
44 #define FLASH_LOADSIZE_ONENAND 0x400
45 #define FLASH_LOADSIZE_NOR 0x0 /* entire image */
46 #define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
47 #define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
49 /* Command tags and parameters */
50 #define IVT_HEADER_TAG 0xD1
51 #define IVT_VERSION 0x40
52 #define IVT_VERSION_V3 0x41
53 #define DCD_HEADER_TAG 0xD2
54 #define DCD_VERSION 0x40
55 #define DCD_WRITE_DATA_COMMAND_TAG 0xCC
56 #define DCD_WRITE_DATA_PARAM 0x4
57 #define DCD_WRITE_CLR_BIT_PARAM 0xC
58 #define DCD_WRITE_SET_BIT_PARAM 0x1C
59 #define DCD_CHECK_DATA_COMMAND_TAG 0xCF
60 #define DCD_CHECK_BITS_SET_PARAM 0x14
61 #define DCD_CHECK_BITS_CLR_PARAM 0x04
76 /* Follwoing on i.MX8MQ/MM */
84 enum imximage_fld_types
{
92 enum imximage_version
{
93 IMXIMAGE_VER_INVALID
= -1,
100 uint32_t type
; /* Type of pointer (byte, halfword, word, wait/read) */
101 uint32_t addr
; /* Address to write to */
102 uint32_t value
; /* Data to write */
103 } dcd_type_addr_data_t
;
106 uint32_t barker
; /* Barker for sanity check */
107 uint32_t length
; /* Device configuration length (without preamble) */
111 dcd_preamble_t preamble
;
112 dcd_type_addr_data_t addr_data
[MAX_HW_CFG_SIZE_V1
];
116 uint32_t app_code_jump_vector
;
117 uint32_t app_code_barker
;
118 uint32_t app_code_csf
;
119 uint32_t dcd_ptr_ptr
;
120 uint32_t super_root_key
;
122 uint32_t app_dest_ptr
;
126 uint32_t length
; /* Length of data to be read from flash */
130 flash_header_v1_t fhdr
;
132 flash_cfg_parms_t ext_header
;
144 } __attribute__((packed
)) ivt_header_t
;
150 } __attribute__((packed
)) write_dcd_command_t
;
153 write_dcd_command_t write_dcd_command
;
154 dcd_addr_data_t addr_data
[MAX_HW_CFG_SIZE_V2
];
159 struct dcd_v2_cmd dcd_cmd
;
160 uint32_t padding
[1]; /* end up on an 8-byte boundary */
174 uint32_t boot_data_ptr
;
181 flash_header_v2_t fhdr
;
182 boot_data_t boot_data
;
185 char plugin_code
[MAX_PLUGIN_CODE_SIZE
];
190 flash_header_v2_t fhdr
;
191 boot_data_t boot_data
;
195 /* The header must be aligned to 4k on MX53 for NAND boot */
198 imx_header_v1_t hdr_v1
;
199 imx_header_v2_t hdr_v2
;
203 typedef void (*set_dcd_val_t
)(struct imx_header
*imxhdr
,
204 char *name
, int lineno
,
205 int fld
, uint32_t value
,
208 typedef void (*set_dcd_param_t
)(struct imx_header
*imxhdr
, uint32_t dcd_len
,
211 typedef void (*set_dcd_rst_t
)(struct imx_header
*imxhdr
,
213 char *name
, int lineno
);
215 typedef void (*set_imx_hdr_t
)(struct imx_header
*imxhdr
, uint32_t dcd_len
,
216 uint32_t entry_point
, uint32_t flash_offset
);
218 #endif /* __ASSEMBLY__ */
219 #endif /* _IMXIMAGE_H_ */