include/lib/cpus/aarch64/neoverse_n1.h

   1 /*
   2  * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef NEOVERSE_N1_H
   8 #define NEOVERSE_N1_H
   9
  10 #include <lib/utils_def.h>
  11
  12 /* Neoverse N1 MIDR for revision 0 */
  13 #define NEOVERSE_N1_MIDR                U(0x410fd0c0)
  14
  15 /* Exception Syndrome register EC code for IC Trap */
  16 #define NEOVERSE_N1_EC_IC_TRAP          U(0x1f)
  17
  18 /*******************************************************************************
  19  * CPU Power Control register specific definitions.
  20  ******************************************************************************/
  21 #define NEOVERSE_N1_CPUPWRCTLR_EL1      S3_0_C15_C2_7
  22
  23 /* Definitions of register field mask in NEOVERSE_N1_CPUPWRCTLR_EL1 */
  24 #define NEOVERSE_N1_CORE_PWRDN_EN_MASK  U(0x1)
  25
  26 #define NEOVERSE_N1_ACTLR_AMEN_BIT      (U(1) << 4)
  27
  28 #define NEOVERSE_N1_AMU_NR_COUNTERS     U(5)
  29 #define NEOVERSE_N1_AMU_GROUP0_MASK     U(0x1f)
  30
  31 /*******************************************************************************
  32  * CPU Extended Control register specific definitions.
  33  ******************************************************************************/
  34 #define NEOVERSE_N1_CPUECTLR_EL1        S3_0_C15_C1_4
  35
  36 #define NEOVERSE_N1_WS_THR_L2_MASK      (ULL(3) << 24)
  37 #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT       (ULL(1) << 51)
  38
  39 /*******************************************************************************
  40  * CPU Auxiliary Control register specific definitions.
  41  ******************************************************************************/
  42 #define NEOVERSE_N1_CPUACTLR_EL1        S3_0_C15_C1_0
  43
  44 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6  (ULL(1) << 6)
  45 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)
  46
  47 #define NEOVERSE_N1_CPUACTLR2_EL1       S3_0_C15_C1_1
  48
  49 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0         (ULL(1) << 0)
  50 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2         (ULL(1) << 2)
  51 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11        (ULL(1) << 11)
  52 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15        (ULL(1) << 15)
  53 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16        (ULL(1) << 16)
  54 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59        (ULL(1) << 59)
  55
  56 #define NEOVERSE_N1_CPUACTLR3_EL1       S3_0_C15_C1_2
  57
  58 #define NEOVERSE_N1_CPUACTLR3_EL1_BIT_10        (ULL(1) << 10)
  59
  60 /* Instruction patching registers */
  61 #define CPUPSELR_EL3    S3_6_C15_C8_0
  62 #define CPUPCR_EL3      S3_6_C15_C8_1
  63 #define CPUPOR_EL3      S3_6_C15_C8_2
  64 #define CPUPMR_EL3      S3_6_C15_C8_3
  65
  66 #endif /* NEOVERSE_N1_H */