include/lib/xlat_tables/xlat_mmu_helpers.h

   1 /*
   2  * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef __XLAT_MMU_HELPERS_H__
   8 #define __XLAT_MMU_HELPERS_H__
   9
  10 /*
  11  * The following flags are passed to enable_mmu_xxx() to override the default
  12  * values used to program system registers while enabling the MMU.
  13  */
  14
  15 /*
  16  * When this flag is used, all data access to Normal memory from this EL and all
  17  * Normal memory accesses to the translation tables of this EL are non-cacheable
  18  * for all levels of data and unified cache until the caches are enabled by
  19  * setting the bit SCTLR_ELx.C.
  20  */
  21 #define DISABLE_DCACHE                  (U(1) << 0)
  22
  23 /*
  24  * Mark the translation tables as non-cacheable for the MMU table walker, which
  25  * is a different observer from the PE/CPU. If the flag is not specified, the
  26  * tables are cacheable for the MMU table walker.
  27  *
  28  * Note that, as far as the PE/CPU observer is concerned, the attributes used
  29  * are the ones specified in the translation tables themselves. The MAIR
  30  * register specifies the cacheability through the field AttrIndx of the lower
  31  * attributes of the translation tables. The shareability is specified in the SH
  32  * field of the lower attributes.
  33  *
  34  * The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn
  35  * and SHn of the TCR register to access the translation tables.
  36  *
  37  * The attributes specified in the TCR register and the tables can be different
  38  * as there are no checks to prevent that. Special care must be taken to ensure
  39  * that there aren't mismatches. The behaviour in that case is described in the
  40  * sections 'Mismatched memory attributes' in the ARMv8 ARM.
  41  */
  42 #define XLAT_TABLE_NC                   (U(1) << 1)
  43
  44 #ifndef __ASSEMBLY__
  45
  46 #ifdef AARCH32
  47 /* AArch32 specific translation table API */
  48 void enable_mmu_secure(unsigned int flags);
  49 #else
  50 /* AArch64 specific translation table APIs */
  51 void enable_mmu_el1(unsigned int flags);
  52 void enable_mmu_el3(unsigned int flags);
  53 #endif /* AARCH32 */
  54
  55 #endif /* __ASSEMBLY__ */
  56
  57 #endif /* __XLAT_MMU_HELPERS_H__ */