include/lib/xlat_tables/xlat_tables_defs.h

   1 /*
   2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef XLAT_TABLES_DEFS_H
   8 #define XLAT_TABLES_DEFS_H
   9
  10 #include <arch.h>
  11 #include <utils_def.h>
  12 #include <xlat_mmu_helpers.h>
  13
  14 /* Miscellaneous MMU related constants */
  15 #define NUM_2MB_IN_GB           (U(1) << 9)
  16 #define NUM_4K_IN_2MB           (U(1) << 9)
  17 #define NUM_GB_IN_4GB           (U(1) << 2)
  18
  19 #define TWO_MB_SHIFT            U(21)
  20 #define ONE_GB_SHIFT            U(30)
  21 #define FOUR_KB_SHIFT           U(12)
  22
  23 #define ONE_GB_INDEX(x)         ((x) >> ONE_GB_SHIFT)
  24 #define TWO_MB_INDEX(x)         ((x) >> TWO_MB_SHIFT)
  25 #define FOUR_KB_INDEX(x)        ((x) >> FOUR_KB_SHIFT)
  26
  27 #define PAGE_SIZE_4KB           U(4096)
  28 #define PAGE_SIZE_16KB          U(16384)
  29 #define PAGE_SIZE_64KB          U(65536)
  30
  31 #define INVALID_DESC            U(0x0)
  32 /*
  33  * A block descriptor points to a region of memory bigger than the granule size
  34  * (e.g. a 2MB region when the granule size is 4KB).
  35  */
  36 #define BLOCK_DESC              U(0x1) /* Table levels 0-2 */
  37 /* A table descriptor points to the next level of translation table. */
  38 #define TABLE_DESC              U(0x3) /* Table levels 0-2 */
  39 /*
  40  * A page descriptor points to a page, i.e. a memory region whose size is the
  41  * translation granule size (e.g. 4KB).
  42  */
  43 #define PAGE_DESC               U(0x3) /* Table level 3 */
  44
  45 #define DESC_MASK               U(0x3)
  46
  47 #define FIRST_LEVEL_DESC_N      ONE_GB_SHIFT
  48 #define SECOND_LEVEL_DESC_N     TWO_MB_SHIFT
  49 #define THIRD_LEVEL_DESC_N      FOUR_KB_SHIFT
  50
  51 /* XN: Translation regimes that support one VA range (EL2 and EL3). */
  52 #define XN                      (ULL(1) << 2)
  53 /* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */
  54 #define UXN                     (ULL(1) << 2)
  55 #define PXN                     (ULL(1) << 1)
  56 #define CONT_HINT               (ULL(1) << 0)
  57 #define UPPER_ATTRS(x)          (((x) & ULL(0x7)) << 52)
  58
  59 #define NON_GLOBAL              (U(1) << 9)
  60 #define ACCESS_FLAG             (U(1) << 8)
  61 #define NSH                     (U(0x0) << 6)
  62 #define OSH                     (U(0x2) << 6)
  63 #define ISH                     (U(0x3) << 6)
  64
  65 #define TABLE_ADDR_MASK         ULL(0x0000FFFFFFFFF000)
  66
  67 /*
  68  * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or
  69  * 64KB. However, only 4KB are supported at the moment.
  70  */
  71 #define PAGE_SIZE_SHIFT         FOUR_KB_SHIFT
  72 #define PAGE_SIZE               (U(1) << PAGE_SIZE_SHIFT)
  73 #define PAGE_SIZE_MASK          (PAGE_SIZE - U(1))
  74 #define IS_PAGE_ALIGNED(addr)   (((addr) & PAGE_SIZE_MASK) == U(0))
  75
  76 #define XLAT_ENTRY_SIZE_SHIFT   U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
  77 #define XLAT_ENTRY_SIZE         (U(1) << XLAT_ENTRY_SIZE_SHIFT)
  78
  79 #define XLAT_TABLE_SIZE_SHIFT   PAGE_SIZE_SHIFT /* Size of one complete table */
  80 #define XLAT_TABLE_SIZE         (U(1) << XLAT_TABLE_SIZE_SHIFT)
  81
  82 #define XLAT_TABLE_LEVEL_MAX    U(3)
  83
  84 /* Values for number of entries in each MMU translation table */
  85 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
  86 #define XLAT_TABLE_ENTRIES      (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
  87 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - U(1))
  88
  89 /* Values to convert a memory address to an index into a translation table */
  90 #define L3_XLAT_ADDRESS_SHIFT   PAGE_SIZE_SHIFT
  91 #define L2_XLAT_ADDRESS_SHIFT   (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
  92 #define L1_XLAT_ADDRESS_SHIFT   (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
  93 #define L0_XLAT_ADDRESS_SHIFT   (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
  94 #define XLAT_ADDR_SHIFT(level)  (PAGE_SIZE_SHIFT + \
  95                   ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
  96
  97 #define XLAT_BLOCK_SIZE(level)  (UL(1) << XLAT_ADDR_SHIFT(level))
  98 /* Mask to get the bits used to index inside a block of a certain level */
  99 #define XLAT_BLOCK_MASK(level)  (XLAT_BLOCK_SIZE(level) - UL(1))
 100 /* Mask to get the address bits common to a block of a certain table level*/
 101 #define XLAT_ADDR_MASK(level)   (~XLAT_BLOCK_MASK(level))
 102 /*
 103  * Extract from the given virtual address the index into the given lookup level.
 104  * This macro assumes the system is using the 4KB translation granule.
 105  */
 106 #define XLAT_TABLE_IDX(virtual_addr, level)     \
 107         (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
 108
 109 /*
 110  * The ARMv8 translation table descriptor format defines AP[2:1] as the Access
 111  * Permissions bits, and does not define an AP[0] bit.
 112  *
 113  * AP[1] is valid only for a stage 1 translation that supports two VA ranges
 114  * (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime). It is RES1
 115  * when stage 1 translations can only support one VA range.
 116  */
 117 #define AP2_SHIFT                       U(0x7)
 118 #define AP2_RO                          ULL(0x1)
 119 #define AP2_RW                          ULL(0x0)
 120
 121 #define AP1_SHIFT                       U(0x6)
 122 #define AP1_ACCESS_UNPRIVILEGED         ULL(0x1)
 123 #define AP1_NO_ACCESS_UNPRIVILEGED      ULL(0x0)
 124 #define AP1_RES1                        ULL(0x1)
 125
 126 /*
 127  * The following definitions must all be passed to the LOWER_ATTRS() macro to
 128  * get the right bitmask.
 129  */
 130 #define AP_RO                           (AP2_RO << 5)
 131 #define AP_RW                           (AP2_RW << 5)
 132 #define AP_ACCESS_UNPRIVILEGED          (AP1_ACCESS_UNPRIVILEGED    << 4)
 133 #define AP_NO_ACCESS_UNPRIVILEGED       (AP1_NO_ACCESS_UNPRIVILEGED << 4)
 134 #define AP_ONE_VA_RANGE_RES1            (AP1_RES1 << 4)
 135 #define NS                              (U(0x1) << 3)
 136 #define ATTR_NON_CACHEABLE_INDEX        ULL(0x2)
 137 #define ATTR_DEVICE_INDEX               ULL(0x1)
 138 #define ATTR_IWBWA_OWBWA_NTR_INDEX      ULL(0x0)
 139 #define LOWER_ATTRS(x)                  (((x) & U(0xfff)) << 2)
 140
 141 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
 142 #define ATTR_NON_CACHEABLE              MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
 143 /* Device-nGnRE */
 144 #define ATTR_DEVICE                     MAIR_DEV_nGnRE
 145 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
 146 #define ATTR_IWBWA_OWBWA_NTR            MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
 147 #define MAIR_ATTR_SET(attr, index)      ((attr) << ((index) << 3))
 148 #define ATTR_INDEX_MASK                 U(0x3)
 149 #define ATTR_INDEX_GET(attr)            (((attr) >> 2) & ATTR_INDEX_MASK)
 150
 151 /*
 152  * Shift values for the attributes fields in a block or page descriptor.
 153  * See section D4.3.3 in the ARMv8-A ARM (issue B.a).
 154  */
 155
 156 /* Memory attributes index field, AttrIndx[2:0]. */
 157 #define ATTR_INDEX_SHIFT                2
 158 /* Non-secure bit, NS. */
 159 #define NS_SHIFT                        5
 160 /* Shareability field, SH[1:0] */
 161 #define SHAREABILITY_SHIFT              8
 162 /* The Access Flag, AF. */
 163 #define ACCESS_FLAG_SHIFT               10
 164 /* The not global bit, nG. */
 165 #define NOT_GLOBAL_SHIFT                11
 166 /* Contiguous hint bit. */
 167 #define CONT_HINT_SHIFT                 52
 168 /* Execute-never bits, XN. */
 169 #define PXN_SHIFT                       53
 170 #define XN_SHIFT                        54
 171 #define UXN_SHIFT                       XN_SHIFT
 172
 173 #endif /* XLAT_TABLES_DEFS_H */