include/lib/xlat_tables/xlat_tables_defs.h

   1 /*
   2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef __XLAT_TABLES_DEFS_H__
   8 #define __XLAT_TABLES_DEFS_H__
   9
  10 #include <arch.h>
  11 #include <utils_def.h>
  12 #include <xlat_mmu_helpers.h>
  13
  14 /* Miscellaneous MMU related constants */
  15 #define NUM_2MB_IN_GB           (U(1) << 9)
  16 #define NUM_4K_IN_2MB           (U(1) << 9)
  17 #define NUM_GB_IN_4GB           (U(1) << 2)
  18
  19 #define TWO_MB_SHIFT            U(21)
  20 #define ONE_GB_SHIFT            U(30)
  21 #define FOUR_KB_SHIFT           U(12)
  22
  23 #define ONE_GB_INDEX(x)         ((x) >> ONE_GB_SHIFT)
  24 #define TWO_MB_INDEX(x)         ((x) >> TWO_MB_SHIFT)
  25 #define FOUR_KB_INDEX(x)        ((x) >> FOUR_KB_SHIFT)
  26
  27 #define INVALID_DESC            U(0x0)
  28 /*
  29  * A block descriptor points to a region of memory bigger than the granule size
  30  * (e.g. a 2MB region when the granule size is 4KB).
  31  */
  32 #define BLOCK_DESC              U(0x1) /* Table levels 0-2 */
  33 /* A table descriptor points to the next level of translation table. */
  34 #define TABLE_DESC              U(0x3) /* Table levels 0-2 */
  35 /*
  36  * A page descriptor points to a page, i.e. a memory region whose size is the
  37  * translation granule size (e.g. 4KB).
  38  */
  39 #define PAGE_DESC               U(0x3) /* Table level 3 */
  40
  41 #define DESC_MASK               U(0x3)
  42
  43 #define FIRST_LEVEL_DESC_N      ONE_GB_SHIFT
  44 #define SECOND_LEVEL_DESC_N     TWO_MB_SHIFT
  45 #define THIRD_LEVEL_DESC_N      FOUR_KB_SHIFT
  46
  47 /* XN: Translation regimes that support one VA range (EL2 and EL3). */
  48 #define XN                      (ULL(1) << 2)
  49 /* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */
  50 #define UXN                     (ULL(1) << 2)
  51 #define PXN                     (ULL(1) << 1)
  52 #define CONT_HINT               (ULL(1) << 0)
  53 #define UPPER_ATTRS(x)          (((x) & ULL(0x7)) << 52)
  54
  55 #define NON_GLOBAL              (U(1) << 9)
  56 #define ACCESS_FLAG             (U(1) << 8)
  57 #define NSH                     (U(0x0) << 6)
  58 #define OSH                     (U(0x2) << 6)
  59 #define ISH                     (U(0x3) << 6)
  60
  61 #define TABLE_ADDR_MASK         ULL(0x0000FFFFFFFFF000)
  62
  63 /*
  64  * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or
  65  * 64KB. However, TF only supports the 4KB case at the moment.
  66  */
  67 #define PAGE_SIZE_SHIFT         FOUR_KB_SHIFT
  68 #define PAGE_SIZE               (U(1) << PAGE_SIZE_SHIFT)
  69 #define PAGE_SIZE_MASK          (PAGE_SIZE - 1)
  70 #define IS_PAGE_ALIGNED(addr)   (((addr) & PAGE_SIZE_MASK) == 0)
  71
  72 #define XLAT_ENTRY_SIZE_SHIFT   U(3) /* Each MMU table entry is 8 bytes (1 << 3) */
  73 #define XLAT_ENTRY_SIZE         (U(1) << XLAT_ENTRY_SIZE_SHIFT)
  74
  75 #define XLAT_TABLE_SIZE_SHIFT   PAGE_SIZE_SHIFT /* Size of one complete table */
  76 #define XLAT_TABLE_SIZE         (U(1) << XLAT_TABLE_SIZE_SHIFT)
  77
  78 #define XLAT_TABLE_LEVEL_MAX    U(3)
  79
  80 /* Values for number of entries in each MMU translation table */
  81 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
  82 #define XLAT_TABLE_ENTRIES      (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
  83 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1)
  84
  85 /* Values to convert a memory address to an index into a translation table */
  86 #define L3_XLAT_ADDRESS_SHIFT   PAGE_SIZE_SHIFT
  87 #define L2_XLAT_ADDRESS_SHIFT   (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
  88 #define L1_XLAT_ADDRESS_SHIFT   (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
  89 #define L0_XLAT_ADDRESS_SHIFT   (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
  90 #define XLAT_ADDR_SHIFT(level)  (PAGE_SIZE_SHIFT + \
  91                   ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
  92
  93 #define XLAT_BLOCK_SIZE(level)  ((u_register_t)1 << XLAT_ADDR_SHIFT(level))
  94 /* Mask to get the bits used to index inside a block of a certain level */
  95 #define XLAT_BLOCK_MASK(level)  (XLAT_BLOCK_SIZE(level) - 1)
  96 /* Mask to get the address bits common to a block of a certain table level*/
  97 #define XLAT_ADDR_MASK(level)   (~XLAT_BLOCK_MASK(level))
  98 /*
  99  * Extract from the given virtual address the index into the given lookup level.
 100  * This macro assumes the system is using the 4KB translation granule.
 101  */
 102 #define XLAT_TABLE_IDX(virtual_addr, level)     \
 103         (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
 104
 105 /*
 106  * The ARMv8 translation table descriptor format defines AP[2:1] as the Access
 107  * Permissions bits, and does not define an AP[0] bit.
 108  *
 109  * AP[1] is valid only for a stage 1 translation that supports two VA ranges
 110  * (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime).
 111  *
 112  * AP[1] is RES0 for stage 1 translations that support only one VA range
 113  * (e.g. EL3).
 114  */
 115 #define AP2_SHIFT                       U(0x7)
 116 #define AP2_RO                          U(0x1)
 117 #define AP2_RW                          U(0x0)
 118
 119 #define AP1_SHIFT                       U(0x6)
 120 #define AP1_ACCESS_UNPRIVILEGED         U(0x1)
 121 #define AP1_NO_ACCESS_UNPRIVILEGED      U(0x0)
 122
 123 /*
 124  * The following definitions must all be passed to the LOWER_ATTRS() macro to
 125  * get the right bitmask.
 126  */
 127 #define AP_RO                           (AP2_RO << 5)
 128 #define AP_RW                           (AP2_RW << 5)
 129 #define AP_ACCESS_UNPRIVILEGED          (AP1_ACCESS_UNPRIVILEGED    << 4)
 130 #define AP_NO_ACCESS_UNPRIVILEGED       (AP1_NO_ACCESS_UNPRIVILEGED << 4)
 131 #define NS                              (U(0x1) << 3)
 132 #define ATTR_NON_CACHEABLE_INDEX        U(0x2)
 133 #define ATTR_DEVICE_INDEX               U(0x1)
 134 #define ATTR_IWBWA_OWBWA_NTR_INDEX      U(0x0)
 135 #define LOWER_ATTRS(x)                  (((x) & U(0xfff)) << 2)
 136
 137 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
 138 #define ATTR_NON_CACHEABLE              MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
 139 /* Device-nGnRE */
 140 #define ATTR_DEVICE                     MAIR_DEV_nGnRE
 141 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
 142 #define ATTR_IWBWA_OWBWA_NTR            MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
 143 #define MAIR_ATTR_SET(attr, index)      ((attr) << ((index) << 3))
 144 #define ATTR_INDEX_MASK                 U(0x3)
 145 #define ATTR_INDEX_GET(attr)            (((attr) >> 2) & ATTR_INDEX_MASK)
 146
 147 /*
 148  * Shift values for the attributes fields in a block or page descriptor.
 149  * See section D4.3.3 in the ARMv8-A ARM (issue B.a).
 150  */
 151
 152 /* Memory attributes index field, AttrIndx[2:0]. */
 153 #define ATTR_INDEX_SHIFT                2
 154 /* Non-secure bit, NS. */
 155 #define NS_SHIFT                        5
 156 /* Shareability field, SH[1:0] */
 157 #define SHAREABILITY_SHIFT              8
 158 /* The Access Flag, AF. */
 159 #define ACCESS_FLAG_SHIFT               10
 160 /* The not global bit, nG. */
 161 #define NOT_GLOBAL_SHIFT                11
 162 /* Contiguous hint bit. */
 163 #define CONT_HINT_SHIFT                 52
 164 /* Execute-never bits, XN. */
 165 #define PXN_SHIFT                       53
 166 #define XN_SHIFT                        54
 167 #define UXN_SHIFT                       XN_SHIFT
 168
 169 #endif /* __XLAT_TABLES_DEFS_H__ */