1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011 Freescale Semiconductor, Inc.
4 * Andy Fleming <afleming@gmail.com>
6 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
13 #include <linux/list.h>
14 #include <linux/mii.h>
15 #include <linux/ethtool.h>
16 #include <linux/mdio.h>
17 #include <phy_interface.h>
19 #define PHY_FIXED_ID 0xa5a55a5a
21 #define PHY_MAX_ADDR 32
23 #define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
25 #define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg | \
29 #define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half | \
30 SUPPORTED_10baseT_Full)
32 #define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half | \
33 SUPPORTED_100baseT_Full)
35 #define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half | \
36 SUPPORTED_1000baseT_Full)
38 #define PHY_BASIC_FEATURES (PHY_10BT_FEATURES | \
39 PHY_100BT_FEATURES | \
42 #define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \
45 #define PHY_10G_FEATURES (PHY_GBIT_FEATURES | \
46 SUPPORTED_10000baseT_Full)
48 #ifndef PHY_ANEG_TIMEOUT
49 #define PHY_ANEG_TIMEOUT 4000
55 #define MDIO_NAME_LEN 32
58 struct list_head link
;
59 char name
[MDIO_NAME_LEN
];
61 int (*read
)(struct mii_dev
*bus
, int addr
, int devad
, int reg
);
62 int (*write
)(struct mii_dev
*bus
, int addr
, int devad
, int reg
,
64 int (*reset
)(struct mii_dev
*bus
);
65 struct phy_device
*phymap
[PHY_MAX_ADDR
];
69 /* struct phy_driver: a structure which defines PHY behavior
71 * uid will contain a number which represents the PHY. During
72 * startup, the driver will poll the PHY to find out what its
73 * UID--as defined by registers 2 and 3--is. The 32-bit result
74 * gotten from the PHY will be masked to
75 * discard any bits which may change based on revision numbers
76 * unimportant to functionality
87 /* Called to do any driver startup necessities */
88 /* Will be called during phy_connect */
89 int (*probe
)(struct phy_device
*phydev
);
91 /* Called to configure the PHY, and modify the controller
92 * based on the results. Should be called after phy_connect */
93 int (*config
)(struct phy_device
*phydev
);
95 /* Called when starting up the controller */
96 int (*startup
)(struct phy_device
*phydev
);
98 /* Called when bringing down the controller */
99 int (*shutdown
)(struct phy_device
*phydev
);
101 int (*readext
)(struct phy_device
*phydev
, int addr
, int devad
, int reg
);
102 int (*writeext
)(struct phy_device
*phydev
, int addr
, int devad
, int reg
,
105 /* Phy specific driver override for reading a MMD register */
106 int (*read_mmd
)(struct phy_device
*phydev
, int devad
, int reg
);
108 /* Phy specific driver override for writing a MMD register */
109 int (*write_mmd
)(struct phy_device
*phydev
, int devad
, int reg
,
112 struct list_head list
;
116 /* Information about the PHY type */
117 /* And management functions */
119 struct phy_driver
*drv
;
126 struct eth_device
*dev
;
129 /* forced speed & duplex (no autoneg)
130 * partner speed & duplex & pause (autoneg)
135 /* The most recently read link state */
138 phy_interface_t interface
;
161 static inline int phy_read(struct phy_device
*phydev
, int devad
, int regnum
)
163 struct mii_dev
*bus
= phydev
->bus
;
165 return bus
->read(bus
, phydev
->addr
, devad
, regnum
);
168 static inline int phy_write(struct phy_device
*phydev
, int devad
, int regnum
,
171 struct mii_dev
*bus
= phydev
->bus
;
173 return bus
->write(bus
, phydev
->addr
, devad
, regnum
, val
);
176 static inline void phy_mmd_start_indirect(struct phy_device
*phydev
, int devad
,
179 /* Write the desired MMD Devad */
180 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_MMD_CTRL
, devad
);
182 /* Write the desired MMD register address */
183 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_MMD_DATA
, regnum
);
185 /* Select the Function : DATA with no post increment */
186 phy_write(phydev
, MDIO_DEVAD_NONE
, MII_MMD_CTRL
,
187 (devad
| MII_MMD_CTRL_NOINCR
));
190 static inline int phy_read_mmd(struct phy_device
*phydev
, int devad
,
193 struct phy_driver
*drv
= phydev
->drv
;
195 if (regnum
> (u16
)~0 || devad
> 32)
198 /* driver-specific access */
200 return drv
->read_mmd(phydev
, devad
, regnum
);
202 /* direct C45 / C22 access */
203 if ((drv
->features
& PHY_10G_FEATURES
) == PHY_10G_FEATURES
||
204 devad
== MDIO_DEVAD_NONE
|| !devad
)
205 return phy_read(phydev
, devad
, regnum
);
207 /* indirect C22 access */
208 phy_mmd_start_indirect(phydev
, devad
, regnum
);
210 /* Read the content of the MMD's selected register */
211 return phy_read(phydev
, MDIO_DEVAD_NONE
, MII_MMD_DATA
);
214 static inline int phy_write_mmd(struct phy_device
*phydev
, int devad
,
217 struct phy_driver
*drv
= phydev
->drv
;
219 if (regnum
> (u16
)~0 || devad
> 32)
222 /* driver-specific access */
224 return drv
->write_mmd(phydev
, devad
, regnum
, val
);
226 /* direct C45 / C22 access */
227 if ((drv
->features
& PHY_10G_FEATURES
) == PHY_10G_FEATURES
||
228 devad
== MDIO_DEVAD_NONE
|| !devad
)
229 return phy_write(phydev
, devad
, regnum
, val
);
231 /* indirect C22 access */
232 phy_mmd_start_indirect(phydev
, devad
, regnum
);
234 /* Write the data into MMD's selected register */
235 return phy_write(phydev
, MDIO_DEVAD_NONE
, MII_MMD_DATA
, val
);
238 #ifdef CONFIG_PHYLIB_10G
239 extern struct phy_driver gen10g_driver
;
241 /* For now, XGMII is the only 10G interface */
242 static inline int is_10g_interface(phy_interface_t interface
)
244 return interface
== PHY_INTERFACE_MODE_XGMII
;
250 int phy_reset(struct phy_device
*phydev
);
251 struct phy_device
*phy_find_by_mask(struct mii_dev
*bus
, unsigned phy_mask
,
252 phy_interface_t interface
);
254 void phy_connect_dev(struct phy_device
*phydev
, struct udevice
*dev
);
255 struct phy_device
*phy_connect(struct mii_dev
*bus
, int addr
,
257 phy_interface_t interface
);
258 static inline ofnode
phy_get_ofnode(struct phy_device
*phydev
)
260 if (ofnode_valid(phydev
->node
))
263 return dev_ofnode(phydev
->dev
);
266 void phy_connect_dev(struct phy_device
*phydev
, struct eth_device
*dev
);
267 struct phy_device
*phy_connect(struct mii_dev
*bus
, int addr
,
268 struct eth_device
*dev
,
269 phy_interface_t interface
);
270 static inline ofnode
phy_get_ofnode(struct phy_device
*phydev
)
272 return ofnode_null();
275 int phy_startup(struct phy_device
*phydev
);
276 int phy_config(struct phy_device
*phydev
);
277 int phy_shutdown(struct phy_device
*phydev
);
278 int phy_register(struct phy_driver
*drv
);
279 int phy_set_supported(struct phy_device
*phydev
, u32 max_speed
);
280 int genphy_config_aneg(struct phy_device
*phydev
);
281 int genphy_restart_aneg(struct phy_device
*phydev
);
282 int genphy_update_link(struct phy_device
*phydev
);
283 int genphy_parse_link(struct phy_device
*phydev
);
284 int genphy_config(struct phy_device
*phydev
);
285 int genphy_startup(struct phy_device
*phydev
);
286 int genphy_shutdown(struct phy_device
*phydev
);
287 int gen10g_config(struct phy_device
*phydev
);
288 int gen10g_startup(struct phy_device
*phydev
);
289 int gen10g_shutdown(struct phy_device
*phydev
);
290 int gen10g_discover_mmds(struct phy_device
*phydev
);
292 int phy_b53_init(void);
293 int phy_mv88e61xx_init(void);
294 int phy_aquantia_init(void);
295 int phy_atheros_init(void);
296 int phy_broadcom_init(void);
297 int phy_cortina_init(void);
298 int phy_davicom_init(void);
299 int phy_et1011c_init(void);
300 int phy_lxt_init(void);
301 int phy_marvell_init(void);
302 int phy_micrel_ksz8xxx_init(void);
303 int phy_micrel_ksz90x1_init(void);
304 int phy_meson_gxl_init(void);
305 int phy_natsemi_init(void);
306 int phy_realtek_init(void);
307 int phy_smsc_init(void);
308 int phy_teranetics_init(void);
309 int phy_ti_init(void);
310 int phy_vitesse_init(void);
311 int phy_xilinx_init(void);
312 int phy_mscc_init(void);
313 int phy_fixed_init(void);
315 int board_phy_config(struct phy_device
*phydev
);
316 int get_phy_id(struct mii_dev
*bus
, int addr
, int devad
, u32
*phy_id
);
319 * phy_get_interface_by_name() - Look up a PHY interface name
321 * @str: PHY interface name, e.g. "mii"
322 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
324 int phy_get_interface_by_name(const char *str
);
327 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
328 * is RGMII (all variants)
329 * @phydev: the phy_device struct
331 static inline bool phy_interface_is_rgmii(struct phy_device
*phydev
)
333 return phydev
->interface
>= PHY_INTERFACE_MODE_RGMII
&&
334 phydev
->interface
<= PHY_INTERFACE_MODE_RGMII_TXID
;
338 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
339 * is SGMII (all variants)
340 * @phydev: the phy_device struct
342 static inline bool phy_interface_is_sgmii(struct phy_device
*phydev
)
344 return phydev
->interface
>= PHY_INTERFACE_MODE_SGMII
&&
345 phydev
->interface
<= PHY_INTERFACE_MODE_QSGMII
;
348 /* PHY UIDs for various PHYs that are referenced in external code */
349 #define PHY_UID_CS4340 0x13e51002
350 #define PHY_UID_CS4223 0x03e57003
351 #define PHY_UID_TN2020 0x00a19410
352 #define PHY_UID_IN112525_S03 0x02107440