include/plat/arm/common/arm_def.h

   1 /*
   2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6 #ifndef ARM_DEF_H
   7 #define ARM_DEF_H
   8
   9 #include <arch.h>
  10 #include <common_def.h>
  11 #include <gic_common.h>
  12 #include <interrupt_props.h>
  13 #include <platform_def.h>
  14 #include <tbbr_img_def.h>
  15 #include <utils_def.h>
  16 #include <xlat_tables_defs.h>
  17
  18
  19 /******************************************************************************
  20  * Definitions common to all ARM standard platforms
  21  *****************************************************************************/
  22
  23 /* Special value used to verify platform parameters from BL2 to BL31 */
  24 #define ARM_BL31_PLAT_PARAM_VAL         ULL(0x0f1e2d3c4b5a6978)
  25
  26 #define ARM_SYSTEM_COUNT                1
  27
  28 #define ARM_CACHE_WRITEBACK_SHIFT       6
  29
  30 /*
  31  * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
  32  * power levels have a 1:1 mapping with the MPIDR affinity levels.
  33  */
  34 #define ARM_PWR_LVL0            MPIDR_AFFLVL0
  35 #define ARM_PWR_LVL1            MPIDR_AFFLVL1
  36 #define ARM_PWR_LVL2            MPIDR_AFFLVL2
  37 #define ARM_PWR_LVL3            MPIDR_AFFLVL3
  38
  39 /*
  40  *  Macros for local power states in ARM platforms encoded by State-ID field
  41  *  within the power-state parameter.
  42  */
  43 /* Local power state for power domains in Run state. */
  44 #define ARM_LOCAL_STATE_RUN     U(0)
  45 /* Local power state for retention. Valid only for CPU power domains */
  46 #define ARM_LOCAL_STATE_RET     U(1)
  47 /* Local power state for OFF/power-down. Valid for CPU and cluster power
  48    domains */
  49 #define ARM_LOCAL_STATE_OFF     U(2)
  50
  51 /* Memory location options for TSP */
  52 #define ARM_TRUSTED_SRAM_ID             0
  53 #define ARM_TRUSTED_DRAM_ID             1
  54 #define ARM_DRAM_ID                     2
  55
  56 /* The first 4KB of Trusted SRAM are used as shared memory */
  57 #define ARM_TRUSTED_SRAM_BASE           UL(0x04000000)
  58 #define ARM_SHARED_RAM_BASE             ARM_TRUSTED_SRAM_BASE
  59 #define ARM_SHARED_RAM_SIZE             UL(0x00001000)  /* 4 KB */
  60
  61 /* The remaining Trusted SRAM is used to load the BL images */
  62 #define ARM_BL_RAM_BASE                 (ARM_SHARED_RAM_BASE +  \
  63                                          ARM_SHARED_RAM_SIZE)
  64 #define ARM_BL_RAM_SIZE                 (PLAT_ARM_TRUSTED_SRAM_SIZE -   \
  65                                          ARM_SHARED_RAM_SIZE)
  66
  67 /*
  68  * The top 16MB of DRAM1 is configured as secure access only using the TZC
  69  *   - SCP TZC DRAM: If present, DRAM reserved for SCP use
  70  *   - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
  71  */
  72 #define ARM_TZC_DRAM1_SIZE              UL(0x01000000)
  73
  74 #define ARM_SCP_TZC_DRAM1_BASE          (ARM_DRAM1_BASE +               \
  75                                          ARM_DRAM1_SIZE -               \
  76                                          ARM_SCP_TZC_DRAM1_SIZE)
  77 #define ARM_SCP_TZC_DRAM1_SIZE          PLAT_ARM_SCP_TZC_DRAM1_SIZE
  78 #define ARM_SCP_TZC_DRAM1_END           (ARM_SCP_TZC_DRAM1_BASE +       \
  79                                          ARM_SCP_TZC_DRAM1_SIZE - 1)
  80
  81 /*
  82  * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
  83  * firmware. This region is meant to be NOLOAD and will not be zero
  84  * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be
  85  * placed here.
  86  */
  87 #define ARM_EL3_TZC_DRAM1_BASE          (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE)
  88 #define ARM_EL3_TZC_DRAM1_SIZE          UL(0x00200000) /* 2 MB */
  89 #define ARM_EL3_TZC_DRAM1_END           (ARM_EL3_TZC_DRAM1_BASE +       \
  90                                         ARM_EL3_TZC_DRAM1_SIZE - 1)
  91
  92 #define ARM_AP_TZC_DRAM1_BASE           (ARM_DRAM1_BASE +               \
  93                                          ARM_DRAM1_SIZE -               \
  94                                          ARM_TZC_DRAM1_SIZE)
  95 #define ARM_AP_TZC_DRAM1_SIZE           (ARM_TZC_DRAM1_SIZE -           \
  96                                          (ARM_SCP_TZC_DRAM1_SIZE +      \
  97                                          ARM_EL3_TZC_DRAM1_SIZE))
  98 #define ARM_AP_TZC_DRAM1_END            (ARM_AP_TZC_DRAM1_BASE +        \
  99                                          ARM_AP_TZC_DRAM1_SIZE - 1)
 100
 101 /* Define the Access permissions for Secure peripherals to NS_DRAM */
 102 #if ARM_CRYPTOCELL_INTEG
 103 /*
 104  * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
 105  * This is required by CryptoCell to authenticate BL33 which is loaded
 106  * into the Non Secure DDR.
 107  */
 108 #define ARM_TZC_NS_DRAM_S_ACCESS        TZC_REGION_S_RD
 109 #else
 110 #define ARM_TZC_NS_DRAM_S_ACCESS        TZC_REGION_S_NONE
 111 #endif
 112
 113 #ifdef SPD_opteed
 114 /*
 115  * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
 116  * load/authenticate the trusted os extra image. The first 512KB of
 117  * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
 118  * for OPTEE is paged image which only include the paging part using
 119  * virtual memory but without "init" data. OPTEE will copy the "init" data
 120  * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
 121  * extra image behind the "init" data.
 122  */
 123 #define ARM_OPTEE_PAGEABLE_LOAD_BASE    (ARM_AP_TZC_DRAM1_BASE + \
 124                                          ARM_AP_TZC_DRAM1_SIZE - \
 125                                          ARM_OPTEE_PAGEABLE_LOAD_SIZE)
 126 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE    UL(0x400000)
 127 #define ARM_OPTEE_PAGEABLE_LOAD_MEM     MAP_REGION_FLAT(                \
 128                                         ARM_OPTEE_PAGEABLE_LOAD_BASE,   \
 129                                         ARM_OPTEE_PAGEABLE_LOAD_SIZE,   \
 130                                         MT_MEMORY | MT_RW | MT_SECURE)
 131
 132 /*
 133  * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
 134  * support is enabled).
 135  */
 136 #define ARM_MAP_OPTEE_CORE_MEM          MAP_REGION_FLAT(                \
 137                                                 BL32_BASE,              \
 138                                                 BL32_LIMIT - BL32_BASE, \
 139                                                 MT_MEMORY | MT_RW | MT_SECURE)
 140 #endif /* SPD_opteed */
 141
 142 #define ARM_NS_DRAM1_BASE               ARM_DRAM1_BASE
 143 #define ARM_NS_DRAM1_SIZE               (ARM_DRAM1_SIZE -               \
 144                                          ARM_TZC_DRAM1_SIZE)
 145 #define ARM_NS_DRAM1_END                (ARM_NS_DRAM1_BASE +            \
 146                                          ARM_NS_DRAM1_SIZE - 1)
 147
 148 #define ARM_DRAM1_BASE                  ULL(0x80000000)
 149 #define ARM_DRAM1_SIZE                  ULL(0x80000000)
 150 #define ARM_DRAM1_END                   (ARM_DRAM1_BASE +               \
 151                                          ARM_DRAM1_SIZE - 1)
 152
 153 #define ARM_DRAM2_BASE                  UL(0x880000000)
 154 #define ARM_DRAM2_SIZE                  PLAT_ARM_DRAM2_SIZE
 155 #define ARM_DRAM2_END                   (ARM_DRAM2_BASE +               \
 156                                          ARM_DRAM2_SIZE - 1)
 157
 158 #define ARM_IRQ_SEC_PHY_TIMER           29
 159
 160 #define ARM_IRQ_SEC_SGI_0               8
 161 #define ARM_IRQ_SEC_SGI_1               9
 162 #define ARM_IRQ_SEC_SGI_2               10
 163 #define ARM_IRQ_SEC_SGI_3               11
 164 #define ARM_IRQ_SEC_SGI_4               12
 165 #define ARM_IRQ_SEC_SGI_5               13
 166 #define ARM_IRQ_SEC_SGI_6               14
 167 #define ARM_IRQ_SEC_SGI_7               15
 168
 169 /*
 170  * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
 171  * terminology. On a GICv2 system or mode, the lists will be merged and treated
 172  * as Group 0 interrupts.
 173  */
 174 #define ARM_G1S_IRQ_PROPS(grp) \
 175         INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 176                         GIC_INTR_CFG_LEVEL), \
 177         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 178                         GIC_INTR_CFG_EDGE), \
 179         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 180                         GIC_INTR_CFG_EDGE), \
 181         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 182                         GIC_INTR_CFG_EDGE), \
 183         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 184                         GIC_INTR_CFG_EDGE), \
 185         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 186                         GIC_INTR_CFG_EDGE), \
 187         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 188                         GIC_INTR_CFG_EDGE)
 189
 190 #define ARM_G0_IRQ_PROPS(grp) \
 191         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
 192                         GIC_INTR_CFG_EDGE), \
 193         INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
 194                         GIC_INTR_CFG_EDGE)
 195
 196 #define ARM_MAP_SHARED_RAM              MAP_REGION_FLAT(                \
 197                                                 ARM_SHARED_RAM_BASE,    \
 198                                                 ARM_SHARED_RAM_SIZE,    \
 199                                                 MT_DEVICE | MT_RW | MT_SECURE)
 200
 201 #define ARM_MAP_NS_DRAM1                MAP_REGION_FLAT(                \
 202                                                 ARM_NS_DRAM1_BASE,      \
 203                                                 ARM_NS_DRAM1_SIZE,      \
 204                                                 MT_MEMORY | MT_RW | MT_NS)
 205
 206 #define ARM_MAP_DRAM2                   MAP_REGION_FLAT(                \
 207                                                 ARM_DRAM2_BASE,         \
 208                                                 ARM_DRAM2_SIZE,         \
 209                                                 MT_MEMORY | MT_RW | MT_NS)
 210
 211 #define ARM_MAP_TSP_SEC_MEM             MAP_REGION_FLAT(                \
 212                                                 TSP_SEC_MEM_BASE,       \
 213                                                 TSP_SEC_MEM_SIZE,       \
 214                                                 MT_MEMORY | MT_RW | MT_SECURE)
 215
 216 #if ARM_BL31_IN_DRAM
 217 #define ARM_MAP_BL31_SEC_DRAM           MAP_REGION_FLAT(                \
 218                                                 BL31_BASE,              \
 219                                                 PLAT_ARM_MAX_BL31_SIZE, \
 220                                                 MT_MEMORY | MT_RW | MT_SECURE)
 221 #endif
 222
 223 #define ARM_MAP_EL3_TZC_DRAM            MAP_REGION_FLAT(                        \
 224                                                 ARM_EL3_TZC_DRAM1_BASE, \
 225                                                 ARM_EL3_TZC_DRAM1_SIZE, \
 226                                                 MT_MEMORY | MT_RW | MT_SECURE)
 227
 228 /*
 229  * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
 230  * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
 231  * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
 232  * to be able to access the heap.
 233  */
 234 #define ARM_MAP_BL1_RW          MAP_REGION_FLAT(        \
 235                                         BL1_RW_BASE,    \
 236                                         BL1_RW_LIMIT - BL1_RW_BASE, \
 237                                         MT_MEMORY | MT_RW | MT_SECURE)
 238
 239 /*
 240  * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
 241  * otherwise one region is defined containing both.
 242  */
 243 #if SEPARATE_CODE_AND_RODATA
 244 #define ARM_MAP_BL_RO                   MAP_REGION_FLAT(                        \
 245                                                 BL_CODE_BASE,                   \
 246                                                 BL_CODE_END - BL_CODE_BASE,     \
 247                                                 MT_CODE | MT_SECURE),           \
 248                                         MAP_REGION_FLAT(                        \
 249                                                 BL_RO_DATA_BASE,                \
 250                                                 BL_RO_DATA_END                  \
 251                                                         - BL_RO_DATA_BASE,      \
 252                                                 MT_RO_DATA | MT_SECURE)
 253 #else
 254 #define ARM_MAP_BL_RO                   MAP_REGION_FLAT(                        \
 255                                                 BL_CODE_BASE,                   \
 256                                                 BL_CODE_END - BL_CODE_BASE,     \
 257                                                 MT_CODE | MT_SECURE)
 258 #endif
 259 #if USE_COHERENT_MEM
 260 #define ARM_MAP_BL_COHERENT_RAM         MAP_REGION_FLAT(                        \
 261                                                 BL_COHERENT_RAM_BASE,           \
 262                                                 BL_COHERENT_RAM_END             \
 263                                                         - BL_COHERENT_RAM_BASE, \
 264                                                 MT_DEVICE | MT_RW | MT_SECURE)
 265 #endif
 266 #if USE_ROMLIB
 267 #define ARM_MAP_ROMLIB_CODE             MAP_REGION_FLAT(                        \
 268                                                 ROMLIB_RO_BASE,                 \
 269                                                 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\
 270                                                 MT_CODE | MT_SECURE)
 271
 272 #define ARM_MAP_ROMLIB_DATA             MAP_REGION_FLAT(                        \
 273                                                 ROMLIB_RW_BASE,                 \
 274                                                 ROMLIB_RW_END   - ROMLIB_RW_BASE,\
 275                                                 MT_MEMORY | MT_RW | MT_SECURE)
 276 #endif
 277
 278 /*
 279  * Map mem_protect flash region with read and write permissions
 280  */
 281 #define ARM_V2M_MAP_MEM_PROTECT         MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
 282                                                 V2M_FLASH_BLOCK_SIZE,           \
 283                                                 MT_DEVICE | MT_RW | MT_SECURE)
 284
 285 /*
 286  * The max number of regions like RO(code), coherent and data required by
 287  * different BL stages which need to be mapped in the MMU.
 288  */
 289 #define ARM_BL_REGIONS                  5
 290
 291 #define MAX_MMAP_REGIONS                (PLAT_ARM_MMAP_ENTRIES +        \
 292                                          ARM_BL_REGIONS)
 293
 294 /* Memory mapped Generic timer interfaces  */
 295 #define ARM_SYS_CNTCTL_BASE             UL(0x2a430000)
 296 #define ARM_SYS_CNTREAD_BASE            UL(0x2a800000)
 297 #define ARM_SYS_TIMCTL_BASE             UL(0x2a810000)
 298 #define ARM_SYS_CNT_BASE_S              UL(0x2a820000)
 299 #define ARM_SYS_CNT_BASE_NS             UL(0x2a830000)
 300
 301 #define ARM_CONSOLE_BAUDRATE            115200
 302
 303 /* Trusted Watchdog constants */
 304 #define ARM_SP805_TWDG_BASE             UL(0x2a490000)
 305 #define ARM_SP805_TWDG_CLK_HZ           32768
 306 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
 307  * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
 308 #define ARM_TWDG_TIMEOUT_SEC            128
 309 #define ARM_TWDG_LOAD_VAL               (ARM_SP805_TWDG_CLK_HZ *        \
 310                                          ARM_TWDG_TIMEOUT_SEC)
 311
 312 /******************************************************************************
 313  * Required platform porting definitions common to all ARM standard platforms
 314  *****************************************************************************/
 315
 316 /*
 317  * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for
 318  * AArch64 builds
 319  */
 320 #ifdef AARCH64
 321 #define PLAT_PHY_ADDR_SPACE_SIZE                        (1ULL << 36)
 322 #define PLAT_VIRT_ADDR_SPACE_SIZE                       (1ULL << 36)
 323 #else
 324 #define PLAT_PHY_ADDR_SPACE_SIZE                        (1ULL << 32)
 325 #define PLAT_VIRT_ADDR_SPACE_SIZE                       (1ULL << 32)
 326 #endif
 327
 328
 329 /*
 330  * This macro defines the deepest retention state possible. A higher state
 331  * id will represent an invalid or a power down state.
 332  */
 333 #define PLAT_MAX_RET_STATE              ARM_LOCAL_STATE_RET
 334
 335 /*
 336  * This macro defines the deepest power down states possible. Any state ID
 337  * higher than this is invalid.
 338  */
 339 #define PLAT_MAX_OFF_STATE              ARM_LOCAL_STATE_OFF
 340
 341 /*
 342  * Some data must be aligned on the biggest cache line size in the platform.
 343  * This is known only to the platform as it might have a combination of
 344  * integrated and external caches.
 345  */
 346 #define CACHE_WRITEBACK_GRANULE         (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
 347
 348 /*
 349  * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
 350  * and limit. Leave enough space of BL2 meminfo.
 351  */
 352 #define ARM_TB_FW_CONFIG_BASE           (ARM_BL_RAM_BASE + sizeof(meminfo_t))
 353 #define ARM_TB_FW_CONFIG_LIMIT          (ARM_BL_RAM_BASE + PAGE_SIZE)
 354
 355 /*******************************************************************************
 356  * BL1 specific defines.
 357  * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
 358  * addresses.
 359  ******************************************************************************/
 360 #define BL1_RO_BASE                     PLAT_ARM_TRUSTED_ROM_BASE
 361 #define BL1_RO_LIMIT                    (PLAT_ARM_TRUSTED_ROM_BASE      \
 362                                          + (PLAT_ARM_TRUSTED_ROM_SIZE - \
 363                                             PLAT_ARM_MAX_ROMLIB_RO_SIZE))
 364 /*
 365  * Put BL1 RW at the top of the Trusted SRAM.
 366  */
 367 #define BL1_RW_BASE                     (ARM_BL_RAM_BASE +              \
 368                                                 ARM_BL_RAM_SIZE -       \
 369                                                 (PLAT_ARM_MAX_BL1_RW_SIZE +\
 370                                                  PLAT_ARM_MAX_ROMLIB_RW_SIZE))
 371 #define BL1_RW_LIMIT                    (ARM_BL_RAM_BASE +              \
 372                                             (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
 373
 374 #define ROMLIB_RO_BASE                  BL1_RO_LIMIT
 375 #define ROMLIB_RO_LIMIT                 (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
 376
 377 #define ROMLIB_RW_BASE                  (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
 378 #define ROMLIB_RW_END                   (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
 379
 380 /*******************************************************************************
 381  * BL2 specific defines.
 382  ******************************************************************************/
 383 #if BL2_AT_EL3
 384 /* Put BL2 towards the middle of the Trusted SRAM */
 385 #define BL2_BASE                        (ARM_TRUSTED_SRAM_BASE + \
 386                                                 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
 387 #define BL2_LIMIT                       (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 388
 389 #else
 390 /*
 391  * Put BL2 just below BL1.
 392  */
 393 #define BL2_BASE                        (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
 394 #define BL2_LIMIT                       BL1_RW_BASE
 395 #endif
 396
 397 /*******************************************************************************
 398  * BL31 specific defines.
 399  ******************************************************************************/
 400 #if ARM_BL31_IN_DRAM
 401 /*
 402  * Put BL31 at the bottom of TZC secured DRAM
 403  */
 404 #define BL31_BASE                       ARM_AP_TZC_DRAM1_BASE
 405 #define BL31_LIMIT                      (ARM_AP_TZC_DRAM1_BASE +        \
 406                                                 PLAT_ARM_MAX_BL31_SIZE)
 407 #elif (RESET_TO_BL31)
 408 /* Ensure Position Independent support (PIE) is enabled for this config.*/
 409 # if !ENABLE_PIE
 410 #  error "BL31 must be a PIE if RESET_TO_BL31=1."
 411 # endif
 412 /*
 413  * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
 414  * used for building BL31 when RESET_TO_BL31=1.
 415  */
 416 #define BL31_BASE                       0x0
 417 #define BL31_LIMIT                      PLAT_ARM_MAX_BL31_SIZE
 418 #else
 419 /* Put BL31 below BL2 in the Trusted SRAM.*/
 420 #define BL31_BASE                       ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
 421                                                 - PLAT_ARM_MAX_BL31_SIZE)
 422 #define BL31_PROGBITS_LIMIT             BL2_BASE
 423 /*
 424  * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is
 425  * because in the BL2_AT_EL3 configuration, BL2 is always resident.
 426  */
 427 #if BL2_AT_EL3
 428 #define BL31_LIMIT                      BL2_BASE
 429 #else
 430 #define BL31_LIMIT                      (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 431 #endif
 432 #endif
 433
 434 #if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME
 435 /*******************************************************************************
 436  * BL32 specific defines for EL3 runtime in AArch32 mode
 437  ******************************************************************************/
 438 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
 439 /*
 440  * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
 441  * the page reserved for fw_configs) to BL32
 442  */
 443 #  define BL32_BASE                     ARM_TB_FW_CONFIG_LIMIT
 444 #  define BL32_LIMIT                    (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 445 # else
 446 /* Put BL32 below BL2 in the Trusted SRAM.*/
 447 #  define BL32_BASE                     ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
 448                                                 - PLAT_ARM_MAX_BL32_SIZE)
 449 #  define BL32_PROGBITS_LIMIT           BL2_BASE
 450 #  define BL32_LIMIT                    (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
 451 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
 452
 453 #else
 454 /*******************************************************************************
 455  * BL32 specific defines for EL3 runtime in AArch64 mode
 456  ******************************************************************************/
 457 /*
 458  * On ARM standard platforms, the TSP can execute from Trusted SRAM,
 459  * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
 460  * controller.
 461  */
 462 # if ENABLE_SPM
 463 #  define TSP_SEC_MEM_BASE              (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
 464 #  define TSP_SEC_MEM_SIZE              (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
 465 #  define BL32_BASE                     (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
 466 #  define BL32_LIMIT                    (ARM_AP_TZC_DRAM1_BASE +        \
 467                                                 ARM_AP_TZC_DRAM1_SIZE)
 468 # elif ARM_BL31_IN_DRAM
 469 #  define TSP_SEC_MEM_BASE              (ARM_AP_TZC_DRAM1_BASE +        \
 470                                                 PLAT_ARM_MAX_BL31_SIZE)
 471 #  define TSP_SEC_MEM_SIZE              (ARM_AP_TZC_DRAM1_SIZE -        \
 472                                                 PLAT_ARM_MAX_BL31_SIZE)
 473 #  define BL32_BASE                     (ARM_AP_TZC_DRAM1_BASE +        \
 474                                                 PLAT_ARM_MAX_BL31_SIZE)
 475 #  define BL32_LIMIT                    (ARM_AP_TZC_DRAM1_BASE +        \
 476                                                 ARM_AP_TZC_DRAM1_SIZE)
 477 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
 478 #  define TSP_SEC_MEM_BASE              ARM_BL_RAM_BASE
 479 #  define TSP_SEC_MEM_SIZE              ARM_BL_RAM_SIZE
 480 #  define TSP_PROGBITS_LIMIT            BL31_BASE
 481 #  define BL32_BASE                     ARM_TB_FW_CONFIG_LIMIT
 482 #  define BL32_LIMIT                    BL31_BASE
 483 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
 484 #  define TSP_SEC_MEM_BASE              PLAT_ARM_TRUSTED_DRAM_BASE
 485 #  define TSP_SEC_MEM_SIZE              PLAT_ARM_TRUSTED_DRAM_SIZE
 486 #  define BL32_BASE                     PLAT_ARM_TRUSTED_DRAM_BASE
 487 #  define BL32_LIMIT                    (PLAT_ARM_TRUSTED_DRAM_BASE     \
 488                                                 + (UL(1) << 21))
 489 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
 490 #  define TSP_SEC_MEM_BASE              ARM_AP_TZC_DRAM1_BASE
 491 #  define TSP_SEC_MEM_SIZE              ARM_AP_TZC_DRAM1_SIZE
 492 #  define BL32_BASE                     ARM_AP_TZC_DRAM1_BASE
 493 #  define BL32_LIMIT                    (ARM_AP_TZC_DRAM1_BASE +        \
 494                                                 ARM_AP_TZC_DRAM1_SIZE)
 495 # else
 496 #  error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
 497 # endif
 498 #endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */
 499
 500 /*
 501  * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
 502  * SPD and no SPM, as they are the only ones that can be used as BL32.
 503  */
 504 #if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME)
 505 # if defined(SPD_none) && !ENABLE_SPM
 506 #  undef BL32_BASE
 507 # endif /* defined(SPD_none) && !ENABLE_SPM */
 508 #endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */
 509
 510 /*******************************************************************************
 511  * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
 512  ******************************************************************************/
 513 #define BL2U_BASE                       BL2_BASE
 514 #define BL2U_LIMIT                      BL2_LIMIT
 515
 516 #define NS_BL2U_BASE                    ARM_NS_DRAM1_BASE
 517 #define NS_BL1U_BASE                    (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
 518
 519 /*
 520  * ID of the secure physical generic timer interrupt used by the TSP.
 521  */
 522 #define TSP_IRQ_SEC_PHY_TIMER           ARM_IRQ_SEC_PHY_TIMER
 523
 524
 525 /*
 526  * One cache line needed for bakery locks on ARM platforms
 527  */
 528 #define PLAT_PERCPU_BAKERY_LOCK_SIZE            (1 * CACHE_WRITEBACK_GRANULE)
 529
 530 /* Priority levels for ARM platforms */
 531 #define PLAT_RAS_PRI                    0x10
 532 #define PLAT_SDEI_CRITICAL_PRI          0x60
 533 #define PLAT_SDEI_NORMAL_PRI            0x70
 534
 535 /* ARM platforms use 3 upper bits of secure interrupt priority */
 536 #define ARM_PRI_BITS                    3
 537
 538 /* SGI used for SDEI signalling */
 539 #define ARM_SDEI_SGI                    ARM_IRQ_SEC_SGI_0
 540
 541 /* ARM SDEI dynamic private event numbers */
 542 #define ARM_SDEI_DP_EVENT_0             1000
 543 #define ARM_SDEI_DP_EVENT_1             1001
 544 #define ARM_SDEI_DP_EVENT_2             1002
 545
 546 /* ARM SDEI dynamic shared event numbers */
 547 #define ARM_SDEI_DS_EVENT_0             2000
 548 #define ARM_SDEI_DS_EVENT_1             2001
 549 #define ARM_SDEI_DS_EVENT_2             2002
 550
 551 #define ARM_SDEI_PRIVATE_EVENTS \
 552         SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
 553         SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
 554         SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
 555         SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
 556
 557 #define ARM_SDEI_SHARED_EVENTS \
 558         SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
 559         SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
 560         SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
 561
 562 #endif /* ARM_DEF_H */