include/plat/arm/common/plat_arm.h

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6 #ifndef PLAT_ARM_H
   7 #define PLAT_ARM_H
   8
   9 #include <stdint.h>
  10
  11 #include <drivers/arm/tzc_common.h>
  12 #include <lib/bakery_lock.h>
  13 #include <lib/cassert.h>
  14 #include <lib/el3_runtime/cpu_data.h>
  15 #include <lib/spinlock.h>
  16 #include <lib/utils_def.h>
  17 #include <lib/xlat_tables/xlat_tables_compat.h>
  18
  19 /*******************************************************************************
  20  * Forward declarations
  21  ******************************************************************************/
  22 struct meminfo;
  23 struct image_info;
  24 struct bl_params;
  25
  26 typedef struct arm_tzc_regions_info {
  27         unsigned long long base;
  28         unsigned long long end;
  29         unsigned int sec_attr;
  30         unsigned int nsaid_permissions;
  31 } arm_tzc_regions_info_t;
  32
  33 /*******************************************************************************
  34  * Default mapping definition of the TrustZone Controller for ARM standard
  35  * platforms.
  36  * Configure:
  37  *   - Region 0 with no access;
  38  *   - Region 1 with secure access only;
  39  *   - the remaining DRAM regions access from the given Non-Secure masters.
  40  ******************************************************************************/
  41 #if ENABLE_SPM && SPM_MM
  42 #define ARM_TZC_REGIONS_DEF                                             \
  43         {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END,                  \
  44                 TZC_REGION_S_RDWR, 0},                                  \
  45         {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
  46                 PLAT_ARM_TZC_NS_DEV_ACCESS},                            \
  47         {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS,       \
  48                 PLAT_ARM_TZC_NS_DEV_ACCESS},                            \
  49         {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE +        \
  50                 PLAT_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE,      \
  51                 PLAT_ARM_TZC_NS_DEV_ACCESS}
  52
  53 #else
  54 #define ARM_TZC_REGIONS_DEF                                             \
  55         {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END,                  \
  56                 TZC_REGION_S_RDWR, 0},                                  \
  57         {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
  58                 PLAT_ARM_TZC_NS_DEV_ACCESS},                            \
  59         {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS,       \
  60                 PLAT_ARM_TZC_NS_DEV_ACCESS}
  61 #endif
  62
  63 #define ARM_CASSERT_MMAP                                                  \
  64         CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \
  65                 assert_plat_arm_mmap_mismatch);                           \
  66         CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)                  \
  67                 <= MAX_MMAP_REGIONS,                                      \
  68                 assert_max_mmap_regions);
  69
  70 void arm_setup_romlib(void);
  71
  72 #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32))
  73 /*
  74  * Use this macro to instantiate lock before it is used in below
  75  * arm_lock_xxx() macros
  76  */
  77 #define ARM_INSTANTIATE_LOCK    static DEFINE_BAKERY_LOCK(arm_lock)
  78 #define ARM_LOCK_GET_INSTANCE   (&arm_lock)
  79
  80 #if !HW_ASSISTED_COHERENCY
  81 #define ARM_SCMI_INSTANTIATE_LOCK       DEFINE_BAKERY_LOCK(arm_scmi_lock)
  82 #else
  83 #define ARM_SCMI_INSTANTIATE_LOCK       spinlock_t arm_scmi_lock
  84 #endif
  85 #define ARM_SCMI_LOCK_GET_INSTANCE      (&arm_scmi_lock)
  86
  87 /*
  88  * These are wrapper macros to the Coherent Memory Bakery Lock API.
  89  */
  90 #define arm_lock_init()         bakery_lock_init(&arm_lock)
  91 #define arm_lock_get()          bakery_lock_get(&arm_lock)
  92 #define arm_lock_release()      bakery_lock_release(&arm_lock)
  93
  94 #else
  95
  96 /*
  97  * Empty macros for all other BL stages other than BL31 and BL32
  98  */
  99 #define ARM_INSTANTIATE_LOCK    static int arm_lock __unused
 100 #define ARM_LOCK_GET_INSTANCE   0
 101 #define arm_lock_init()
 102 #define arm_lock_get()
 103 #define arm_lock_release()
 104
 105 #endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */
 106
 107 #if ARM_RECOM_STATE_ID_ENC
 108 /*
 109  * Macros used to parse state information from State-ID if it is using the
 110  * recommended encoding for State-ID.
 111  */
 112 #define ARM_LOCAL_PSTATE_WIDTH          4
 113 #define ARM_LOCAL_PSTATE_MASK           ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1)
 114
 115 /* Macros to construct the composite power state */
 116
 117 /* Make composite power state parameter till power level 0 */
 118 #if PSCI_EXTENDED_STATE_ID
 119
 120 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
 121                 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT))
 122 #else
 123 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
 124                 (((lvl0_state) << PSTATE_ID_SHIFT) | \
 125                 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
 126                 ((type) << PSTATE_TYPE_SHIFT))
 127 #endif /* __PSCI_EXTENDED_STATE_ID__ */
 128
 129 /* Make composite power state parameter till power level 1 */
 130 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
 131                 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \
 132                 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
 133
 134 /* Make composite power state parameter till power level 2 */
 135 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
 136                 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \
 137                 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type))
 138
 139 #endif /* __ARM_RECOM_STATE_ID_ENC__ */
 140
 141 /* ARM State switch error codes */
 142 #define STATE_SW_E_PARAM                (-2)
 143 #define STATE_SW_E_DENIED               (-3)
 144
 145 /* IO storage utility functions */
 146 void arm_io_setup(void);
 147
 148 /* Security utility functions */
 149 void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions);
 150 struct tzc_dmc500_driver_data;
 151 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data,
 152                         const arm_tzc_regions_info_t *tzc_regions);
 153
 154 /* Console utility functions */
 155 void arm_console_boot_init(void);
 156 void arm_console_boot_end(void);
 157 void arm_console_runtime_init(void);
 158 void arm_console_runtime_end(void);
 159
 160 /* Systimer utility function */
 161 void arm_configure_sys_timer(void);
 162
 163 /* PM utility functions */
 164 int arm_validate_power_state(unsigned int power_state,
 165                             psci_power_state_t *req_state);
 166 int arm_validate_psci_entrypoint(uintptr_t entrypoint);
 167 int arm_validate_ns_entrypoint(uintptr_t entrypoint);
 168 void arm_system_pwr_domain_save(void);
 169 void arm_system_pwr_domain_resume(void);
 170 int arm_psci_read_mem_protect(int *enabled);
 171 int arm_nor_psci_write_mem_protect(int val);
 172 void arm_nor_psci_do_static_mem_protect(void);
 173 void arm_nor_psci_do_dyn_mem_protect(void);
 174 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length);
 175
 176 /* Topology utility function */
 177 int arm_check_mpidr(u_register_t mpidr);
 178
 179 /* BL1 utility functions */
 180 void arm_bl1_early_platform_setup(void);
 181 void arm_bl1_platform_setup(void);
 182 void arm_bl1_plat_arch_setup(void);
 183
 184 /* BL2 utility functions */
 185 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout);
 186 void arm_bl2_platform_setup(void);
 187 void arm_bl2_plat_arch_setup(void);
 188 uint32_t arm_get_spsr_for_bl32_entry(void);
 189 uint32_t arm_get_spsr_for_bl33_entry(void);
 190 int arm_bl2_plat_handle_post_image_load(unsigned int image_id);
 191 int arm_bl2_handle_post_image_load(unsigned int image_id);
 192 struct bl_params *arm_get_next_bl_params(void);
 193
 194 /* BL2 at EL3 functions */
 195 void arm_bl2_el3_early_platform_setup(void);
 196 void arm_bl2_el3_plat_arch_setup(void);
 197
 198 /* BL2U utility functions */
 199 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout,
 200                                 void *plat_info);
 201 void arm_bl2u_platform_setup(void);
 202 void arm_bl2u_plat_arch_setup(void);
 203
 204 /* BL31 utility functions */
 205 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
 206                                 uintptr_t hw_config, void *plat_params_from_bl2);
 207 void arm_bl31_platform_setup(void);
 208 void arm_bl31_plat_runtime_setup(void);
 209 void arm_bl31_plat_arch_setup(void);
 210
 211 /* TSP utility functions */
 212 void arm_tsp_early_platform_setup(void);
 213
 214 /* SP_MIN utility functions */
 215 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config,
 216                                 uintptr_t hw_config, void *plat_params_from_bl2);
 217 void arm_sp_min_plat_runtime_setup(void);
 218
 219 /* FIP TOC validity check */
 220 int arm_io_is_toc_valid(void);
 221
 222 /* Utility functions for Dynamic Config */
 223 void arm_load_tb_fw_config(void);
 224 void arm_bl2_set_tb_cfg_addr(void *dtb);
 225 void arm_bl2_dyn_cfg_init(void);
 226 void arm_bl1_set_mbedtls_heap(void);
 227 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
 228
 229 /*
 230  * Free the memory storing initialization code only used during an images boot
 231  * time so it can be reclaimed for runtime data
 232  */
 233 void arm_free_init_memory(void);
 234
 235 /*
 236  * Mandatory functions required in ARM standard platforms
 237  */
 238 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
 239 void plat_arm_gic_driver_init(void);
 240 void plat_arm_gic_init(void);
 241 void plat_arm_gic_cpuif_enable(void);
 242 void plat_arm_gic_cpuif_disable(void);
 243 void plat_arm_gic_redistif_on(void);
 244 void plat_arm_gic_redistif_off(void);
 245 void plat_arm_gic_pcpu_init(void);
 246 void plat_arm_gic_save(void);
 247 void plat_arm_gic_resume(void);
 248 void plat_arm_security_setup(void);
 249 void plat_arm_pwrc_setup(void);
 250 void plat_arm_interconnect_init(void);
 251 void plat_arm_interconnect_enter_coherency(void);
 252 void plat_arm_interconnect_exit_coherency(void);
 253 void plat_arm_program_trusted_mailbox(uintptr_t address);
 254 int plat_arm_bl1_fwu_needed(void);
 255 __dead2 void plat_arm_error_handler(int err);
 256
 257 #if ARM_PLAT_MT
 258 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr);
 259 #endif
 260
 261 /*
 262  * This function is called after loading SCP_BL2 image and it is used to perform
 263  * any platform-specific actions required to handle the SCP firmware.
 264  */
 265 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info);
 266
 267 /*
 268  * Optional functions required in ARM standard platforms
 269  */
 270 void plat_arm_io_setup(void);
 271 int plat_arm_get_alt_image_source(
 272         unsigned int image_id,
 273         uintptr_t *dev_handle,
 274         uintptr_t *image_spec);
 275 unsigned int plat_arm_calc_core_pos(u_register_t mpidr);
 276 const mmap_region_t *plat_arm_get_mmap(void);
 277
 278 /* Allow platform to override psci_pm_ops during runtime */
 279 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops);
 280
 281 /* Execution state switch in ARM platforms */
 282 int arm_execution_state_switch(unsigned int smc_fid,
 283                 uint32_t pc_hi,
 284                 uint32_t pc_lo,
 285                 uint32_t cookie_hi,
 286                 uint32_t cookie_lo,
 287                 void *handle);
 288
 289 /* Optional functions for SP_MIN */
 290 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1,
 291                         u_register_t arg2, u_register_t arg3);
 292
 293 /* global variables */
 294 extern plat_psci_ops_t plat_arm_psci_pm_ops;
 295 extern const mmap_region_t plat_arm_mmap[];
 296 extern const unsigned int arm_pm_idle_states[];
 297
 298 /* secure watchdog */
 299 void plat_arm_secure_wdt_start(void);
 300 void plat_arm_secure_wdt_stop(void);
 301
 302 #endif /* PLAT_ARM_H */