lib/cpus/aarch64/neoverse_n1.S

   1 /*
   2  * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <asm_macros.S>
   9 #include <neoverse_n1.h>
  10 #include <cpuamu.h>
  11 #include <cpu_macros.S>
  12
  13 /* Hardware handled coherency */
  14 #if HW_ASSISTED_COHERENCY == 0
  15 #error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
  16 #endif
  17
  18 /* 64-bit only core */
  19 #if CTX_INCLUDE_AARCH32_REGS == 1
  20 #error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
  21 #endif
  22
  23 /* --------------------------------------------------
  24  * Errata Workaround for Neoverse N1 Erratum 1043202.
  25  * This applies to revision r0p0 and r1p0 of Neoverse N1.
  26  * Inputs:
  27  * x0: variant[4:7] and revision[0:3] of current cpu.
  28  * Shall clobber: x0-x17
  29  * --------------------------------------------------
  30  */
  31 func errata_n1_1043202_wa
  32         /* Compare x0 against revision r1p0 */
  33         mov     x17, x30
  34         bl      check_errata_1043202
  35         cbz     x0, 1f
  36
  37         /* Apply instruction patching sequence */
  38         ldr     x0, =0x0
  39         msr     CPUPSELR_EL3, x0
  40         ldr     x0, =0xF3BF8F2F
  41         msr     CPUPOR_EL3, x0
  42         ldr     x0, =0xFFFFFFFF
  43         msr     CPUPMR_EL3, x0
  44         ldr     x0, =0x800200071
  45         msr     CPUPCR_EL3, x0
  46         isb
  47 1:
  48         ret     x17
  49 endfunc errata_n1_1043202_wa
  50
  51 func check_errata_1043202
  52         /* Applies to r0p0 and r1p0 */
  53         mov     x1, #0x10
  54         b       cpu_rev_var_ls
  55 endfunc check_errata_1043202
  56
  57 /* --------------------------------------------------
  58  * Disable speculative loads if Neoverse N1 supports
  59  * SSBS.
  60  *
  61  * Shall clobber: x0.
  62  * --------------------------------------------------
  63  */
  64 func neoverse_n1_disable_speculative_loads
  65         /* Check if the PE implements SSBS */
  66         mrs     x0, id_aa64pfr1_el1
  67         tst     x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
  68         b.eq    1f
  69
  70         /* Disable speculative loads */
  71         msr     SSBS, xzr
  72
  73 1:
  74         ret
  75 endfunc neoverse_n1_disable_speculative_loads
  76
  77 /* --------------------------------------------------
  78  * Errata Workaround for Neoverse N1 Errata #1073348
  79  * This applies to revision r0p0 and r1p0 of Neoverse N1.
  80  * Inputs:
  81  * x0: variant[4:7] and revision[0:3] of current cpu.
  82  * Shall clobber: x0-x17
  83  * --------------------------------------------------
  84  */
  85 func errata_n1_1073348_wa
  86         /* Compare x0 against revision r1p0 */
  87         mov     x17, x30
  88         bl      check_errata_1073348
  89         cbz     x0, 1f
  90         mrs     x1, NEOVERSE_N1_CPUACTLR_EL1
  91         orr     x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
  92         msr     NEOVERSE_N1_CPUACTLR_EL1, x1
  93 1:
  94         ret     x17
  95 endfunc errata_n1_1073348_wa
  96
  97 func check_errata_1073348
  98         /* Applies to r0p0 and r1p0 */
  99         mov     x1, #0x10
 100         b       cpu_rev_var_ls
 101 endfunc check_errata_1073348
 102
 103 /* --------------------------------------------------
 104  * Errata Workaround for Neoverse N1 Errata #1130799
 105  * This applies to revision <=r2p0 of Neoverse N1.
 106  * Inputs:
 107  * x0: variant[4:7] and revision[0:3] of current cpu.
 108  * Shall clobber: x0-x17
 109  * --------------------------------------------------
 110  */
 111 func errata_n1_1130799_wa
 112         /* Compare x0 against revision r2p0 */
 113         mov     x17, x30
 114         bl      check_errata_1130799
 115         cbz     x0, 1f
 116         mrs     x1, NEOVERSE_N1_CPUACTLR2_EL1
 117         orr     x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
 118         msr     NEOVERSE_N1_CPUACTLR2_EL1, x1
 119 1:
 120         ret     x17
 121 endfunc errata_n1_1130799_wa
 122
 123 func check_errata_1130799
 124         /* Applies to <=r2p0 */
 125         mov     x1, #0x20
 126         b       cpu_rev_var_ls
 127 endfunc check_errata_1130799
 128
 129 /* --------------------------------------------------
 130  * Errata Workaround for Neoverse N1 Errata #1165347
 131  * This applies to revision <=r2p0 of Neoverse N1.
 132  * Inputs:
 133  * x0: variant[4:7] and revision[0:3] of current cpu.
 134  * Shall clobber: x0-x17
 135  * --------------------------------------------------
 136  */
 137 func errata_n1_1165347_wa
 138         /* Compare x0 against revision r2p0 */
 139         mov     x17, x30
 140         bl      check_errata_1165347
 141         cbz     x0, 1f
 142         mrs     x1, NEOVERSE_N1_CPUACTLR2_EL1
 143         orr     x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
 144         orr     x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
 145         msr     NEOVERSE_N1_CPUACTLR2_EL1, x1
 146 1:
 147         ret     x17
 148 endfunc errata_n1_1165347_wa
 149
 150 func check_errata_1165347
 151         /* Applies to <=r2p0 */
 152         mov     x1, #0x20
 153         b       cpu_rev_var_ls
 154 endfunc check_errata_1165347
 155
 156 /* --------------------------------------------------
 157  * Errata Workaround for Neoverse N1 Errata #1207823
 158  * This applies to revision <=r2p0 of Neoverse N1.
 159  * Inputs:
 160  * x0: variant[4:7] and revision[0:3] of current cpu.
 161  * Shall clobber: x0-x17
 162  * --------------------------------------------------
 163  */
 164 func errata_n1_1207823_wa
 165         /* Compare x0 against revision r2p0 */
 166         mov     x17, x30
 167         bl      check_errata_1207823
 168         cbz     x0, 1f
 169         mrs     x1, NEOVERSE_N1_CPUACTLR2_EL1
 170         orr     x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
 171         msr     NEOVERSE_N1_CPUACTLR2_EL1, x1
 172 1:
 173         ret     x17
 174 endfunc errata_n1_1207823_wa
 175
 176 func check_errata_1207823
 177         /* Applies to <=r2p0 */
 178         mov     x1, #0x20
 179         b       cpu_rev_var_ls
 180 endfunc check_errata_1207823
 181
 182 /* --------------------------------------------------
 183  * Errata Workaround for Neoverse N1 Errata #1220197
 184  * This applies to revision <=r2p0 of Neoverse N1.
 185  * Inputs:
 186  * x0: variant[4:7] and revision[0:3] of current cpu.
 187  * Shall clobber: x0-x17
 188  * --------------------------------------------------
 189  */
 190 func errata_n1_1220197_wa
 191         /* Compare x0 against revision r2p0 */
 192         mov     x17, x30
 193         bl      check_errata_1220197
 194         cbz     x0, 1f
 195         mrs     x1, NEOVERSE_N1_CPUECTLR_EL1
 196         orr     x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
 197         msr     NEOVERSE_N1_CPUECTLR_EL1, x1
 198 1:
 199         ret     x17
 200 endfunc errata_n1_1220197_wa
 201
 202 func check_errata_1220197
 203         /* Applies to <=r2p0 */
 204         mov     x1, #0x20
 205         b       cpu_rev_var_ls
 206 endfunc check_errata_1220197
 207
 208 /* --------------------------------------------------
 209  * Errata Workaround for Neoverse N1 Errata #1257314
 210  * This applies to revision <=r3p0 of Neoverse N1.
 211  * Inputs:
 212  * x0: variant[4:7] and revision[0:3] of current cpu.
 213  * Shall clobber: x0-x17
 214  * --------------------------------------------------
 215  */
 216 func errata_n1_1257314_wa
 217         /* Compare x0 against revision r3p0 */
 218         mov     x17, x30
 219         bl      check_errata_1257314
 220         cbz     x0, 1f
 221         mrs     x1, NEOVERSE_N1_CPUACTLR3_EL1
 222         orr     x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
 223         msr     NEOVERSE_N1_CPUACTLR3_EL1, x1
 224 1:
 225         ret     x17
 226 endfunc errata_n1_1257314_wa
 227
 228 func check_errata_1257314
 229         /* Applies to <=r3p0 */
 230         mov     x1, #0x30
 231         b       cpu_rev_var_ls
 232 endfunc check_errata_1257314
 233
 234 /* --------------------------------------------------
 235  * Errata Workaround for Neoverse N1 Errata #1262606
 236  * This applies to revision <=r3p0 of Neoverse N1.
 237  * Inputs:
 238  * x0: variant[4:7] and revision[0:3] of current cpu.
 239  * Shall clobber: x0-x17
 240  * --------------------------------------------------
 241  */
 242 func errata_n1_1262606_wa
 243         /* Compare x0 against revision r3p0 */
 244         mov     x17, x30
 245         bl      check_errata_1262606
 246         cbz     x0, 1f
 247         mrs     x1, NEOVERSE_N1_CPUACTLR_EL1
 248         orr     x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
 249         msr     NEOVERSE_N1_CPUACTLR_EL1, x1
 250 1:
 251         ret     x17
 252 endfunc errata_n1_1262606_wa
 253
 254 func check_errata_1262606
 255         /* Applies to <=r3p0 */
 256         mov     x1, #0x30
 257         b       cpu_rev_var_ls
 258 endfunc check_errata_1262606
 259
 260 /* --------------------------------------------------
 261  * Errata Workaround for Neoverse N1 Errata #1262888
 262  * This applies to revision <=r3p0 of Neoverse N1.
 263  * Inputs:
 264  * x0: variant[4:7] and revision[0:3] of current cpu.
 265  * Shall clobber: x0-x17
 266  * --------------------------------------------------
 267  */
 268 func errata_n1_1262888_wa
 269         /* Compare x0 against revision r3p0 */
 270         mov     x17, x30
 271         bl      check_errata_1262888
 272         cbz     x0, 1f
 273         mrs     x1, NEOVERSE_N1_CPUECTLR_EL1
 274         orr     x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
 275         msr     NEOVERSE_N1_CPUECTLR_EL1, x1
 276 1:
 277         ret     x17
 278 endfunc errata_n1_1262888_wa
 279
 280 func check_errata_1262888
 281         /* Applies to <=r3p0 */
 282         mov     x1, #0x30
 283         b       cpu_rev_var_ls
 284 endfunc check_errata_1262888
 285
 286 /* --------------------------------------------------
 287  * Errata Workaround for Neoverse N1 Errata #1275112
 288  * This applies to revision <=r3p0 of Neoverse N1.
 289  * Inputs:
 290  * x0: variant[4:7] and revision[0:3] of current cpu.
 291  * Shall clobber: x0-x17
 292  * --------------------------------------------------
 293  */
 294 func errata_n1_1275112_wa
 295         /* Compare x0 against revision r3p0 */
 296         mov     x17, x30
 297         bl      check_errata_1275112
 298         cbz     x0, 1f
 299         mrs     x1, NEOVERSE_N1_CPUACTLR_EL1
 300         orr     x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
 301         msr     NEOVERSE_N1_CPUACTLR_EL1, x1
 302 1:
 303         ret     x17
 304 endfunc errata_n1_1275112_wa
 305
 306 func check_errata_1275112
 307         /* Applies to <=r3p0 */
 308         mov     x1, #0x30
 309         b       cpu_rev_var_ls
 310 endfunc check_errata_1275112
 311
 312 /* --------------------------------------------------
 313  * Errata Workaround for Neoverse N1 Erratum 1315703.
 314  * This applies to revision <= r3p0 of Neoverse N1.
 315  * Inputs:
 316  * x0: variant[4:7] and revision[0:3] of current cpu.
 317  * Shall clobber: x0-x17
 318  * --------------------------------------------------
 319  */
 320 func errata_n1_1315703_wa
 321         /* Compare x0 against revision r3p1 */
 322         mov     x17, x30
 323         bl      check_errata_1315703
 324         cbz     x0, 1f
 325
 326         mrs     x0, NEOVERSE_N1_CPUACTLR2_EL1
 327         orr     x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
 328         msr     NEOVERSE_N1_CPUACTLR2_EL1, x0
 329
 330 1:
 331         ret     x17
 332 endfunc errata_n1_1315703_wa
 333
 334 func check_errata_1315703
 335         /* Applies to everything <= r3p0. */
 336         mov     x1, #0x30
 337         b       cpu_rev_var_ls
 338 endfunc check_errata_1315703
 339
 340 func neoverse_n1_reset_func
 341         mov     x19, x30
 342
 343         bl neoverse_n1_disable_speculative_loads
 344
 345         /* Forces all cacheable atomic instructions to be near */
 346         mrs     x0, NEOVERSE_N1_CPUACTLR2_EL1
 347         orr     x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
 348         msr     NEOVERSE_N1_CPUACTLR2_EL1, x0
 349         isb
 350
 351         bl      cpu_get_rev_var
 352         mov     x18, x0
 353
 354 #if ERRATA_N1_1043202
 355         mov     x0, x18
 356         bl      errata_n1_1043202_wa
 357 #endif
 358
 359 #if ERRATA_N1_1073348
 360         mov     x0, x18
 361         bl      errata_n1_1073348_wa
 362 #endif
 363
 364 #if ERRATA_N1_1130799
 365         mov     x0, x18
 366         bl      errata_n1_1130799_wa
 367 #endif
 368
 369 #if ERRATA_N1_1165347
 370         mov     x0, x18
 371         bl      errata_n1_1165347_wa
 372 #endif
 373
 374 #if ERRATA_N1_1207823
 375         mov     x0, x18
 376         bl      errata_n1_1207823_wa
 377 #endif
 378
 379 #if ERRATA_N1_1220197
 380         mov     x0, x18
 381         bl      errata_n1_1220197_wa
 382 #endif
 383
 384 #if ERRATA_N1_1257314
 385         mov     x0, x18
 386         bl      errata_n1_1257314_wa
 387 #endif
 388
 389 #if ERRATA_N1_1262606
 390         mov     x0, x18
 391         bl      errata_n1_1262606_wa
 392 #endif
 393
 394 #if ERRATA_N1_1262888
 395         mov     x0, x18
 396         bl      errata_n1_1262888_wa
 397 #endif
 398
 399 #if ERRATA_N1_1275112
 400         mov     x0, x18
 401         bl      errata_n1_1275112_wa
 402 #endif
 403
 404 #if ERRATA_N1_1315703
 405         mov     x0, x18
 406         bl      errata_n1_1315703_wa
 407 #endif
 408
 409 #if ENABLE_AMU
 410         /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 411         mrs     x0, actlr_el3
 412         orr     x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
 413         msr     actlr_el3, x0
 414
 415         /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
 416         mrs     x0, actlr_el2
 417         orr     x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
 418         msr     actlr_el2, x0
 419
 420         /* Enable group0 counters */
 421         mov     x0, #NEOVERSE_N1_AMU_GROUP0_MASK
 422         msr     CPUAMCNTENSET_EL0, x0
 423 #endif
 424
 425 #if ERRATA_DSU_936184
 426         bl      errata_dsu_936184_wa
 427 #endif
 428
 429         isb
 430         ret     x19
 431 endfunc neoverse_n1_reset_func
 432
 433         /* ---------------------------------------------
 434          * HW will do the cache maintenance while powering down
 435          * ---------------------------------------------
 436          */
 437 func neoverse_n1_core_pwr_dwn
 438         /* ---------------------------------------------
 439          * Enable CPU power down bit in power control register
 440          * ---------------------------------------------
 441          */
 442         mrs     x0, NEOVERSE_N1_CPUPWRCTLR_EL1
 443         orr     x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
 444         msr     NEOVERSE_N1_CPUPWRCTLR_EL1, x0
 445         isb
 446         ret
 447 endfunc neoverse_n1_core_pwr_dwn
 448
 449 #if REPORT_ERRATA
 450 /*
 451  * Errata printing function for Neoverse N1. Must follow AAPCS.
 452  */
 453 func neoverse_n1_errata_report
 454         stp     x8, x30, [sp, #-16]!
 455
 456         bl      cpu_get_rev_var
 457         mov     x8, x0
 458
 459         /*
 460          * Report all errata. The revision-variant information is passed to
 461          * checking functions of each errata.
 462          */
 463         report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
 464         report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
 465         report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
 466         report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
 467         report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
 468         report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
 469         report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
 470         report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
 471         report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
 472         report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
 473         report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
 474         report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
 475
 476         ldp     x8, x30, [sp], #16
 477         ret
 478 endfunc neoverse_n1_errata_report
 479 #endif
 480
 481         /* ---------------------------------------------
 482          * This function provides neoverse_n1 specific
 483          * register information for crash reporting.
 484          * It needs to return with x6 pointing to
 485          * a list of register names in ascii and
 486          * x8 - x15 having values of registers to be
 487          * reported.
 488          * ---------------------------------------------
 489          */
 490 .section .rodata.neoverse_n1_regs, "aS"
 491 neoverse_n1_regs:  /* The ascii list of register names to be reported */
 492         .asciz  "cpuectlr_el1", ""
 493
 494 func neoverse_n1_cpu_reg_dump
 495         adr     x6, neoverse_n1_regs
 496         mrs     x8, NEOVERSE_N1_CPUECTLR_EL1
 497         ret
 498 endfunc neoverse_n1_cpu_reg_dump
 499
 500 declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \
 501         neoverse_n1_reset_func, \
 502         neoverse_n1_core_pwr_dwn