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[project/bcm63xx/atf.git] / lib / el3_runtime / aarch64 / context_mgmt.c
1 /*
2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <stdbool.h>
9 #include <string.h>
10
11 #include <platform_def.h>
12
13 #include <arch.h>
14 #include <arch_helpers.h>
15 #include <arch_features.h>
16 #include <bl31/interrupt_mgmt.h>
17 #include <common/bl_common.h>
18 #include <context.h>
19 #include <lib/el3_runtime/context_mgmt.h>
20 #include <lib/el3_runtime/pubsub_events.h>
21 #include <lib/extensions/amu.h>
22 #include <lib/extensions/mpam.h>
23 #include <lib/extensions/spe.h>
24 #include <lib/extensions/sve.h>
25 #include <lib/utils.h>
26 #include <plat/common/platform.h>
27 #include <smccc_helpers.h>
28
29
30 /*******************************************************************************
31 * Context management library initialisation routine. This library is used by
32 * runtime services to share pointers to 'cpu_context' structures for the secure
33 * and non-secure states. Management of the structures and their associated
34 * memory is not done by the context management library e.g. the PSCI service
35 * manages the cpu context used for entry from and exit to the non-secure state.
36 * The Secure payload dispatcher service manages the context(s) corresponding to
37 * the secure state. It also uses this library to get access to the non-secure
38 * state cpu context pointers.
39 * Lastly, this library provides the api to make SP_EL3 point to the cpu context
40 * which will used for programming an entry into a lower EL. The same context
41 * will used to save state upon exception entry from that EL.
42 ******************************************************************************/
43 void __init cm_init(void)
44 {
45 /*
46 * The context management library has only global data to intialize, but
47 * that will be done when the BSS is zeroed out
48 */
49 }
50
51 /*******************************************************************************
52 * The following function initializes the cpu_context 'ctx' for
53 * first use, and sets the initial entrypoint state as specified by the
54 * entry_point_info structure.
55 *
56 * The security state to initialize is determined by the SECURE attribute
57 * of the entry_point_info.
58 *
59 * The EE and ST attributes are used to configure the endianness and secure
60 * timer availability for the new execution context.
61 *
62 * To prepare the register state for entry call cm_prepare_el3_exit() and
63 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
64 * cm_e1_sysreg_context_restore().
65 ******************************************************************************/
66 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
67 {
68 unsigned int security_state;
69 uint32_t scr_el3;
70 el3_state_t *state;
71 gp_regs_t *gp_regs;
72 unsigned long sctlr_elx, actlr_elx;
73
74 assert(ctx != NULL);
75
76 security_state = GET_SECURITY_STATE(ep->h.attr);
77
78 /* Clear any residual register values from the context */
79 zeromem(ctx, sizeof(*ctx));
80
81 /*
82 * SCR_EL3 was initialised during reset sequence in macro
83 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
84 * affect the next EL.
85 *
86 * The following fields are initially set to zero and then updated to
87 * the required value depending on the state of the SPSR_EL3 and the
88 * Security state and entrypoint attributes of the next EL.
89 */
90 scr_el3 = (uint32_t)read_scr();
91 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
92 SCR_ST_BIT | SCR_HCE_BIT);
93 /*
94 * SCR_NS: Set the security state of the next EL.
95 */
96 if (security_state != SECURE)
97 scr_el3 |= SCR_NS_BIT;
98 /*
99 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
100 * Exception level as specified by SPSR.
101 */
102 if (GET_RW(ep->spsr) == MODE_RW_64)
103 scr_el3 |= SCR_RW_BIT;
104 /*
105 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
106 * Secure timer registers to EL3, from AArch64 state only, if specified
107 * by the entrypoint attributes.
108 */
109 if (EP_GET_ST(ep->h.attr) != 0U)
110 scr_el3 |= SCR_ST_BIT;
111
112 #if !HANDLE_EA_EL3_FIRST
113 /*
114 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
115 * to EL3 when executing at a lower EL. When executing at EL3, External
116 * Aborts are taken to EL3.
117 */
118 scr_el3 &= ~SCR_EA_BIT;
119 #endif
120
121 #if FAULT_INJECTION_SUPPORT
122 /* Enable fault injection from lower ELs */
123 scr_el3 |= SCR_FIEN_BIT;
124 #endif
125
126 #if !CTX_INCLUDE_PAUTH_REGS
127 /*
128 * If the pointer authentication registers aren't saved during world
129 * switches the value of the registers can be leaked from the Secure to
130 * the Non-secure world. To prevent this, rather than enabling pointer
131 * authentication everywhere, we only enable it in the Non-secure world.
132 *
133 * If the Secure world wants to use pointer authentication,
134 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
135 */
136 if (security_state == NON_SECURE)
137 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
138 #endif /* !CTX_INCLUDE_PAUTH_REGS */
139
140 unsigned int mte = get_armv8_5_mte_support();
141
142 /*
143 * Enable MTE support unilaterally for normal world if the CPU supports
144 * it.
145 */
146 if (mte != MTE_UNIMPLEMENTED) {
147 if (security_state == NON_SECURE) {
148 scr_el3 |= SCR_ATA_BIT;
149 }
150 }
151
152 #ifdef IMAGE_BL31
153 /*
154 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
155 * indicated by the interrupt routing model for BL31.
156 */
157 scr_el3 |= get_scr_el3_from_routing_model(security_state);
158 #endif
159
160 /*
161 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
162 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
163 * next mode is Hyp.
164 */
165 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
166 || ((GET_RW(ep->spsr) != MODE_RW_64)
167 && (GET_M32(ep->spsr) == MODE32_hyp))) {
168 scr_el3 |= SCR_HCE_BIT;
169 }
170
171 /*
172 * Initialise SCTLR_EL1 to the reset value corresponding to the target
173 * execution state setting all fields rather than relying of the hw.
174 * Some fields have architecturally UNKNOWN reset values and these are
175 * set to zero.
176 *
177 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
178 *
179 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
180 * required by PSCI specification)
181 */
182 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
183 if (GET_RW(ep->spsr) == MODE_RW_64)
184 sctlr_elx |= SCTLR_EL1_RES1;
185 else {
186 /*
187 * If the target execution state is AArch32 then the following
188 * fields need to be set.
189 *
190 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
191 * instructions are not trapped to EL1.
192 *
193 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
194 * instructions are not trapped to EL1.
195 *
196 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
197 * CP15DMB, CP15DSB, and CP15ISB instructions.
198 */
199 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
200 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
201 }
202
203 #if ERRATA_A75_764081
204 /*
205 * If workaround of errata 764081 for Cortex-A75 is used then set
206 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
207 */
208 sctlr_elx |= SCTLR_IESB_BIT;
209 #endif
210
211 /*
212 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
213 * and other EL2 registers are set up by cm_prepare_ns_entry() as they
214 * are not part of the stored cpu_context.
215 */
216 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
217
218 /*
219 * Base the context ACTLR_EL1 on the current value, as it is
220 * implementation defined. The context restore process will write
221 * the value from the context to the actual register and can cause
222 * problems for processor cores that don't expect certain bits to
223 * be zero.
224 */
225 actlr_elx = read_actlr_el1();
226 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
227
228 /*
229 * Populate EL3 state so that we've the right context
230 * before doing ERET
231 */
232 state = get_el3state_ctx(ctx);
233 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
234 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
235 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
236
237 /*
238 * Store the X0-X7 value from the entrypoint into the context
239 * Use memcpy as we are in control of the layout of the structures
240 */
241 gp_regs = get_gpregs_ctx(ctx);
242 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
243 }
244
245 /*******************************************************************************
246 * Enable architecture extensions on first entry to Non-secure world.
247 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
248 * it is zero.
249 ******************************************************************************/
250 static void enable_extensions_nonsecure(bool el2_unused)
251 {
252 #if IMAGE_BL31
253 #if ENABLE_SPE_FOR_LOWER_ELS
254 spe_enable(el2_unused);
255 #endif
256
257 #if ENABLE_AMU
258 amu_enable(el2_unused);
259 #endif
260
261 #if ENABLE_SVE_FOR_NS
262 sve_enable(el2_unused);
263 #endif
264
265 #if ENABLE_MPAM_FOR_LOWER_ELS
266 mpam_enable(el2_unused);
267 #endif
268 #endif
269 }
270
271 /*******************************************************************************
272 * The following function initializes the cpu_context for a CPU specified by
273 * its `cpu_idx` for first use, and sets the initial entrypoint state as
274 * specified by the entry_point_info structure.
275 ******************************************************************************/
276 void cm_init_context_by_index(unsigned int cpu_idx,
277 const entry_point_info_t *ep)
278 {
279 cpu_context_t *ctx;
280 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
281 cm_setup_context(ctx, ep);
282 }
283
284 /*******************************************************************************
285 * The following function initializes the cpu_context for the current CPU
286 * for first use, and sets the initial entrypoint state as specified by the
287 * entry_point_info structure.
288 ******************************************************************************/
289 void cm_init_my_context(const entry_point_info_t *ep)
290 {
291 cpu_context_t *ctx;
292 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
293 cm_setup_context(ctx, ep);
294 }
295
296 /*******************************************************************************
297 * Prepare the CPU system registers for first entry into secure or normal world
298 *
299 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
300 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
301 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
302 * For all entries, the EL1 registers are initialized from the cpu_context
303 ******************************************************************************/
304 void cm_prepare_el3_exit(uint32_t security_state)
305 {
306 uint32_t sctlr_elx, scr_el3, mdcr_el2;
307 cpu_context_t *ctx = cm_get_context(security_state);
308 bool el2_unused = false;
309 uint64_t hcr_el2 = 0U;
310
311 assert(ctx != NULL);
312
313 if (security_state == NON_SECURE) {
314 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx),
315 CTX_SCR_EL3);
316 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
317 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
318 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx),
319 CTX_SCTLR_EL1);
320 sctlr_elx &= SCTLR_EE_BIT;
321 sctlr_elx |= SCTLR_EL2_RES1;
322 #if ERRATA_A75_764081
323 /*
324 * If workaround of errata 764081 for Cortex-A75 is used
325 * then set SCTLR_EL2.IESB to enable Implicit Error
326 * Synchronization Barrier.
327 */
328 sctlr_elx |= SCTLR_IESB_BIT;
329 #endif
330 write_sctlr_el2(sctlr_elx);
331 } else if (el_implemented(2) != EL_IMPL_NONE) {
332 el2_unused = true;
333
334 /*
335 * EL2 present but unused, need to disable safely.
336 * SCTLR_EL2 can be ignored in this case.
337 *
338 * Set EL2 register width appropriately: Set HCR_EL2
339 * field to match SCR_EL3.RW.
340 */
341 if ((scr_el3 & SCR_RW_BIT) != 0U)
342 hcr_el2 |= HCR_RW_BIT;
343
344 /*
345 * For Armv8.3 pointer authentication feature, disable
346 * traps to EL2 when accessing key registers or using
347 * pointer authentication instructions from lower ELs.
348 */
349 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
350
351 write_hcr_el2(hcr_el2);
352
353 /*
354 * Initialise CPTR_EL2 setting all fields rather than
355 * relying on the hw. All fields have architecturally
356 * UNKNOWN reset values.
357 *
358 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
359 * accesses to the CPACR_EL1 or CPACR from both
360 * Execution states do not trap to EL2.
361 *
362 * CPTR_EL2.TTA: Set to zero so that Non-secure System
363 * register accesses to the trace registers from both
364 * Execution states do not trap to EL2.
365 *
366 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
367 * to SIMD and floating-point functionality from both
368 * Execution states do not trap to EL2.
369 */
370 write_cptr_el2(CPTR_EL2_RESET_VAL &
371 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
372 | CPTR_EL2_TFP_BIT));
373
374 /*
375 * Initialise CNTHCTL_EL2. All fields are
376 * architecturally UNKNOWN on reset and are set to zero
377 * except for field(s) listed below.
378 *
379 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to
380 * Hyp mode of Non-secure EL0 and EL1 accesses to the
381 * physical timer registers.
382 *
383 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
384 * Hyp mode of Non-secure EL0 and EL1 accesses to the
385 * physical counter registers.
386 */
387 write_cnthctl_el2(CNTHCTL_RESET_VAL |
388 EL1PCEN_BIT | EL1PCTEN_BIT);
389
390 /*
391 * Initialise CNTVOFF_EL2 to zero as it resets to an
392 * architecturally UNKNOWN value.
393 */
394 write_cntvoff_el2(0);
395
396 /*
397 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
398 * MPIDR_EL1 respectively.
399 */
400 write_vpidr_el2(read_midr_el1());
401 write_vmpidr_el2(read_mpidr_el1());
402
403 /*
404 * Initialise VTTBR_EL2. All fields are architecturally
405 * UNKNOWN on reset.
406 *
407 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
408 * 2 address translation is disabled, cache maintenance
409 * operations depend on the VMID.
410 *
411 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
412 * translation is disabled.
413 */
414 write_vttbr_el2(VTTBR_RESET_VAL &
415 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
416 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
417
418 /*
419 * Initialise MDCR_EL2, setting all fields rather than
420 * relying on hw. Some fields are architecturally
421 * UNKNOWN on reset.
422 *
423 * MDCR_EL2.HLP: Set to one so that event counter
424 * overflow, that is recorded in PMOVSCLR_EL0[0-30],
425 * occurs on the increment that changes
426 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
427 * implemented. This bit is RES0 in versions of the
428 * architecture earlier than ARMv8.5, setting it to 1
429 * doesn't have any effect on them.
430 *
431 * MDCR_EL2.TTRF: Set to zero so that access to Trace
432 * Filter Control register TRFCR_EL1 at EL1 is not
433 * trapped to EL2. This bit is RES0 in versions of
434 * the architecture earlier than ARMv8.4.
435 *
436 * MDCR_EL2.HPMD: Set to one so that event counting is
437 * prohibited at EL2. This bit is RES0 in versions of
438 * the architecture earlier than ARMv8.1, setting it
439 * to 1 doesn't have any effect on them.
440 *
441 * MDCR_EL2.TPMS: Set to zero so that accesses to
442 * Statistical Profiling control registers from EL1
443 * do not trap to EL2. This bit is RES0 when SPE is
444 * not implemented.
445 *
446 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
447 * EL1 System register accesses to the Debug ROM
448 * registers are not trapped to EL2.
449 *
450 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
451 * System register accesses to the powerdown debug
452 * registers are not trapped to EL2.
453 *
454 * MDCR_EL2.TDA: Set to zero so that System register
455 * accesses to the debug registers do not trap to EL2.
456 *
457 * MDCR_EL2.TDE: Set to zero so that debug exceptions
458 * are not routed to EL2.
459 *
460 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
461 * Monitors.
462 *
463 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
464 * EL1 accesses to all Performance Monitors registers
465 * are not trapped to EL2.
466 *
467 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
468 * and EL1 accesses to the PMCR_EL0 or PMCR are not
469 * trapped to EL2.
470 *
471 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
472 * architecturally-defined reset value.
473 */
474 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
475 MDCR_EL2_HPMD) |
476 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
477 >> PMCR_EL0_N_SHIFT)) &
478 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
479 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
480 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
481 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
482 MDCR_EL2_TPMCR_BIT);
483
484 write_mdcr_el2(mdcr_el2);
485
486 /*
487 * Initialise HSTR_EL2. All fields are architecturally
488 * UNKNOWN on reset.
489 *
490 * HSTR_EL2.T<n>: Set all these fields to zero so that
491 * Non-secure EL0 or EL1 accesses to System registers
492 * do not trap to EL2.
493 */
494 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
495 /*
496 * Initialise CNTHP_CTL_EL2. All fields are
497 * architecturally UNKNOWN on reset.
498 *
499 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
500 * physical timer and prevent timer interrupts.
501 */
502 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
503 ~(CNTHP_CTL_ENABLE_BIT));
504 }
505 enable_extensions_nonsecure(el2_unused);
506 }
507
508 cm_el1_sysregs_context_restore(security_state);
509 cm_set_next_eret_context(security_state);
510 }
511
512 /*******************************************************************************
513 * The next four functions are used by runtime services to save and restore
514 * EL1 context on the 'cpu_context' structure for the specified security
515 * state.
516 ******************************************************************************/
517 void cm_el1_sysregs_context_save(uint32_t security_state)
518 {
519 cpu_context_t *ctx;
520
521 ctx = cm_get_context(security_state);
522 assert(ctx != NULL);
523
524 el1_sysregs_context_save(get_sysregs_ctx(ctx));
525
526 #if IMAGE_BL31
527 if (security_state == SECURE)
528 PUBLISH_EVENT(cm_exited_secure_world);
529 else
530 PUBLISH_EVENT(cm_exited_normal_world);
531 #endif
532 }
533
534 void cm_el1_sysregs_context_restore(uint32_t security_state)
535 {
536 cpu_context_t *ctx;
537
538 ctx = cm_get_context(security_state);
539 assert(ctx != NULL);
540
541 el1_sysregs_context_restore(get_sysregs_ctx(ctx));
542
543 #if IMAGE_BL31
544 if (security_state == SECURE)
545 PUBLISH_EVENT(cm_entering_secure_world);
546 else
547 PUBLISH_EVENT(cm_entering_normal_world);
548 #endif
549 }
550
551 /*******************************************************************************
552 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
553 * given security state with the given entrypoint
554 ******************************************************************************/
555 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
556 {
557 cpu_context_t *ctx;
558 el3_state_t *state;
559
560 ctx = cm_get_context(security_state);
561 assert(ctx != NULL);
562
563 /* Populate EL3 state so that ERET jumps to the correct entry */
564 state = get_el3state_ctx(ctx);
565 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
566 }
567
568 /*******************************************************************************
569 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
570 * pertaining to the given security state
571 ******************************************************************************/
572 void cm_set_elr_spsr_el3(uint32_t security_state,
573 uintptr_t entrypoint, uint32_t spsr)
574 {
575 cpu_context_t *ctx;
576 el3_state_t *state;
577
578 ctx = cm_get_context(security_state);
579 assert(ctx != NULL);
580
581 /* Populate EL3 state so that ERET jumps to the correct entry */
582 state = get_el3state_ctx(ctx);
583 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
584 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
585 }
586
587 /*******************************************************************************
588 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
589 * pertaining to the given security state using the value and bit position
590 * specified in the parameters. It preserves all other bits.
591 ******************************************************************************/
592 void cm_write_scr_el3_bit(uint32_t security_state,
593 uint32_t bit_pos,
594 uint32_t value)
595 {
596 cpu_context_t *ctx;
597 el3_state_t *state;
598 uint32_t scr_el3;
599
600 ctx = cm_get_context(security_state);
601 assert(ctx != NULL);
602
603 /* Ensure that the bit position is a valid one */
604 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
605
606 /* Ensure that the 'value' is only a bit wide */
607 assert(value <= 1U);
608
609 /*
610 * Get the SCR_EL3 value from the cpu context, clear the desired bit
611 * and set it to its new value.
612 */
613 state = get_el3state_ctx(ctx);
614 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
615 scr_el3 &= ~(1U << bit_pos);
616 scr_el3 |= value << bit_pos;
617 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
618 }
619
620 /*******************************************************************************
621 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
622 * given security state.
623 ******************************************************************************/
624 uint32_t cm_get_scr_el3(uint32_t security_state)
625 {
626 cpu_context_t *ctx;
627 el3_state_t *state;
628
629 ctx = cm_get_context(security_state);
630 assert(ctx != NULL);
631
632 /* Populate EL3 state so that ERET jumps to the correct entry */
633 state = get_el3state_ctx(ctx);
634 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
635 }
636
637 /*******************************************************************************
638 * This function is used to program the context that's used for exception
639 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
640 * the required security state
641 ******************************************************************************/
642 void cm_set_next_eret_context(uint32_t security_state)
643 {
644 cpu_context_t *ctx;
645
646 ctx = cm_get_context(security_state);
647 assert(ctx != NULL);
648
649 cm_set_next_context(ctx);
650 }
Broadcom-s Trusted Firmware A