lib/xlat_tables/aarch64/xlat_tables.c

   1 /*
   2  * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #include <arch.h>
   8 #include <arch_helpers.h>
   9 #include <assert.h>
  10 #include <bl_common.h>
  11 #include <cassert.h>
  12 #include <common_def.h>
  13 #include <platform_def.h>
  14 #include <sys/types.h>
  15 #include <utils.h>
  16 #include <xlat_tables.h>
  17 #include "../xlat_tables_private.h"
  18
  19 /*
  20  * Each platform can define the size of the virtual address space, which is
  21  * defined in PLAT_VIRT_ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the
  22  * width of said address space. The value of TCR.TxSZ must be in the range 16
  23  * to 39 [1], which means that the virtual address space width must be in the
  24  * range 48 to 25 bits.
  25  *
  26  * Here we calculate the initial lookup level from the value of
  27  * PLAT_VIRT_ADDR_SPACE_SIZE. For a 4 KB page size, level 0 supports virtual
  28  * address spaces of widths 48 to 40 bits, level 1 from 39 to 31, and level 2
  29  * from 30 to 25. Wider or narrower address spaces are not supported. As a
  30  * result, level 3 cannot be used as initial lookup level with 4 KB
  31  * granularity. [2]
  32  *
  33  * For example, for a 35-bit address space (i.e. PLAT_VIRT_ADDR_SPACE_SIZE ==
  34  * 1 << 35), TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table
  35  * D4-11 in the ARM ARM, the initial lookup level for an address space like
  36  * that is 1.
  37  *
  38  * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
  39  * information:
  40  * [1] Page 1730: 'Input address size', 'For all translation stages'.
  41  * [2] Section D4.2.5
  42  */
  43
  44 #if PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN))
  45
  46 # error "PLAT_VIRT_ADDR_SPACE_SIZE is too big."
  47
  48 #elif PLAT_VIRT_ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT)
  49
  50 # define XLAT_TABLE_LEVEL_BASE  0
  51 # define NUM_BASE_LEVEL_ENTRIES \
  52                 (PLAT_VIRT_ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT)
  53
  54 #elif PLAT_VIRT_ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT)
  55
  56 # define XLAT_TABLE_LEVEL_BASE  1
  57 # define NUM_BASE_LEVEL_ENTRIES \
  58                 (PLAT_VIRT_ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
  59
  60 #elif PLAT_VIRT_ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX))
  61
  62 # define XLAT_TABLE_LEVEL_BASE  2
  63 # define NUM_BASE_LEVEL_ENTRIES \
  64                 (PLAT_VIRT_ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT)
  65
  66 #else
  67
  68 # error "PLAT_VIRT_ADDR_SPACE_SIZE is too small."
  69
  70 #endif
  71
  72 static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES]
  73                 __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
  74
  75 static unsigned long long tcr_ps_bits;
  76
  77 static unsigned long long calc_physical_addr_size_bits(
  78                                         unsigned long long max_addr)
  79 {
  80         /* Physical address can't exceed 48 bits */
  81         assert((max_addr & ADDR_MASK_48_TO_63) == 0);
  82
  83         /* 48 bits address */
  84         if (max_addr & ADDR_MASK_44_TO_47)
  85                 return TCR_PS_BITS_256TB;
  86
  87         /* 44 bits address */
  88         if (max_addr & ADDR_MASK_42_TO_43)
  89                 return TCR_PS_BITS_16TB;
  90
  91         /* 42 bits address */
  92         if (max_addr & ADDR_MASK_40_TO_41)
  93                 return TCR_PS_BITS_4TB;
  94
  95         /* 40 bits address */
  96         if (max_addr & ADDR_MASK_36_TO_39)
  97                 return TCR_PS_BITS_1TB;
  98
  99         /* 36 bits address */
 100         if (max_addr & ADDR_MASK_32_TO_35)
 101                 return TCR_PS_BITS_64GB;
 102
 103         return TCR_PS_BITS_4GB;
 104 }
 105
 106 #if ENABLE_ASSERTIONS
 107 /* Physical Address ranges supported in the AArch64 Memory Model */
 108 static const unsigned int pa_range_bits_arr[] = {
 109         PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100,
 110         PARANGE_0101
 111 };
 112
 113 static unsigned long long get_max_supported_pa(void)
 114 {
 115         u_register_t pa_range = read_id_aa64mmfr0_el1() &
 116                                                 ID_AA64MMFR0_EL1_PARANGE_MASK;
 117
 118         /* All other values are reserved */
 119         assert(pa_range < ARRAY_SIZE(pa_range_bits_arr));
 120
 121         return (1ULL << pa_range_bits_arr[pa_range]) - 1ULL;
 122 }
 123 #endif /* ENABLE_ASSERTIONS */
 124
 125 int xlat_arch_current_el(void)
 126 {
 127         int el = GET_EL(read_CurrentEl());
 128
 129         assert(el > 0);
 130
 131         return el;
 132 }
 133
 134 uint64_t xlat_arch_get_xn_desc(int el)
 135 {
 136         if (el == 3) {
 137                 return UPPER_ATTRS(XN);
 138         } else {
 139                 assert(el == 1);
 140                 return UPPER_ATTRS(PXN);
 141         }
 142 }
 143
 144 void init_xlat_tables(void)
 145 {
 146         unsigned long long max_pa;
 147         uintptr_t max_va;
 148         print_mmap();
 149         init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE,
 150                            &max_va, &max_pa);
 151
 152         assert(max_va <= PLAT_VIRT_ADDR_SPACE_SIZE - 1);
 153         assert(max_pa <= PLAT_PHY_ADDR_SPACE_SIZE - 1);
 154         assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= get_max_supported_pa());
 155
 156         tcr_ps_bits = calc_physical_addr_size_bits(max_pa);
 157 }
 158
 159 /*******************************************************************************
 160  * Macro generating the code for the function enabling the MMU in the given
 161  * exception level, assuming that the pagetables have already been created.
 162  *
 163  *   _el:               Exception level at which the function will run
 164  *   _tcr_extra:        Extra bits to set in the TCR register. This mask will
 165  *                      be OR'ed with the default TCR value.
 166  *   _tlbi_fct:         Function to invalidate the TLBs at the current
 167  *                      exception level
 168  ******************************************************************************/
 169 #define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct)                \
 170         void enable_mmu_el##_el(unsigned int flags)                             \
 171         {                                                               \
 172                 uint64_t mair, tcr, ttbr;                               \
 173                 uint32_t sctlr;                                         \
 174                                                                         \
 175                 assert(IS_IN_EL(_el));                                  \
 176                 assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0);      \
 177                                                                         \
 178                 /* Set attributes in the right indices of the MAIR */   \
 179                 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);   \
 180                 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,             \
 181                                 ATTR_IWBWA_OWBWA_NTR_INDEX);            \
 182                 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE,               \
 183                                 ATTR_NON_CACHEABLE_INDEX);              \
 184                 write_mair_el##_el(mair);                               \
 185                                                                         \
 186                 /* Invalidate TLBs at the current exception level */    \
 187                 _tlbi_fct();                                            \
 188                                                                         \
 189                 /* Set TCR bits as well. */                             \
 190                 /* Set T0SZ to (64 - width of virtual address space) */ \
 191                 if (flags & XLAT_TABLE_NC) {                            \
 192                         /* Inner & outer non-cacheable non-shareable. */\
 193                         tcr = TCR_SH_NON_SHAREABLE |                    \
 194                                 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC |   \
 195                                 (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
 196                 } else {                                                \
 197                         /* Inner & outer WBWA & shareable. */           \
 198                         tcr = TCR_SH_INNER_SHAREABLE |                  \
 199                                 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
 200                                 (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
 201                 }                                                       \
 202                 tcr |= _tcr_extra;                                      \
 203                 write_tcr_el##_el(tcr);                                 \
 204                                                                         \
 205                 /* Set TTBR bits as well */                             \
 206                 ttbr = (uint64_t) base_xlation_table;                   \
 207                 write_ttbr0_el##_el(ttbr);                              \
 208                                                                         \
 209                 /* Ensure all translation table writes have drained */  \
 210                 /* into memory, the TLB invalidation is complete, */    \
 211                 /* and translation register writes are committed */     \
 212                 /* before enabling the MMU */                           \
 213                 dsbish();                                               \
 214                 isb();                                                  \
 215                                                                         \
 216                 sctlr = read_sctlr_el##_el();                           \
 217                 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT;                   \
 218                                                                         \
 219                 if (flags & DISABLE_DCACHE)                             \
 220                         sctlr &= ~SCTLR_C_BIT;                          \
 221                 else                                                    \
 222                         sctlr |= SCTLR_C_BIT;                           \
 223                                                                         \
 224                 write_sctlr_el##_el(sctlr);                             \
 225                                                                         \
 226                 /* Ensure the MMU enable takes effect immediately */    \
 227                 isb();                                                  \
 228         }
 229
 230 /* Define EL1 and EL3 variants of the function enabling the MMU */
 231 DEFINE_ENABLE_MMU_EL(1,
 232                 (tcr_ps_bits << TCR_EL1_IPS_SHIFT),
 233                 tlbivmalle1)
 234 DEFINE_ENABLE_MMU_EL(3,
 235                 TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT),
 236                 tlbialle3)