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Merge pull request #13 from dangowrt/master
[feed/telephony.git] / libs / dahdi-linux / patches / 100-add-support-for-hfc-s-pci.patch
1 Index: dahdi-linux-2.10.0.1/drivers/dahdi/Kbuild
2 ===================================================================
3 --- dahdi-linux-2.10.0.1.orig/drivers/dahdi/Kbuild
4 +++ dahdi-linux-2.10.0.1/drivers/dahdi/Kbuild
5 @@ -13,6 +13,7 @@ obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_WCT
6 obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_WCTDM24XXP) += wctdm24xxp/
7 obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_WCTE12XP) += wcte12xp/
8 obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_WCTE13XP) += wcte13xp.o
9 +obj-$(DAHDI_BUILD_ALL)$(CONFIG_DAHDI_HFCS) += hfcs/
10
11 wcte13xp-objs := wcte13xp-base.o wcxb_spi.o wcxb.o wcxb_flash.o
12 CFLAGS_wcte13xp-base.o += -I$(src)/oct612x -I$(src)/oct612x/include -I$(src)/oct612x/octdeviceapi -I$(src)/oct612x/octdeviceapi/oct6100api
13 Index: dahdi-linux-2.10.0.1/drivers/dahdi/Kconfig
14 ===================================================================
15 --- dahdi-linux-2.10.0.1.orig/drivers/dahdi/Kconfig
16 +++ dahdi-linux-2.10.0.1/drivers/dahdi/Kconfig
17 @@ -291,4 +291,14 @@ config DAHDI_WCTE11XP
18
19 If unsure, say Y.
20
21 +config DAHDI_HFCS
22 + tristate "Support for various HFC-S PCI BRI adapters"
23 + depends on DAHDI && PCI
24 + default DAHDI
25 + ---help---
26 + To compile this driver as a module, choose M here: the
27 + module will be called dahdi_hfcs.
28 +
29 + If unsure, say Y.
30 +
31 source "drivers/dahdi/xpp/Kconfig"
32 Index: dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/base.c
33 ===================================================================
34 --- /dev/null
35 +++ dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/base.c
36 @@ -0,0 +1,1742 @@
37 +/*
38 + * dahdi_hfcs.c - Dahdi driver for HFC-S PCI A based ISDN BRI cards
39 + *
40 + * Dahdi rewrite in hardhdlc mode
41 + * Jose A. Deniz <odicha@hotmail.com>
42 + *
43 + * Copyright (C) 2011, Raoul Bönisch
44 + * Copyright (C) 2009, Jose A. Deniz
45 + * Copyright (C) 2006, headissue GmbH; Jens Wilke
46 + * Copyright (C) 2004 Daniele Orlandi
47 + * Copyright (C) 2002, 2003, 2004, Junghanns.NET GmbH
48 + *
49 + * Jens Wilke <jw_vzaphfc@headissue.com>
50 + *
51 + * Original author of this code is
52 + * Daniele "Vihai" Orlandi <daniele@orlandi.com>
53 + *
54 + * Major rewrite of the driver made by
55 + * Klaus-Peter Junghanns <kpj@junghanns.net>
56 + *
57 + * This program is free software and may be modified and
58 + * distributed under the terms of the GNU Public License.
59 + *
60 + * Please read the README file for important infos.
61 + */
62 +
63 +#include <linux/spinlock.h>
64 +#include <linux/init.h>
65 +#include <linux/pci.h>
66 +#include <linux/interrupt.h>
67 +#include <linux/module.h>
68 +#include <linux/moduleparam.h>
69 +#include <linux/version.h>
70 +#include <linux/kernel.h>
71 +#include <linux/delay.h>
72 +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32))
73 +#include <linux/sched.h>
74 +#endif
75 +#include <linux/proc_fs.h>
76 +#include <linux/if_arp.h>
77 +
78 +#include <dahdi/kernel.h>
79 +
80 +#include "dahdi_hfcs.h"
81 +#include "fifo.h"
82 +
83 +#if CONFIG_PCI
84 +
85 +#define DAHDI_B1 0
86 +#define DAHDI_B2 1
87 +#define DAHDI_D 2
88 +
89 +#define D 0
90 +#define B1 1
91 +#define B2 2
92 +
93 +/*
94 + * Mode Te for all
95 + */
96 +static int modes;
97 +static int nt_modes[hfc_MAX_BOARDS];
98 +static int nt_modes_count;
99 +static int force_l1_up;
100 +static struct proc_dir_entry *hfc_proc_dahdi_hfcs_dir;
101 +
102 +#define DEBUG
103 +#ifdef DEBUG
104 +int debug_level;
105 +#endif
106 +
107 +#ifndef FALSE
108 +#define FALSE 0
109 +#endif
110 +#ifndef TRUE
111 +#define TRUE (!FALSE)
112 +#endif
113 +
114 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
115 +#define SET_PROC_DIRENTRY_OWNER(p) do { (p)->owner = THIS_MODULE; } while(0);
116 +#else
117 +#define SET_PROC_DIRENTRY_OWNER(p) do { } while(0);
118 +#endif
119 +
120 +static DEFINE_PCI_DEVICE_TABLE(hfc_pci_ids) = {
121 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0,
122 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000,
124 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006,
126 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007,
128 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008,
130 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009,
132 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A,
134 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B,
136 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C,
138 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 + {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100,
140 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 + {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1,
142 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 + {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675,
144 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 + {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT,
146 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 + {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T,
148 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 + {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575,
150 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 + {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0,
152 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 + {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,
154 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 + {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,
156 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 + {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,
158 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 + {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,
160 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 + {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_3069,
162 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 + {0,}
164 +};
165 +
166 +MODULE_DEVICE_TABLE(pci, hfc_pci_ids);
167 +
168 +static int __devinit hfc_probe(struct pci_dev *dev
169 + , const struct pci_device_id *ent);
170 +static void __devexit hfc_remove(struct pci_dev *dev);
171 +
172 +static struct pci_driver hfc_driver = {
173 + .name = hfc_DRIVER_NAME,
174 + .id_table = hfc_pci_ids,
175 + .probe = hfc_probe,
176 + .remove = __devexit_p(hfc_remove),
177 +};
178 +
179 +/******************************************
180 + * HW routines
181 + ******************************************/
182 +
183 +static void hfc_softreset(struct hfc_card *card)
184 +{
185 + printk(KERN_INFO hfc_DRIVER_PREFIX
186 + "card %d: "
187 + "resetting\n",
188 + card->cardnum);
189 +
190 +/*
191 + * Softreset procedure. Put it on, wait and off again
192 + */
193 + hfc_outb(card, hfc_CIRM, hfc_CIRM_RESET);
194 + udelay(6);
195 + hfc_outb(card, hfc_CIRM, 0);
196 +
197 + set_current_state(TASK_UNINTERRUPTIBLE);
198 + schedule_timeout((hfc_RESET_DELAY * HZ) / 1000);
199 +}
200 +
201 +static void hfc_resetCard(struct hfc_card *card)
202 +{
203 + card->regs.m1 = 0;
204 + hfc_outb(card, hfc_INT_M1, card->regs.m1);
205 +
206 + card->regs.m2 = 0;
207 + hfc_outb(card, hfc_INT_M2, card->regs.m2);
208 +
209 + hfc_softreset(card);
210 +
211 + card->regs.trm = 0;
212 + hfc_outb(card, hfc_TRM, card->regs.trm);
213 +
214 + /*
215 + * Select the non-capacitive line mode for the S/T interface
216 + */
217 + card->regs.sctrl = hfc_SCTRL_NONE_CAP;
218 +
219 + if (card->nt_mode) {
220 + /*
221 + * ST-Bit delay for NT-Mode
222 + */
223 + hfc_outb(card, hfc_CLKDEL, hfc_CLKDEL_NT);
224 +
225 + card->regs.sctrl |= hfc_SCTRL_MODE_NT;
226 + } else {
227 + /*
228 + * ST-Bit delay for TE-Mode
229 + */
230 + hfc_outb(card, hfc_CLKDEL, hfc_CLKDEL_TE);
231 +
232 + card->regs.sctrl |= hfc_SCTRL_MODE_TE;
233 + }
234 +
235 + hfc_outb(card, hfc_SCTRL, card->regs.sctrl);
236 +
237 + /*
238 + * S/T Auto awake
239 + */
240 + card->regs.sctrl_e = hfc_SCTRL_E_AUTO_AWAKE;
241 + hfc_outb(card, hfc_SCTRL_E, card->regs.sctrl_e);
242 +
243 + /*
244 + * No B-channel enabled at startup
245 + */
246 + card->regs.sctrl_r = 0;
247 + hfc_outb(card, hfc_SCTRL_R, card->regs.sctrl_r);
248 +
249 + /*
250 + * HFC Master Mode
251 + */
252 + hfc_outb(card, hfc_MST_MODE, hfc_MST_MODE_MASTER);
253 +
254 + /*
255 + * Connect internal blocks
256 + */
257 + card->regs.connect =
258 + hfc_CONNECT_B1_HFC_from_ST |
259 + hfc_CONNECT_B1_ST_from_HFC |
260 + hfc_CONNECT_B1_GCI_from_HFC |
261 + hfc_CONNECT_B2_HFC_from_ST |
262 + hfc_CONNECT_B2_ST_from_HFC |
263 + hfc_CONNECT_B2_GCI_from_HFC;
264 + hfc_outb(card, hfc_CONNECT, card->regs.connect);
265 +
266 + /*
267 + * All bchans are HDLC by default, not useful, actually
268 + * since mode is set during open()
269 + */
270 + hfc_outb(card, hfc_CTMT, 0);
271 +
272 + /*
273 + * bit order
274 + */
275 + hfc_outb(card, hfc_CIRM, 0);
276 +
277 + /*
278 + * Enable D-rx FIFO. At least one FIFO must be enabled (by specs)
279 + */
280 + card->regs.fifo_en = hfc_FIFOEN_DRX;
281 + hfc_outb(card, hfc_FIFO_EN, card->regs.fifo_en);
282 +
283 + card->late_irqs = 0;
284 +
285 + /*
286 + * Clear already pending ints
287 + */
288 + hfc_inb(card, hfc_INT_S1);
289 + hfc_inb(card, hfc_INT_S2);
290 +
291 + /*
292 + * Enable IRQ output
293 + */
294 + card->regs.m1 = hfc_INTS_DREC | hfc_INTS_L1STATE | hfc_INTS_TIMER;
295 + hfc_outb(card, hfc_INT_M1, card->regs.m1);
296 +
297 + card->regs.m2 = hfc_M2_IRQ_ENABLE;
298 + hfc_outb(card, hfc_INT_M2, card->regs.m2);
299 +
300 + /*
301 + * Unlocks the states machine
302 + */
303 + hfc_outb(card, hfc_STATES, 0);
304 +
305 + /*
306 + * There's no need to explicitly activate L1 now.
307 + * Activation is managed inside the interrupt routine.
308 + */
309 +}
310 +
311 +static void hfc_update_fifo_state(struct hfc_card *card)
312 +{
313 + /*
314 + * I'm not sure if irqsave is needed but there could be a race
315 + * condition since hfc_update_fifo_state could be called from
316 + * both the IRQ handler and the *_(open|close) functions
317 + */
318 +
319 + unsigned long flags;
320 + spin_lock_irqsave(&card->chans[B1].lock, flags);
321 + if (!card->fifo_suspended &&
322 + (card->chans[B1].status == open_framed ||
323 + card->chans[B1].status == open_voice)) {
324 +
325 + if (!(card->regs.fifo_en & hfc_FIFOEN_B1RX)) {
326 + card->regs.fifo_en |= hfc_FIFOEN_B1RX;
327 + hfc_clear_fifo_rx(&card->chans[B1].rx);
328 + }
329 +
330 + if (!(card->regs.fifo_en & hfc_FIFOEN_B1TX)) {
331 + card->regs.fifo_en |= hfc_FIFOEN_B1TX;
332 + hfc_clear_fifo_tx(&card->chans[B1].tx);
333 + }
334 + } else {
335 + if (card->regs.fifo_en & hfc_FIFOEN_B1RX)
336 + card->regs.fifo_en &= ~hfc_FIFOEN_B1RX;
337 + if (card->regs.fifo_en & hfc_FIFOEN_B1TX)
338 + card->regs.fifo_en &= ~hfc_FIFOEN_B1TX;
339 + }
340 + spin_unlock_irqrestore(&card->chans[B1].lock, flags);
341 +
342 + spin_lock_irqsave(&card->chans[B2].lock, flags);
343 + if (!card->fifo_suspended &&
344 + (card->chans[B2].status == open_framed ||
345 + card->chans[B2].status == open_voice ||
346 + card->chans[B2].status == sniff_aux)) {
347 +
348 + if (!(card->regs.fifo_en & hfc_FIFOEN_B2RX)) {
349 + card->regs.fifo_en |= hfc_FIFOEN_B2RX;
350 + hfc_clear_fifo_rx(&card->chans[B2].rx);
351 + }
352 +
353 + if (!(card->regs.fifo_en & hfc_FIFOEN_B2TX)) {
354 + card->regs.fifo_en |= hfc_FIFOEN_B2TX;
355 + hfc_clear_fifo_tx(&card->chans[B2].tx);
356 + }
357 + } else {
358 + if (card->regs.fifo_en & hfc_FIFOEN_B2RX)
359 + card->regs.fifo_en &= ~hfc_FIFOEN_B2RX;
360 + if (card->regs.fifo_en & hfc_FIFOEN_B2TX)
361 + card->regs.fifo_en &= ~hfc_FIFOEN_B2TX;
362 + }
363 + spin_unlock_irqrestore(&card->chans[B2].lock, flags);
364 +
365 + spin_lock_irqsave(&card->chans[D].lock, flags);
366 + if (!card->fifo_suspended &&
367 + card->chans[D].status == open_framed) {
368 +
369 + if (!(card->regs.fifo_en & hfc_FIFOEN_DTX)) {
370 + card->regs.fifo_en |= hfc_FIFOEN_DTX;
371 +
372 + card->chans[D].tx.ugly_framebuf_size = 0;
373 + card->chans[D].tx.ugly_framebuf_off = 0;
374 + }
375 + } else {
376 + if (card->regs.fifo_en & hfc_FIFOEN_DTX)
377 + card->regs.fifo_en &= ~hfc_FIFOEN_DTX;
378 + }
379 + spin_unlock_irqrestore(&card->chans[D].lock, flags);
380 +
381 + hfc_outb(card, hfc_FIFO_EN, card->regs.fifo_en);
382 +}
383 +
384 +static inline void hfc_suspend_fifo(struct hfc_card *card)
385 +{
386 + card->fifo_suspended = TRUE;
387 +
388 + hfc_update_fifo_state(card);
389 +
390 + /*
391 + * When L1 goes down D rx receives garbage; it is nice to
392 + * clear it to avoid a CRC error on reactivation
393 + * udelay is needed because the FIFO deactivation happens
394 + * in 250us
395 + */
396 + udelay(250);
397 + hfc_clear_fifo_rx(&card->chans[D].rx);
398 +
399 +#ifdef DEBUG
400 + if (debug_level >= 3) {
401 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
402 + "card %d: "
403 + "FIFOs suspended\n",
404 + card->cardnum);
405 + }
406 +#endif
407 +}
408 +
409 +static inline void hfc_resume_fifo(struct hfc_card *card)
410 +{
411 + card->fifo_suspended = FALSE;
412 +
413 + hfc_update_fifo_state(card);
414 +
415 +#ifdef DEBUG
416 + if (debug_level >= 3) {
417 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
418 + "card %d: "
419 + "FIFOs resumed\n",
420 + card->cardnum);
421 + }
422 +#endif
423 +}
424 +
425 +static void hfc_check_l1_up(struct hfc_card *card)
426 +{
427 + if ((!card->nt_mode && card->l1_state != 7)
428 + || (card->nt_mode && card->l1_state != 3)) {
429 +
430 + hfc_outb(card, hfc_STATES, hfc_STATES_DO_ACTION |
431 + hfc_STATES_ACTIVATE|
432 + hfc_STATES_NT_G2_G3);
433 +
434 + /*
435 + * 0 because this is quite verbose when an inferface is unconnected, jaw
436 + */
437 +#if 0
438 + if (debug_level >= 1) {
439 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
440 + "card %d: "
441 + "L1 is down, bringing up L1.\n",
442 + card->cardnum);
443 + }
444 +#endif
445 + }
446 +}
447 +
448 +
449 +/*******************
450 + * Dahdi interface *
451 + *******************/
452 +
453 +static int hfc_dahdi_open(struct dahdi_chan *dahdi_chan)
454 +{
455 + struct hfc_chan_duplex *chan = dahdi_chan->pvt;
456 + struct hfc_card *card = chan->card;
457 +
458 + spin_lock(&chan->lock);
459 +
460 + switch (chan->number) {
461 + case D:
462 + if (chan->status != free &&
463 + chan->status != open_framed) {
464 + spin_unlock(&chan->lock);
465 + return -EBUSY;
466 + }
467 + chan->status = open_framed;
468 + break;
469 +
470 + case B1:
471 + case B2:
472 + if (chan->status != free) {
473 + spin_unlock(&chan->lock);
474 + return -EBUSY;
475 + }
476 + chan->status = open_voice;
477 + break;
478 + }
479 +
480 + chan->open_by_dahdi = TRUE;
481 + try_module_get(THIS_MODULE);
482 + spin_unlock(&chan->lock);
483 +
484 + switch (chan->number) {
485 + case D:
486 + break;
487 +
488 + case B1:
489 + card->regs.m2 |= hfc_M2_PROC_TRANS;
490 + /*
491 + * Enable transparent mode
492 + */
493 + card->regs.ctmt |= hfc_CTMT_TRANSB1;
494 + /*
495 + * Reversed bit order
496 + */
497 + card->regs.cirm |= hfc_CIRM_B1_REV;
498 + /*
499 + * Enable transmission
500 + */
501 + card->regs.sctrl |= hfc_SCTRL_B1_ENA;
502 + /*
503 + * Enable reception
504 + */
505 + card->regs.sctrl_r |= hfc_SCTRL_R_B1_ENA;
506 + break;
507 +
508 + case B2:
509 + card->regs.m2 |= hfc_M2_PROC_TRANS;
510 + card->regs.ctmt |= hfc_CTMT_TRANSB2;
511 + card->regs.cirm |= hfc_CIRM_B2_REV;
512 + card->regs.sctrl |= hfc_SCTRL_B2_ENA;
513 + card->regs.sctrl_r |= hfc_SCTRL_R_B2_ENA;
514 + break;
515 +
516 + }
517 +
518 + /*
519 + * If not already enabled, enable processing transition (8KHz)
520 + * interrupt
521 + */
522 + hfc_outb(card, hfc_INT_M2, card->regs.m2);
523 + hfc_outb(card, hfc_CTMT, card->regs.ctmt);
524 + hfc_outb(card, hfc_CIRM, card->regs.cirm);
525 + hfc_outb(card, hfc_SCTRL, card->regs.sctrl);
526 + hfc_outb(card, hfc_SCTRL_R, card->regs.sctrl_r);
527 +
528 + hfc_update_fifo_state(card);
529 +
530 + printk(KERN_INFO hfc_DRIVER_PREFIX
531 + "card %d: "
532 + "chan %s opened as %s.\n",
533 + card->cardnum,
534 + chan->name,
535 + dahdi_chan->name);
536 +
537 + return 0;
538 +}
539 +
540 +static int hfc_dahdi_close(struct dahdi_chan *dahdi_chan)
541 +{
542 + struct hfc_chan_duplex *chan = dahdi_chan->pvt;
543 + struct hfc_card *card = chan->card;
544 +
545 + if (!card) {
546 + printk(KERN_CRIT hfc_DRIVER_PREFIX
547 + "hfc_dahdi_close called with NULL card\n");
548 + return -1;
549 + }
550 +
551 + spin_lock(&chan->lock);
552 +
553 + if (chan->status == free) {
554 + spin_unlock(&chan->lock);
555 + return -EINVAL;
556 + }
557 +
558 + chan->status = free;
559 + chan->open_by_dahdi = FALSE;
560 +
561 + spin_unlock(&chan->lock);
562 +
563 + switch (chan->number) {
564 + case D:
565 + break;
566 +
567 + case B1:
568 + card->regs.ctmt &= ~hfc_CTMT_TRANSB1;
569 + card->regs.cirm &= ~hfc_CIRM_B1_REV;
570 + card->regs.sctrl &= ~hfc_SCTRL_B1_ENA;
571 + card->regs.sctrl_r &= ~hfc_SCTRL_R_B1_ENA;
572 + break;
573 +
574 + case B2:
575 + card->regs.ctmt &= ~hfc_CTMT_TRANSB2;
576 + card->regs.cirm &= ~hfc_CIRM_B2_REV;
577 + card->regs.sctrl &= ~hfc_SCTRL_B2_ENA;
578 + card->regs.sctrl_r &= ~hfc_SCTRL_R_B2_ENA;
579 + break;
580 + }
581 +
582 + if (card->chans[B1].status == free &&
583 + card->chans[B2].status == free)
584 + card->regs.m2 &= ~hfc_M2_PROC_TRANS;
585 +
586 + hfc_outb(card, hfc_INT_M2, card->regs.m2);
587 + hfc_outb(card, hfc_CTMT, card->regs.ctmt);
588 + hfc_outb(card, hfc_CIRM, card->regs.cirm);
589 + hfc_outb(card, hfc_SCTRL, card->regs.sctrl);
590 + hfc_outb(card, hfc_SCTRL_R, card->regs.sctrl_r);
591 +
592 + hfc_update_fifo_state(card);
593 +
594 + module_put(THIS_MODULE);
595 +
596 + printk(KERN_INFO hfc_DRIVER_PREFIX
597 + "card %d: "
598 + "chan %s closed as %s.\n",
599 + card->cardnum,
600 + chan->name,
601 + dahdi_chan->name);
602 +
603 + return 0;
604 +}
605 +
606 +static int hfc_dahdi_rbsbits(struct dahdi_chan *chan, int bits)
607 +{
608 + return 0;
609 +}
610 +
611 +static int hfc_dahdi_ioctl(struct dahdi_chan *chan,
612 + unsigned int cmd, unsigned long data)
613 +{
614 + switch (cmd) {
615 +
616 + default:
617 + return -ENOTTY;
618 + }
619 +
620 + return 0;
621 +}
622 +
623 +static void hfc_hdlc_hard_xmit(struct dahdi_chan *d_chan)
624 +{
625 + struct hfc_chan_duplex *chan = d_chan->pvt;
626 + struct hfc_card *card = chan->card;
627 + struct dahdi_hfc *hfccard = card->dahdi_dev;
628 +
629 + atomic_inc(&hfccard->hdlc_pending);
630 +
631 +}
632 +
633 +static int hfc_dahdi_startup(struct file *file, struct dahdi_span *span)
634 +{
635 + struct dahdi_hfc *dahdi_hfcs = dahdi_hfc_from_span(span);
636 + struct hfc_card *hfctmp = dahdi_hfcs->card;
637 + int alreadyrunning;
638 +
639 + if (!hfctmp) {
640 + printk(KERN_INFO hfc_DRIVER_PREFIX
641 + "card %d: "
642 + "no card for span at startup!\n",
643 + hfctmp->cardnum);
644 + }
645 +
646 + alreadyrunning = span->flags & DAHDI_FLAG_RUNNING;
647 +
648 + if (!alreadyrunning)
649 + span->flags |= DAHDI_FLAG_RUNNING;
650 +
651 + return 0;
652 +}
653 +
654 +static int hfc_dahdi_shutdown(struct dahdi_span *span)
655 +{
656 + return 0;
657 +}
658 +
659 +static int hfc_dahdi_maint(struct dahdi_span *span, int cmd)
660 +{
661 + return 0;
662 +}
663 +
664 +static int hfc_dahdi_chanconfig(struct file *file, struct dahdi_chan *d_chan, int sigtype)
665 +{
666 + struct hfc_chan_duplex *chan = d_chan->pvt;
667 + struct hfc_card *card = chan->card;
668 + struct dahdi_hfc *hfccard = card->dahdi_dev;
669 +
670 + if ((sigtype == DAHDI_SIG_HARDHDLC) && (hfccard->sigchan == d_chan)) {
671 + hfccard->sigactive = 0;
672 + atomic_set(&hfccard->hdlc_pending, 0);
673 + }
674 +
675 + return 0;
676 +}
677 +
678 +static int hfc_dahdi_spanconfig(struct file *file, struct dahdi_span *span,
679 + struct dahdi_lineconfig *lc)
680 +{
681 + span->lineconfig = lc->lineconfig;
682 +
683 + return 0;
684 +}
685 +
686 +static const struct dahdi_span_ops hfc_dahdi_span_ops = {
687 + .owner = THIS_MODULE,
688 + .chanconfig = hfc_dahdi_chanconfig,
689 + .spanconfig = hfc_dahdi_spanconfig,
690 + .startup = hfc_dahdi_startup,
691 + .shutdown = hfc_dahdi_shutdown,
692 + .maint = hfc_dahdi_maint,
693 + .rbsbits = hfc_dahdi_rbsbits,
694 + .open = hfc_dahdi_open,
695 + .close = hfc_dahdi_close,
696 + .ioctl = hfc_dahdi_ioctl,
697 + .hdlc_hard_xmit = hfc_hdlc_hard_xmit
698 +};
699 +
700 +static int hfc_dahdi_initialize(struct dahdi_hfc *hfccard)
701 +{
702 + struct hfc_card *hfctmp = hfccard->card;
703 + int i;
704 +
705 + hfccard->ddev = dahdi_create_device();
706 + if (!hfccard->ddev)
707 + return -ENOMEM;
708 +
709 + memset(&hfccard->span, 0x0, sizeof(struct dahdi_span));
710 +
711 + /*
712 + * ZTHFC
713 + *
714 + * Cards' and channels' names shall contain "ZTHFC"
715 + * as the dahdi-tools look for this string to guess framing.
716 + * We don't want to modify dahdi-tools only in order to change this.
717 + *
718 + * So we choose for a span name: DAHDI HFC-S formerly known as ZTHFC. :-)
719 + */
720 +
721 + sprintf(hfccard->span.name, "DAHDI_HFCS_FKA_ZTHFC%d", hfctmp->cardnum + 1);
722 + sprintf(hfccard->span.desc,
723 + "HFC-S PCI A ISDN card %d [%s] ",
724 + hfctmp->cardnum,
725 + hfctmp->nt_mode ? "NT" : "TE");
726 + hfccard->span.spantype = hfctmp->nt_mode ? SPANTYPE_DIGITAL_BRI_NT :
727 + SPANTYPE_DIGITAL_BRI_TE;
728 + hfccard->ddev->manufacturer = "Cologne Chips";
729 + hfccard->span.flags = 0;
730 + hfccard->span.ops = &hfc_dahdi_span_ops;
731 + hfccard->ddev->devicetype = kasprintf(GFP_KERNEL, "HFC-S PCI-A ISDN");
732 + hfccard->ddev->location = kasprintf(GFP_KERNEL, "PCI Bus %02d Slot %02d",
733 + hfctmp->pcidev->bus->number,
734 + PCI_SLOT(hfctmp->pcidev->devfn) + 1);
735 + hfccard->span.chans = hfccard->_chans;
736 + hfccard->span.channels = 3;
737 + for (i = 0; i < hfccard->span.channels; i++)
738 + hfccard->_chans[i] = &hfccard->chans[i];
739 + hfccard->span.deflaw = DAHDI_LAW_ALAW;
740 + hfccard->span.linecompat = DAHDI_CONFIG_AMI | DAHDI_CONFIG_CCS;
741 + hfccard->span.offset = 0;
742 +
743 + for (i = 0; i < hfccard->span.channels; i++) {
744 + memset(&hfccard->chans[i], 0x0, sizeof(struct dahdi_chan));
745 +
746 + sprintf(hfccard->chans[i].name,
747 + "DAHDI_HFCS_FKA_ZTHFC%d/%d/%d",
748 + hfctmp->cardnum + 1, 0, i + 1);
749 +
750 + printk(KERN_INFO hfc_DRIVER_PREFIX
751 + "card %d: "
752 + "registered %s\n",
753 + hfctmp->cardnum,
754 + hfccard->chans[i].name);
755 +
756 + if (i == hfccard->span.channels - 1) {
757 + hfccard->chans[i].sigcap = DAHDI_SIG_HARDHDLC;
758 + hfccard->sigchan = &hfccard->chans[DAHDI_D];
759 + hfccard->sigactive = 0;
760 + atomic_set(&hfccard->hdlc_pending, 0);
761 + } else {
762 + hfccard->chans[i].sigcap =
763 + DAHDI_SIG_CLEAR | DAHDI_SIG_DACS;
764 + }
765 +
766 + hfccard->chans[i].chanpos = i + 1;
767 + }
768 +
769 + hfccard->chans[DAHDI_D].readchunk =
770 + hfctmp->chans[D].rx.dahdi_buffer;
771 +
772 + hfccard->chans[DAHDI_D].writechunk =
773 + hfctmp->chans[D].tx.dahdi_buffer;
774 +
775 + hfccard->chans[DAHDI_D].pvt = &hfctmp->chans[D];
776 +
777 + hfccard->chans[DAHDI_B1].readchunk =
778 + hfctmp->chans[B1].rx.dahdi_buffer;
779 +
780 + hfccard->chans[DAHDI_B1].writechunk =
781 + hfctmp->chans[B1].tx.dahdi_buffer;
782 +
783 + hfccard->chans[DAHDI_B1].pvt = &hfctmp->chans[B1];
784 +
785 + hfccard->chans[DAHDI_B2].readchunk =
786 + hfctmp->chans[B2].rx.dahdi_buffer;
787 +
788 + hfccard->chans[DAHDI_B2].writechunk =
789 + hfctmp->chans[B2].tx.dahdi_buffer;
790 +
791 + hfccard->chans[DAHDI_B2].pvt = &hfctmp->chans[B2];
792 +
793 + list_add_tail(&hfccard->span.device_node, &hfccard->ddev->spans);
794 + if (dahdi_register_device(hfccard->ddev, &hfccard->card->pcidev->dev)) {
795 + printk(KERN_NOTICE "Unable to register device with DAHDI\n");
796 + return -1;
797 + }
798 +
799 + return 0;
800 +}
801 +
802 +static void hfc_dahdi_transmit(struct hfc_chan_simplex *chan)
803 +{
804 + hfc_fifo_put(chan, chan->dahdi_buffer, DAHDI_CHUNKSIZE);
805 +}
806 +
807 +static void hfc_dahdi_receive(struct hfc_chan_simplex *chan)
808 +{
809 + hfc_fifo_get(chan, chan->dahdi_buffer, DAHDI_CHUNKSIZE);
810 +}
811 +
812 +/******************************************
813 + * Interrupt Handler
814 + ******************************************/
815 +
816 +static void hfc_handle_timer_interrupt(struct hfc_card *card);
817 +static void hfc_handle_state_interrupt(struct hfc_card *card);
818 +static void hfc_handle_processing_interrupt(struct hfc_card *card);
819 +static void hfc_frame_arrived(struct hfc_chan_duplex *chan);
820 +static void hfc_handle_voice(struct hfc_card *card);
821 +
822 +#if (KERNEL_VERSION(2, 6, 24) < LINUX_VERSION_CODE)
823 +static irqreturn_t hfc_interrupt(int irq, void *dev_id)
824 +#else
825 +static irqreturn_t hfc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
826 +#endif
827 +{
828 + struct hfc_card *card = dev_id;
829 + unsigned long flags;
830 + u8 status, s1, s2;
831 +
832 + if (!card) {
833 + printk(KERN_CRIT hfc_DRIVER_PREFIX
834 + "spurious interrupt (IRQ %d)\n",
835 + irq);
836 + return IRQ_NONE;
837 + }
838 +
839 + spin_lock_irqsave(&card->lock, flags);
840 + status = hfc_inb(card, hfc_STATUS);
841 + if (!(status & hfc_STATUS_ANYINT)) {
842 + /*
843 + * maybe we are sharing the irq
844 + */
845 + spin_unlock_irqrestore(&card->lock, flags);
846 + return IRQ_NONE;
847 + }
848 +
849 + /* We used to ingore the IRQ when the card was in processing
850 + * state but apparently there is no restriction to access the
851 + * card in such state:
852 + *
853 + * Joerg Ciesielski wrote:
854 + * > There is no restriction for the IRQ handler to access
855 + * > HFC-S PCI during processing phase. A IRQ latency of 375 us
856 + * > is also no problem since there are no interrupt sources in
857 + * > HFC-S PCI which must be handled very fast.
858 + * > Due to its deep fifos the IRQ latency can be several ms with
859 + * > out the risk of loosing data. Even the S/T state interrupts
860 + * > must not be handled with a latency less than <5ms.
861 + * >
862 + * > The processing phase only indicates that HFC-S PCI is
863 + * > processing the Fifos as PCI master so that data is read and
864 + * > written in the 32k memory window. But there is no restriction
865 + * > to access data in the memory window during this time.
866 + *
867 + * // if (status & hfc_STATUS_PCI_PROC) {
868 + * // return IRQ_HANDLED;
869 + * // }
870 + */
871 +
872 + s1 = hfc_inb(card, hfc_INT_S1);
873 + s2 = hfc_inb(card, hfc_INT_S2);
874 +
875 + if (s1 != 0) {
876 + if (s1 & hfc_INTS_TIMER) {
877 + /*
878 + * timer (bit 7)
879 + */
880 + hfc_handle_timer_interrupt(card);
881 + }
882 +
883 + if (s1 & hfc_INTS_L1STATE) {
884 + /*
885 + * state machine (bit 6)
886 + */
887 + hfc_handle_state_interrupt(card);
888 + }
889 +
890 + if (s1 & hfc_INTS_DREC) {
891 + /*
892 + * D chan RX (bit 5)
893 + */
894 + hfc_frame_arrived(&card->chans[D]);
895 + }
896 +
897 + if (s1 & hfc_INTS_B1REC) {
898 + /*
899 + * B1 chan RX (bit 3)
900 + */
901 + hfc_frame_arrived(&card->chans[B1]);
902 + }
903 +
904 + if (s1 & hfc_INTS_B2REC) {
905 + /*
906 + * B2 chan RX (bit 4)
907 + */
908 + hfc_frame_arrived(&card->chans[B2]);
909 + }
910 +
911 + if (s1 & hfc_INTS_DTRANS) {
912 + /*
913 + * D chan TX (bit 2)
914 + */
915 + }
916 +
917 + if (s1 & hfc_INTS_B1TRANS) {
918 + /*
919 + * B1 chan TX (bit 0)
920 + */
921 + }
922 +
923 + if (s1 & hfc_INTS_B2TRANS) {
924 + /*
925 + * B2 chan TX (bit 1)
926 + */
927 + }
928 +
929 + }
930 +
931 + if (s2 != 0) {
932 + if (s2 & hfc_M2_PMESEL) {
933 + /*
934 + * kaboom irq (bit 7)
935 + *
936 + * CologneChip says:
937 + *
938 + * the meaning of this fatal error bit is that HFC-S
939 + * PCI as PCI master could not access the PCI bus
940 + * within 125us to finish its data processing. If this
941 + * happens only very seldom it does not cause big
942 + * problems but of course some B-channel or D-channel
943 + * data will be corrupted due to this event.
944 + *
945 + * Unfortunately this bit is only set once after the
946 + * problem occurs and can only be reseted by a
947 + * software reset. That means it is not easily
948 + * possible to check how often this fatal error
949 + * happens.
950 + *
951 + */
952 +
953 + if (!card->sync_loss_reported) {
954 + printk(KERN_CRIT hfc_DRIVER_PREFIX
955 + "card %d: "
956 + "sync lost, pci performance too low!\n",
957 + card->cardnum);
958 +
959 + card->sync_loss_reported = TRUE;
960 + }
961 + }
962 +
963 + if (s2 & hfc_M2_GCI_MON_REC) {
964 + /*
965 + * RxR monitor channel (bit 2)
966 + */
967 + }
968 +
969 + if (s2 & hfc_M2_GCI_I_CHG) {
970 + /*
971 + * GCI I-change (bit 1)
972 + */
973 + }
974 +
975 + if (s2 & hfc_M2_PROC_TRANS) {
976 + /*
977 + * processing/non-processing transition (bit 0)
978 + */
979 + hfc_handle_processing_interrupt(card);
980 + }
981 +
982 + }
983 +
984 + spin_unlock_irqrestore(&card->lock, flags);
985 +
986 + return IRQ_HANDLED;
987 +}
988 +
989 +static void hfc_handle_timer_interrupt(struct hfc_card *card)
990 +{
991 + if (card->ignore_first_timer_interrupt) {
992 + card->ignore_first_timer_interrupt = FALSE;
993 + return;
994 + }
995 +
996 + if ((card->nt_mode && card->l1_state == 3) ||
997 + (!card->nt_mode && card->l1_state == 7)) {
998 +
999 + card->regs.ctmt &= ~hfc_CTMT_TIMER_MASK;
1000 + hfc_outb(card, hfc_CTMT, card->regs.ctmt);
1001 +
1002 + hfc_resume_fifo(card);
1003 + }
1004 +}
1005 +
1006 +static void hfc_handle_state_interrupt(struct hfc_card *card)
1007 +{
1008 + u8 new_state = hfc_inb(card, hfc_STATES) & hfc_STATES_STATE_MASK;
1009 +
1010 +#ifdef DEBUG
1011 + if (debug_level >= 1) {
1012 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
1013 + "card %d: "
1014 + "layer 1 state = %c%d\n",
1015 + card->cardnum,
1016 + card->nt_mode ? 'G' : 'F',
1017 + new_state);
1018 + }
1019 +#endif
1020 +
1021 + if (card->nt_mode) {
1022 + /*
1023 + * NT mode
1024 + */
1025 +
1026 + if (new_state == 3) {
1027 + /*
1028 + * fix to G3 state (see specs)
1029 + */
1030 + hfc_outb(card, hfc_STATES, hfc_STATES_LOAD_STATE | 3);
1031 + }
1032 +
1033 + if (new_state == 3 && card->l1_state != 3)
1034 + hfc_resume_fifo(card);
1035 +
1036 + if (new_state != 3 && card->l1_state == 3)
1037 + hfc_suspend_fifo(card);
1038 +
1039 + } else {
1040 + if (new_state == 3) {
1041 + /*
1042 + * Keep L1 up... zaptel & libpri expects
1043 + * a always up L1...
1044 + * Enable only when using an unpatched libpri
1045 + *
1046 + * Are we still using unpatched libpri? Is this tested at runtime???
1047 + * Does it only affect zaptel or DAHDI, too?
1048 + */
1049 +
1050 + if (force_l1_up) {
1051 + hfc_outb(card, hfc_STATES,
1052 + hfc_STATES_DO_ACTION |
1053 + hfc_STATES_ACTIVATE|
1054 + hfc_STATES_NT_G2_G3);
1055 + }
1056 + }
1057 +
1058 + if (new_state == 7 && card->l1_state != 7) {
1059 + /*
1060 + * TE is now active, schedule FIFO activation after
1061 + * some time, otherwise the first frames are lost
1062 + */
1063 +
1064 + card->regs.ctmt |= hfc_CTMT_TIMER_50 |
1065 + hfc_CTMT_TIMER_CLEAR;
1066 + hfc_outb(card, hfc_CTMT, card->regs.ctmt);
1067 +
1068 + /*
1069 + * Activating the timer firest an
1070 + * interrupt immediately, we
1071 + * obviously need to ignore it
1072 + */
1073 + card->ignore_first_timer_interrupt = TRUE;
1074 + }
1075 +
1076 + if (new_state != 7 && card->l1_state == 7) {
1077 + /*
1078 + * TE has become inactive, disable FIFO
1079 + */
1080 + hfc_suspend_fifo(card);
1081 + }
1082 + }
1083 +
1084 + card->l1_state = new_state;
1085 +}
1086 +
1087 +static void hfc_handle_processing_interrupt(struct hfc_card *card)
1088 +{
1089 + int available_bytes = 0;
1090 +
1091 + /*
1092 + * Synchronize with the first enabled channel
1093 + */
1094 + if (card->regs.fifo_en & hfc_FIFOEN_B1RX)
1095 + available_bytes = hfc_fifo_used_rx(&card->chans[B1].rx);
1096 + if (card->regs.fifo_en & hfc_FIFOEN_B2RX)
1097 + available_bytes = hfc_fifo_used_rx(&card->chans[B2].rx);
1098 + else
1099 + available_bytes = -1;
1100 +
1101 + if ((available_bytes == -1 && card->ticks == 8) ||
1102 + available_bytes >= DAHDI_CHUNKSIZE + hfc_RX_FIFO_PRELOAD) {
1103 + card->ticks = 0;
1104 +
1105 + if (available_bytes > DAHDI_CHUNKSIZE*2 + hfc_RX_FIFO_PRELOAD) {
1106 + card->late_irqs++;
1107 + /*
1108 + * we are out of sync, clear fifos, jaw
1109 + */
1110 + hfc_clear_fifo_rx(&card->chans[B1].rx);
1111 + hfc_clear_fifo_tx(&card->chans[B1].tx);
1112 + hfc_clear_fifo_rx(&card->chans[B2].rx);
1113 + hfc_clear_fifo_tx(&card->chans[B2].tx);
1114 +
1115 +#ifdef DEBUG
1116 + if (debug_level >= 4) {
1117 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
1118 + "card %d: "
1119 + "late IRQ, %d bytes late\n",
1120 + card->cardnum,
1121 + available_bytes -
1122 + (DAHDI_CHUNKSIZE +
1123 + hfc_RX_FIFO_PRELOAD));
1124 + }
1125 +#endif
1126 + } else {
1127 + hfc_handle_voice(card);
1128 + }
1129 + }
1130 +
1131 + card->ticks++;
1132 +}
1133 +
1134 +
1135 +static void hfc_handle_voice(struct hfc_card *card)
1136 +{
1137 + struct dahdi_hfc *hfccard = card->dahdi_dev;
1138 + int frame_left, res;
1139 + unsigned char buf[hfc_HDLC_BUF_LEN];
1140 + unsigned int size = sizeof(buf) / sizeof(buf[0]);
1141 +
1142 +
1143 + if (card->chans[B1].status != open_voice &&
1144 + card->chans[B2].status != open_voice)
1145 + return;
1146 +
1147 + dahdi_transmit(&hfccard->span);
1148 +
1149 + if (card->regs.fifo_en & hfc_FIFOEN_B1TX)
1150 + hfc_dahdi_transmit(&card->chans[B1].tx);
1151 + if (card->regs.fifo_en & hfc_FIFOEN_B2TX)
1152 + hfc_dahdi_transmit(&card->chans[B2].tx);
1153 +
1154 + /*
1155 + * dahdi hdlc frame tx
1156 + */
1157 +
1158 + if (atomic_read(&hfccard->hdlc_pending)) {
1159 + hfc_check_l1_up(card);
1160 + res = dahdi_hdlc_getbuf(hfccard->sigchan, buf, &size);
1161 + if (size > 0) {
1162 + hfccard->sigactive = 1;
1163 + memcpy(card->chans[D].tx.ugly_framebuf +
1164 + card->chans[D].tx.ugly_framebuf_size,
1165 + buf, size);
1166 + card->chans[D].tx.ugly_framebuf_size += size;
1167 + if (res != 0) {
1168 + hfc_fifo_put_frame(&card->chans[D].tx,
1169 + card->chans[D].tx.ugly_framebuf,
1170 + card->chans[D].tx.ugly_framebuf_size);
1171 + ++hfccard->frames_out;
1172 + hfccard->sigactive = 0;
1173 + card->chans[D].tx.ugly_framebuf_size
1174 + = 0;
1175 + atomic_dec(&hfccard->hdlc_pending);
1176 + }
1177 + }
1178 + }
1179 + /*
1180 + * dahdi hdlc frame tx done
1181 + */
1182 +
1183 + if (card->regs.fifo_en & hfc_FIFOEN_B1RX)
1184 + hfc_dahdi_receive(&card->chans[B1].rx);
1185 + else
1186 + memset(&card->chans[B1].rx.dahdi_buffer, 0x7f,
1187 + sizeof(card->chans[B1].rx.dahdi_buffer));
1188 +
1189 + if (card->regs.fifo_en & hfc_FIFOEN_B2RX)
1190 + hfc_dahdi_receive(&card->chans[B2].rx);
1191 + else
1192 + memset(&card->chans[B2].rx.dahdi_buffer, 0x7f,
1193 + sizeof(card->chans[B1].rx.dahdi_buffer));
1194 +
1195 + /*
1196 + * Echo cancellation
1197 + */
1198 + dahdi_ec_chunk(&hfccard->chans[DAHDI_B1],
1199 + card->chans[B1].rx.dahdi_buffer,
1200 + card->chans[B1].tx.dahdi_buffer);
1201 + dahdi_ec_chunk(&hfccard->chans[DAHDI_B2],
1202 + card->chans[B2].rx.dahdi_buffer,
1203 + card->chans[B2].tx.dahdi_buffer);
1204 +
1205 + /*
1206 + * dahdi hdlc frame rx
1207 + */
1208 + if (hfc_fifo_has_frames(&card->chans[D].rx))
1209 + hfc_frame_arrived(&card->chans[D]);
1210 +
1211 + if (card->chans[D].rx.ugly_framebuf_size) {
1212 + frame_left = card->chans[D].rx.ugly_framebuf_size -
1213 + card->chans[D].rx.ugly_framebuf_off ;
1214 + if (frame_left > hfc_HDLC_BUF_LEN) {
1215 + dahdi_hdlc_putbuf(hfccard->sigchan,
1216 + card->chans[D].rx.ugly_framebuf +
1217 + card->chans[D].rx.ugly_framebuf_off,
1218 + hfc_HDLC_BUF_LEN);
1219 + card->chans[D].rx.ugly_framebuf_off +=
1220 + hfc_HDLC_BUF_LEN;
1221 + } else {
1222 + dahdi_hdlc_putbuf(hfccard->sigchan,
1223 + card->chans[D].rx.ugly_framebuf +
1224 + card->chans[D].rx.ugly_framebuf_off,
1225 + frame_left);
1226 + dahdi_hdlc_finish(hfccard->sigchan);
1227 + card->chans[D].rx.ugly_framebuf_size = 0;
1228 + card->chans[D].rx.ugly_framebuf_off = 0;
1229 + }
1230 + }
1231 + /*
1232 + * dahdi hdlc frame rx done
1233 + */
1234 +
1235 + if (hfccard->span.flags & DAHDI_FLAG_RUNNING)
1236 + dahdi_receive(&hfccard->span);
1237 +
1238 +}
1239 +
1240 +static void hfc_frame_arrived(struct hfc_chan_duplex *chan)
1241 +{
1242 + struct hfc_card *card = chan->card;
1243 + int antiloop = 16;
1244 + struct sk_buff *skb;
1245 +
1246 + while (hfc_fifo_has_frames(&chan->rx) && --antiloop) {
1247 + int frame_size = hfc_fifo_get_frame_size(&chan->rx);
1248 +
1249 + if (frame_size < 3) {
1250 +#ifdef DEBUG
1251 + if (debug_level >= 2)
1252 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
1253 + "card %d: "
1254 + "chan %s: "
1255 + "invalid frame received, "
1256 + "just %d bytes\n",
1257 + card->cardnum,
1258 + chan->name,
1259 + frame_size);
1260 +#endif
1261 +
1262 + hfc_fifo_drop_frame(&chan->rx);
1263 +
1264 +
1265 + continue;
1266 + } else if (frame_size == 3) {
1267 +#ifdef DEBUG
1268 + if (debug_level >= 2)
1269 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
1270 + "card %d: "
1271 + "chan %s: "
1272 + "empty frame received\n",
1273 + card->cardnum,
1274 + chan->name);
1275 +#endif
1276 +
1277 + hfc_fifo_drop_frame(&chan->rx);
1278 +
1279 +
1280 + continue;
1281 + }
1282 +
1283 + if (chan->open_by_dahdi &&
1284 + card->chans[D].rx.ugly_framebuf_size) {
1285 +
1286 + /*
1287 + * We have to wait for Dahdi to transmit the
1288 + * frame... wait for next time
1289 + */
1290 +
1291 + break;
1292 + }
1293 +
1294 + skb = dev_alloc_skb(frame_size - 3);
1295 +
1296 + if (!skb) {
1297 + printk(KERN_ERR hfc_DRIVER_PREFIX
1298 + "card %d: "
1299 + "chan %s: "
1300 + "cannot allocate skb: frame dropped\n",
1301 + card->cardnum,
1302 + chan->name);
1303 +
1304 + hfc_fifo_drop_frame(&chan->rx);
1305 +
1306 +
1307 + continue;
1308 + }
1309 +
1310 +
1311 + /*
1312 + * HFC does the checksum
1313 + */
1314 +#ifndef CHECKSUM_HW
1315 + skb->ip_summed = CHECKSUM_COMPLETE;
1316 +#else
1317 + skb->ip_summed = CHECKSUM_HW;
1318 +#endif
1319 +
1320 + if (chan->open_by_dahdi) {
1321 + card->chans[D].rx.ugly_framebuf_size = frame_size - 1;
1322 +
1323 + if (hfc_fifo_get_frame(&card->chans[D].rx,
1324 + card->chans[D].rx.ugly_framebuf,
1325 + frame_size - 1) == -1) {
1326 + dev_kfree_skb(skb);
1327 + continue;
1328 + }
1329 +
1330 + memcpy(skb_put(skb, frame_size - 3),
1331 + card->chans[D].rx.ugly_framebuf,
1332 + frame_size - 3);
1333 + } else {
1334 + if (hfc_fifo_get_frame(&chan->rx,
1335 + skb_put(skb, frame_size - 3),
1336 + frame_size - 3) == -1) {
1337 + dev_kfree_skb(skb);
1338 + continue;
1339 + }
1340 + }
1341 + }
1342 +
1343 + if (!antiloop)
1344 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1345 + "card %d: "
1346 + "Infinite loop detected\n",
1347 + card->cardnum);
1348 +}
1349 +
1350 +/******************************************
1351 + * Module initialization and cleanup
1352 + ******************************************/
1353 +
1354 +static int __devinit hfc_probe(struct pci_dev *pci_dev,
1355 + const struct pci_device_id *ent)
1356 +{
1357 + static int cardnum;
1358 + int err;
1359 + int i;
1360 +
1361 + struct hfc_card *card = NULL;
1362 + struct dahdi_hfc *dahdi_hfcs = NULL;
1363 + card = kmalloc(sizeof(struct hfc_card), GFP_KERNEL);
1364 + if (!card) {
1365 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1366 + "unable to kmalloc!\n");
1367 + err = -ENOMEM;
1368 + goto err_alloc_hfccard;
1369 + }
1370 +
1371 + memset(card, 0x00, sizeof(struct hfc_card));
1372 + card->cardnum = cardnum;
1373 + card->pcidev = pci_dev;
1374 + spin_lock_init(&card->lock);
1375 +
1376 + pci_set_drvdata(pci_dev, card);
1377 +
1378 + err = pci_enable_device(pci_dev);
1379 + if (err)
1380 + goto err_pci_enable_device;
1381 +
1382 + err = pci_set_dma_mask(pci_dev, PCI_DMA_32BIT);
1383 + if (err) {
1384 + printk(KERN_ERR hfc_DRIVER_PREFIX
1385 + "card %d: "
1386 + "No suitable DMA configuration available.\n",
1387 + card->cardnum);
1388 + goto err_pci_set_dma_mask;
1389 + }
1390 +
1391 + pci_write_config_word(pci_dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
1392 + err = pci_request_regions(pci_dev, hfc_DRIVER_NAME);
1393 + if (err) {
1394 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1395 + "card %d: "
1396 + "cannot request I/O memory region\n",
1397 + card->cardnum);
1398 + goto err_pci_request_regions;
1399 + }
1400 +
1401 + pci_set_master(pci_dev);
1402 +
1403 + if (!pci_dev->irq) {
1404 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1405 + "card %d: "
1406 + "no irq!\n",
1407 + card->cardnum);
1408 + err = -ENODEV;
1409 + goto err_noirq;
1410 + }
1411 +
1412 + card->io_bus_mem = pci_resource_start(pci_dev, 1);
1413 + if (!card->io_bus_mem) {
1414 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1415 + "card %d: "
1416 + "no iomem!\n",
1417 + card->cardnum);
1418 + err = -ENODEV;
1419 + goto err_noiobase;
1420 + }
1421 +
1422 + card->io_mem = ioremap(card->io_bus_mem, hfc_PCI_MEM_SIZE);
1423 + if (!(card->io_mem)) {
1424 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1425 + "card %d: "
1426 + "cannot ioremap I/O memory\n",
1427 + card->cardnum);
1428 + err = -ENODEV;
1429 + goto err_ioremap;
1430 + }
1431 +
1432 + /*
1433 + * pci_alloc_consistent guarantees alignment
1434 + * (Documentation/DMA-mapping.txt)
1435 + */
1436 + card->fifo_mem = pci_alloc_consistent(pci_dev,
1437 + hfc_FIFO_SIZE, &card->fifo_bus_mem);
1438 + if (!card->fifo_mem) {
1439 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1440 + "card %d: "
1441 + "unable to allocate FIFO DMA memory!\n",
1442 + card->cardnum);
1443 + err = -ENOMEM;
1444 + goto err_alloc_fifo;
1445 + }
1446 +
1447 + memset(card->fifo_mem, 0x00, hfc_FIFO_SIZE);
1448 +
1449 + card->fifos = card->fifo_mem;
1450 +
1451 + pci_write_config_dword(card->pcidev, hfc_PCI_MWBA, card->fifo_bus_mem);
1452 +
1453 + err = request_irq(card->pcidev->irq, &hfc_interrupt,
1454 +
1455 +#if (KERNEL_VERSION(2, 6, 23) < LINUX_VERSION_CODE)
1456 + IRQF_SHARED, hfc_DRIVER_NAME, card);
1457 +#else
1458 + SA_SHIRQ, hfc_DRIVER_NAME, card);
1459 +#endif
1460 +
1461 + if (err) {
1462 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1463 + "card %d: "
1464 + "unable to register irq\n",
1465 + card->cardnum);
1466 + goto err_request_irq;
1467 + }
1468 +
1469 + card->nt_mode = FALSE;
1470 +
1471 + if (modes & (1 << card->cardnum))
1472 + card->nt_mode = TRUE;
1473 +
1474 + for (i = 0; i < nt_modes_count; i++) {
1475 + if (nt_modes[i] == card->cardnum)
1476 + card->nt_mode = TRUE;
1477 + }
1478 +
1479 + /*
1480 + * D Channel
1481 + */
1482 + card->chans[D].card = card;
1483 + card->chans[D].name = "D";
1484 + card->chans[D].status = free;
1485 + card->chans[D].number = D;
1486 + spin_lock_init(&card->chans[D].lock);
1487 +
1488 + card->chans[D].rx.chan = &card->chans[D];
1489 + card->chans[D].rx.fifo_base = card->fifos + 0x4000;
1490 + card->chans[D].rx.z_base = card->fifos + 0x4000;
1491 + card->chans[D].rx.z1_base = card->fifos + 0x6080;
1492 + card->chans[D].rx.z2_base = card->fifos + 0x6082;
1493 + card->chans[D].rx.z_min = 0x0000;
1494 + card->chans[D].rx.z_max = 0x01FF;
1495 + card->chans[D].rx.f_min = 0x10;
1496 + card->chans[D].rx.f_max = 0x1F;
1497 + card->chans[D].rx.f1 = card->fifos + 0x60a0;
1498 + card->chans[D].rx.f2 = card->fifos + 0x60a1;
1499 + card->chans[D].rx.fifo_size = card->chans[D].rx.z_max
1500 + - card->chans[D].rx.z_min + 1;
1501 + card->chans[D].rx.f_num = card->chans[D].rx.f_max
1502 + - card->chans[D].rx.f_min + 1;
1503 +
1504 + card->chans[D].tx.chan = &card->chans[D];
1505 + card->chans[D].tx.fifo_base = card->fifos + 0x0000;
1506 + card->chans[D].tx.z_base = card->fifos + 0x0000;
1507 + card->chans[D].tx.z1_base = card->fifos + 0x2080;
1508 + card->chans[D].tx.z2_base = card->fifos + 0x2082;
1509 + card->chans[D].tx.z_min = 0x0000;
1510 + card->chans[D].tx.z_max = 0x01FF;
1511 + card->chans[D].tx.f_min = 0x10;
1512 + card->chans[D].tx.f_max = 0x1F;
1513 + card->chans[D].tx.f1 = card->fifos + 0x20a0;
1514 + card->chans[D].tx.f2 = card->fifos + 0x20a1;
1515 + card->chans[D].tx.fifo_size = card->chans[D].tx.z_max -
1516 + card->chans[D].tx.z_min + 1;
1517 + card->chans[D].tx.f_num = card->chans[D].tx.f_max -
1518 + card->chans[D].tx.f_min + 1;
1519 +
1520 + /*
1521 + * B1 Channel
1522 + */
1523 + card->chans[B1].card = card;
1524 + card->chans[B1].name = "B1";
1525 + card->chans[B1].status = free;
1526 + card->chans[B1].number = B1;
1527 + card->chans[B1].protocol = 0;
1528 + spin_lock_init(&card->chans[B1].lock);
1529 +
1530 + card->chans[B1].rx.chan = &card->chans[B1];
1531 + card->chans[B1].rx.fifo_base = card->fifos + 0x4200;
1532 + card->chans[B1].rx.z_base = card->fifos + 0x4000;
1533 + card->chans[B1].rx.z1_base = card->fifos + 0x6000;
1534 + card->chans[B1].rx.z2_base = card->fifos + 0x6002;
1535 + card->chans[B1].rx.z_min = 0x0200;
1536 + card->chans[B1].rx.z_max = 0x1FFF;
1537 + card->chans[B1].rx.f_min = 0x00;
1538 + card->chans[B1].rx.f_max = 0x1F;
1539 + card->chans[B1].rx.f1 = card->fifos + 0x6080;
1540 + card->chans[B1].rx.f2 = card->fifos + 0x6081;
1541 + card->chans[B1].rx.fifo_size = card->chans[B1].rx.z_max -
1542 + card->chans[B1].rx.z_min + 1;
1543 + card->chans[B1].rx.f_num = card->chans[B1].rx.f_max -
1544 + card->chans[B1].rx.f_min + 1;
1545 +
1546 + card->chans[B1].tx.chan = &card->chans[B1];
1547 + card->chans[B1].tx.fifo_base = card->fifos + 0x0200;
1548 + card->chans[B1].tx.z_base = card->fifos + 0x0000;
1549 + card->chans[B1].tx.z1_base = card->fifos + 0x2000;
1550 + card->chans[B1].tx.z2_base = card->fifos + 0x2002;
1551 + card->chans[B1].tx.z_min = 0x0200;
1552 + card->chans[B1].tx.z_max = 0x1FFF;
1553 + card->chans[B1].tx.f_min = 0x00;
1554 + card->chans[B1].tx.f_max = 0x1F;
1555 + card->chans[B1].tx.f1 = card->fifos + 0x2080;
1556 + card->chans[B1].tx.f2 = card->fifos + 0x2081;
1557 + card->chans[B1].tx.fifo_size = card->chans[B1].tx.z_max -
1558 + card->chans[B1].tx.z_min + 1;
1559 + card->chans[B1].tx.f_num = card->chans[B1].tx.f_max -
1560 + card->chans[B1].tx.f_min + 1;
1561 +
1562 + /*
1563 + * B2 Channel
1564 + */
1565 + card->chans[B2].card = card;
1566 + card->chans[B2].name = "B2";
1567 + card->chans[B2].status = free;
1568 + card->chans[B2].number = B2;
1569 + card->chans[B2].protocol = 0;
1570 + spin_lock_init(&card->chans[B2].lock);
1571 +
1572 + card->chans[B2].rx.chan = &card->chans[B2];
1573 + card->chans[B2].rx.fifo_base = card->fifos + 0x6200,
1574 + card->chans[B2].rx.z_base = card->fifos + 0x6000;
1575 + card->chans[B2].rx.z1_base = card->fifos + 0x6100;
1576 + card->chans[B2].rx.z2_base = card->fifos + 0x6102;
1577 + card->chans[B2].rx.z_min = 0x0200;
1578 + card->chans[B2].rx.z_max = 0x1FFF;
1579 + card->chans[B2].rx.f_min = 0x00;
1580 + card->chans[B2].rx.f_max = 0x1F;
1581 + card->chans[B2].rx.f1 = card->fifos + 0x6180;
1582 + card->chans[B2].rx.f2 = card->fifos + 0x6181;
1583 + card->chans[B2].rx.fifo_size = card->chans[B2].rx.z_max -
1584 + card->chans[B2].rx.z_min + 1;
1585 + card->chans[B2].rx.f_num = card->chans[B2].rx.f_max -
1586 + card->chans[B2].rx.f_min + 1;
1587 +
1588 + card->chans[B2].tx.chan = &card->chans[B2];
1589 + card->chans[B2].tx.fifo_base = card->fifos + 0x2200;
1590 + card->chans[B2].tx.z_base = card->fifos + 0x2000;
1591 + card->chans[B2].tx.z1_base = card->fifos + 0x2100;
1592 + card->chans[B2].tx.z2_base = card->fifos + 0x2102;
1593 + card->chans[B2].tx.z_min = 0x0200;
1594 + card->chans[B2].tx.z_max = 0x1FFF;
1595 + card->chans[B2].tx.f_min = 0x00;
1596 + card->chans[B2].tx.f_max = 0x1F;
1597 + card->chans[B2].tx.f1 = card->fifos + 0x2180;
1598 + card->chans[B2].tx.f2 = card->fifos + 0x2181;
1599 + card->chans[B2].tx.fifo_size = card->chans[B2].tx.z_max -
1600 + card->chans[B2].tx.z_min + 1;
1601 + card->chans[B2].tx.f_num = card->chans[B2].tx.f_max -
1602 + card->chans[B2].tx.f_min + 1;
1603 +
1604 + /*
1605 + * All done
1606 + */
1607 +
1608 + dahdi_hfcs = kmalloc(sizeof(struct dahdi_hfc), GFP_KERNEL);
1609 + if (!dahdi_hfcs) {
1610 + printk(KERN_CRIT hfc_DRIVER_PREFIX
1611 + "unable to kmalloc!\n");
1612 + goto err_request_irq;
1613 + }
1614 + memset(dahdi_hfcs, 0x0, sizeof(struct dahdi_hfc));
1615 +
1616 + dahdi_hfcs->card = card;
1617 + hfc_dahdi_initialize(dahdi_hfcs);
1618 + card->dahdi_dev = dahdi_hfcs;
1619 +
1620 + snprintf(card->proc_dir_name,
1621 + sizeof(card->proc_dir_name),
1622 + "%d", card->cardnum);
1623 + card->proc_dir = proc_mkdir(card->proc_dir_name, hfc_proc_dahdi_hfcs_dir);
1624 + SET_PROC_DIRENTRY_OWNER(card->proc_dir);
1625 +
1626 + hfc_resetCard(card);
1627 +
1628 + printk(KERN_INFO hfc_DRIVER_PREFIX
1629 + "card %d configured for %s mode at mem %#lx (0x%p) IRQ %u\n",
1630 + card->cardnum,
1631 + card->nt_mode ? "NT" : "TE",
1632 + card->io_bus_mem,
1633 + card->io_mem,
1634 + card->pcidev->irq);
1635 +
1636 + cardnum++;
1637 +
1638 + return 0;
1639 +
1640 +err_request_irq:
1641 + pci_free_consistent(pci_dev, hfc_FIFO_SIZE,
1642 + card->fifo_mem, card->fifo_bus_mem);
1643 +err_alloc_fifo:
1644 + iounmap(card->io_mem);
1645 +err_ioremap:
1646 +err_noiobase:
1647 +err_noirq:
1648 + pci_release_regions(pci_dev);
1649 +err_pci_request_regions:
1650 +err_pci_set_dma_mask:
1651 +err_pci_enable_device:
1652 + kfree(card);
1653 +err_alloc_hfccard:
1654 + return err;
1655 +}
1656 +
1657 +static void __devexit hfc_remove(struct pci_dev *pci_dev)
1658 +{
1659 + struct hfc_card *card = pci_get_drvdata(pci_dev);
1660 +
1661 +
1662 + printk(KERN_INFO hfc_DRIVER_PREFIX
1663 + "card %d: "
1664 + "shutting down card at %p.\n",
1665 + card->cardnum,
1666 + card->io_mem);
1667 +
1668 + if (!card) {
1669 + return;
1670 + }
1671 +
1672 + hfc_softreset(card);
1673 +
1674 + dahdi_unregister_device(card->dahdi_dev->ddev);
1675 +
1676 +
1677 + /*
1678 + * disable memio and bustmaster
1679 + */
1680 + pci_write_config_word(pci_dev, PCI_COMMAND, 0);
1681 +
1682 +/*
1683 +BUG: these proc entries just cause Call traces, so removed.
1684 + remove_proc_entry("bufs", card->proc_dir);
1685 + remove_proc_entry("fifos", card->proc_dir);
1686 + remove_proc_entry("info", card->proc_dir);
1687 +*/
1688 + remove_proc_entry(card->proc_dir_name, hfc_proc_dahdi_hfcs_dir);
1689 +
1690 + free_irq(pci_dev->irq, card);
1691 +
1692 + pci_free_consistent(pci_dev, hfc_FIFO_SIZE,
1693 + card->fifo_mem, card->fifo_bus_mem);
1694 +
1695 + iounmap(card->io_mem);
1696 +
1697 + pci_release_regions(pci_dev);
1698 +
1699 + pci_disable_device(pci_dev);
1700 +
1701 + kfree(card);
1702 +}
1703 +
1704 +/******************************************
1705 + * Module stuff
1706 + ******************************************/
1707 +
1708 +static int __init hfc_init_module(void)
1709 +{
1710 + int ret;
1711 +
1712 + printk(KERN_INFO hfc_DRIVER_PREFIX
1713 + hfc_DRIVER_STRING " loading\n");
1714 +#ifdef DEBUG
1715 +printk(KERN_INFO hfc_DRIVER_PREFIX "Check /var/log/kern-debug.log for debugging output level %d.", debug_level);
1716 +printk(KERN_DEBUG hfc_DRIVER_PREFIX "base.c is debugging.");
1717 +#endif
1718 +
1719 +#if (KERNEL_VERSION(2, 6, 26) <= LINUX_VERSION_CODE)
1720 + hfc_proc_dahdi_hfcs_dir = proc_mkdir(hfc_DRIVER_NAME, NULL);
1721 +#else
1722 + hfc_proc_dahdi_hfcs_dir = proc_mkdir(hfc_DRIVER_NAME, proc_root_driver);
1723 +#endif
1724 +
1725 + ret = dahdi_pci_module(&hfc_driver);
1726 + return ret;
1727 +}
1728 +
1729 +module_init(hfc_init_module);
1730 +
1731 +static void __exit hfc_module_exit(void)
1732 +{
1733 + pci_unregister_driver(&hfc_driver);
1734 +
1735 +#if (KERNEL_VERSION(2, 6, 26) <= LINUX_VERSION_CODE)
1736 + remove_proc_entry(hfc_DRIVER_NAME, NULL);
1737 +#else
1738 + remove_proc_entry(hfc_DRIVER_NAME, proc_root_driver);
1739 +#endif
1740 +
1741 + printk(KERN_INFO hfc_DRIVER_PREFIX
1742 + hfc_DRIVER_STRING " unloaded\n");
1743 +}
1744 +
1745 +module_exit(hfc_module_exit);
1746 +
1747 +#endif
1748 +
1749 +MODULE_DESCRIPTION(hfc_DRIVER_DESCR);
1750 +MODULE_AUTHOR("Jens Wilke <jw_vzaphfc@headissue.com>, "
1751 + "Daniele (Vihai) Orlandi <daniele@orlandi.com>, "
1752 + "Jose A. Deniz <odicha@hotmail.com>");
1753 +MODULE_ALIAS("dahdi_hfcs");
1754 +#ifdef MODULE_LICENSE
1755 +MODULE_LICENSE("GPL");
1756 +#endif
1757 +
1758 +
1759 +module_param(modes, int, 0444);
1760 +
1761 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 10)
1762 +module_param_array(nt_modes, int, &nt_modes_count, 0444);
1763 +#else
1764 +module_param_array(nt_modes, int, nt_modes_count, 0444);
1765 +#endif
1766 +
1767 +module_param(force_l1_up, int, 0444);
1768 +#ifdef DEBUG
1769 +module_param(debug_level, int, 0444);
1770 +#endif
1771 +
1772 +MODULE_PARM_DESC(modes, "[Deprecated] bit-mask to configure NT mode");
1773 +MODULE_PARM_DESC(nt_modes,
1774 + "Comma-separated list of card IDs to configure in NT mode");
1775 +MODULE_PARM_DESC(force_l1_up, "Don't allow L1 to go down");
1776 +#ifdef DEBUG
1777 +MODULE_PARM_DESC(debug_level, "Debug verbosity level");
1778 +#endif
1779 Index: dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/dahdi_hfcs.h
1780 ===================================================================
1781 --- /dev/null
1782 +++ dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/dahdi_hfcs.h
1783 @@ -0,0 +1,419 @@
1784 +/*
1785 + * dahdi_hfcs.h - Dahdi driver for HFC-S PCI A based ISDN BRI cards
1786 + *
1787 + * Dahdi port by Jose A. Deniz <odicha@hotmail.com>
1788 + *
1789 + * Copyright (C) 2009 Jose A. Deniz
1790 + * Copyright (C) 2006 headissue GmbH; Jens Wilke
1791 + * Copyright (C) 2004 Daniele Orlandi
1792 + * Copyright (C) 2002, 2003, 2004, Junghanns.NET GmbH
1793 + *
1794 + * Jens Wilke <jw_vzaphfc@headissue.com>
1795 + *
1796 + * Orginal author of this code is
1797 + * Daniele "Vihai" Orlandi <daniele@orlandi.com>
1798 + *
1799 + * Major rewrite of the driver made by
1800 + * Klaus-Peter Junghanns <kpj@junghanns.net>
1801 + *
1802 + * This program is free software and may be modified and
1803 + * distributed under the terms of the GNU Public License.
1804 + *
1805 + */
1806 +
1807 +#ifndef _HFC_ZAPHFC_H
1808 +#define _HFC_ZAPHFC_H
1809 +
1810 +#include <asm/io.h>
1811 +
1812 +#define hfc_DRIVER_NAME "dahdi_hfcs"
1813 +#define hfc_DRIVER_PREFIX hfc_DRIVER_NAME ": "
1814 +#define hfc_DRIVER_DESCR "HFC-S PCI A ISDN"
1815 +#define hfc_DRIVER_VERSION "1.42"
1816 +#define hfc_DRIVER_STRING hfc_DRIVER_DESCR " (V" hfc_DRIVER_VERSION ")"
1817 +
1818 +#define hfc_MAX_BOARDS 32
1819 +
1820 +#ifndef PCI_DMA_32BIT
1821 +#define PCI_DMA_32BIT 0x00000000ffffffffULL
1822 +#endif
1823 +
1824 +#ifndef PCI_VENDOR_ID_SITECOM
1825 +#define PCI_VENDOR_ID_SITECOM 0x182D
1826 +#endif
1827 +
1828 +#ifndef PCI_DEVICE_ID_SITECOM_3069
1829 +#define PCI_DEVICE_ID_SITECOM_3069 0x3069
1830 +#endif
1831 +
1832 +#define hfc_RESET_DELAY 20
1833 +
1834 +#define hfc_CLKDEL_TE 0x0f /* CLKDEL in TE mode */
1835 +#define hfc_CLKDEL_NT 0x6c /* CLKDEL in NT mode */
1836 +
1837 +/* PCI memory mapped I/O */
1838 +
1839 +#define hfc_PCI_MEM_SIZE 0x0100
1840 +#define hfc_PCI_MWBA 0x80
1841 +
1842 +/* GCI/IOM bus monitor registers */
1843 +
1844 +#define hfc_C_I 0x08
1845 +#define hfc_TRxR 0x0C
1846 +#define hfc_MON1_D 0x28
1847 +#define hfc_MON2_D 0x2C
1848 +
1849 +
1850 +/* GCI/IOM bus timeslot registers */
1851 +
1852 +#define hfc_B1_SSL 0x80
1853 +#define hfc_B2_SSL 0x84
1854 +#define hfc_AUX1_SSL 0x88
1855 +#define hfc_AUX2_SSL 0x8C
1856 +#define hfc_B1_RSL 0x90
1857 +#define hfc_B2_RSL 0x94
1858 +#define hfc_AUX1_RSL 0x98
1859 +#define hfc_AUX2_RSL 0x9C
1860 +
1861 +/* GCI/IOM bus data registers */
1862 +
1863 +#define hfc_B1_D 0xA0
1864 +#define hfc_B2_D 0xA4
1865 +#define hfc_AUX1_D 0xA8
1866 +#define hfc_AUX2_D 0xAC
1867 +
1868 +/* GCI/IOM bus configuration registers */
1869 +
1870 +#define hfc_MST_EMOD 0xB4
1871 +#define hfc_MST_MODE 0xB8
1872 +#define hfc_CONNECT 0xBC
1873 +
1874 +
1875 +/* Interrupt and status registers */
1876 +
1877 +#define hfc_FIFO_EN 0x44
1878 +#define hfc_TRM 0x48
1879 +#define hfc_B_MODE 0x4C
1880 +#define hfc_CHIP_ID 0x58
1881 +#define hfc_CIRM 0x60
1882 +#define hfc_CTMT 0x64
1883 +#define hfc_INT_M1 0x68
1884 +#define hfc_INT_M2 0x6C
1885 +#define hfc_INT_S1 0x78
1886 +#define hfc_INT_S2 0x7C
1887 +#define hfc_STATUS 0x70
1888 +
1889 +/* S/T section registers */
1890 +
1891 +#define hfc_STATES 0xC0
1892 +#define hfc_SCTRL 0xC4
1893 +#define hfc_SCTRL_E 0xC8
1894 +#define hfc_SCTRL_R 0xCC
1895 +#define hfc_SQ 0xD0
1896 +#define hfc_CLKDEL 0xDC
1897 +#define hfc_B1_REC 0xF0
1898 +#define hfc_B1_SEND 0xF0
1899 +#define hfc_B2_REC 0xF4
1900 +#define hfc_B2_SEND 0xF4
1901 +#define hfc_D_REC 0xF8
1902 +#define hfc_D_SEND 0xF8
1903 +#define hfc_E_REC 0xFC
1904 +
1905 +/* Bits and values in various HFC PCI registers */
1906 +
1907 +/* bits in status register (READ) */
1908 +#define hfc_STATUS_PCI_PROC 0x02
1909 +#define hfc_STATUS_NBUSY 0x04
1910 +#define hfc_STATUS_TIMER_ELAP 0x10
1911 +#define hfc_STATUS_STATINT 0x20
1912 +#define hfc_STATUS_FRAMEINT 0x40
1913 +#define hfc_STATUS_ANYINT 0x80
1914 +
1915 +/* bits in CTMT (Write) */
1916 +#define hfc_CTMT_TRANSB1 0x01
1917 +#define hfc_CTMT_TRANSB2 0x02
1918 +#define hfc_CTMT_TIMER_CLEAR 0x80
1919 +#define hfc_CTMT_TIMER_MASK 0x1C
1920 +#define hfc_CTMT_TIMER_3_125 (0x01 << 2)
1921 +#define hfc_CTMT_TIMER_6_25 (0x02 << 2)
1922 +#define hfc_CTMT_TIMER_12_5 (0x03 << 2)
1923 +#define hfc_CTMT_TIMER_25 (0x04 << 2)
1924 +#define hfc_CTMT_TIMER_50 (0x05 << 2)
1925 +#define hfc_CTMT_TIMER_400 (0x06 << 2)
1926 +#define hfc_CTMT_TIMER_800 (0x07 << 2)
1927 +#define hfc_CTMT_AUTO_TIMER 0x20
1928 +
1929 +/* bits in CIRM (Write) */
1930 +#define hfc_CIRM_AUX_MSK 0x07
1931 +#define hfc_CIRM_RESET 0x08
1932 +#define hfc_CIRM_B1_REV 0x40
1933 +#define hfc_CIRM_B2_REV 0x80
1934 +
1935 +/* bits in INT_M1 and INT_S1 */
1936 +#define hfc_INTS_B1TRANS 0x01
1937 +#define hfc_INTS_B2TRANS 0x02
1938 +#define hfc_INTS_DTRANS 0x04
1939 +#define hfc_INTS_B1REC 0x08
1940 +#define hfc_INTS_B2REC 0x10
1941 +#define hfc_INTS_DREC 0x20
1942 +#define hfc_INTS_L1STATE 0x40
1943 +#define hfc_INTS_TIMER 0x80
1944 +
1945 +/* bits in INT_M2 */
1946 +#define hfc_M2_PROC_TRANS 0x01
1947 +#define hfc_M2_GCI_I_CHG 0x02
1948 +#define hfc_M2_GCI_MON_REC 0x04
1949 +#define hfc_M2_IRQ_ENABLE 0x08
1950 +#define hfc_M2_PMESEL 0x80
1951 +
1952 +/* bits in STATES */
1953 +#define hfc_STATES_STATE_MASK 0x0F
1954 +#define hfc_STATES_LOAD_STATE 0x10
1955 +#define hfc_STATES_ACTIVATE 0x20
1956 +#define hfc_STATES_DO_ACTION 0x40
1957 +#define hfc_STATES_NT_G2_G3 0x80
1958 +
1959 +/* bits in HFCD_MST_MODE */
1960 +#define hfc_MST_MODE_MASTER 0x01
1961 +#define hfc_MST_MODE_SLAVE 0x00
1962 +/* remaining bits are for codecs control */
1963 +
1964 +/* bits in HFCD_SCTRL */
1965 +#define hfc_SCTRL_B1_ENA 0x01
1966 +#define hfc_SCTRL_B2_ENA 0x02
1967 +#define hfc_SCTRL_MODE_TE 0x00
1968 +#define hfc_SCTRL_MODE_NT 0x04
1969 +#define hfc_SCTRL_LOW_PRIO 0x08
1970 +#define hfc_SCTRL_SQ_ENA 0x10
1971 +#define hfc_SCTRL_TEST 0x20
1972 +#define hfc_SCTRL_NONE_CAP 0x40
1973 +#define hfc_SCTRL_PWR_DOWN 0x80
1974 +
1975 +/* bits in SCTRL_E */
1976 +#define hfc_SCTRL_E_AUTO_AWAKE 0x01
1977 +#define hfc_SCTRL_E_DBIT_1 0x04
1978 +#define hfc_SCTRL_E_IGNORE_COL 0x08
1979 +#define hfc_SCTRL_E_CHG_B1_B2 0x80
1980 +
1981 +/* bits in SCTRL_R */
1982 +#define hfc_SCTRL_R_B1_ENA 0x01
1983 +#define hfc_SCTRL_R_B2_ENA 0x02
1984 +
1985 +/* bits in FIFO_EN register */
1986 +#define hfc_FIFOEN_B1TX 0x01
1987 +#define hfc_FIFOEN_B1RX 0x02
1988 +#define hfc_FIFOEN_B2TX 0x04
1989 +#define hfc_FIFOEN_B2RX 0x08
1990 +#define hfc_FIFOEN_DTX 0x10
1991 +#define hfc_FIFOEN_DRX 0x20
1992 +
1993 +#define hfc_FIFOEN_B1 (hfc_FIFOEN_B1TX|hfc_FIFOEN_B1RX)
1994 +#define hfc_FIFOEN_B2 (hfc_FIFOEN_B2TX|hfc_FIFOEN_B2RX)
1995 +#define hfc_FIFOEN_D (hfc_FIFOEN_DTX|hfc_FIFOEN_DRX)
1996 +
1997 +/* bits in the CONNECT register */
1998 +#define hfc_CONNECT_B1_HFC_from_ST 0x00
1999 +#define hfc_CONNECT_B1_HFC_from_GCI 0x01
2000 +#define hfc_CONNECT_B1_ST_from_HFC 0x00
2001 +#define hfc_CONNECT_B1_ST_from_GCI 0x02
2002 +#define hfc_CONNECT_B1_GCI_from_HFC 0x00
2003 +#define hfc_CONNECT_B1_GCI_from_ST 0x04
2004 +
2005 +#define hfc_CONNECT_B2_HFC_from_ST 0x00
2006 +#define hfc_CONNECT_B2_HFC_from_GCI 0x08
2007 +#define hfc_CONNECT_B2_ST_from_HFC 0x00
2008 +#define hfc_CONNECT_B2_ST_from_GCI 0x10
2009 +#define hfc_CONNECT_B2_GCI_from_HFC 0x00
2010 +#define hfc_CONNECT_B2_GCI_from_ST 0x20
2011 +
2012 +/* bits in the TRM register */
2013 +#define hfc_TRM_TRANS_INT_00 0x00
2014 +#define hfc_TRM_TRANS_INT_01 0x01
2015 +#define hfc_TRM_TRANS_INT_10 0x02
2016 +#define hfc_TRM_TRANS_INT_11 0x04
2017 +#define hfc_TRM_ECHO 0x20
2018 +#define hfc_TRM_B1_PLUS_B2 0x40
2019 +#define hfc_TRM_IOM_TEST_LOOP 0x80
2020 +
2021 +/* bits in the __SSL and __RSL registers */
2022 +#define hfc_SRSL_STIO 0x40
2023 +#define hfc_SRSL_ENABLE 0x80
2024 +#define hfc_SRCL_SLOT_MASK 0x1f
2025 +
2026 +/* FIFO memory definitions */
2027 +
2028 +#define hfc_FIFO_SIZE 0x8000
2029 +
2030 +#define hfc_UGLY_FRAMEBUF 0x2000
2031 +
2032 +#define hfc_TX_FIFO_PRELOAD (DAHDI_CHUNKSIZE + 2)
2033 +#define hfc_RX_FIFO_PRELOAD 4
2034 +
2035 +/* HDLC STUFF */
2036 +#define hfc_HDLC_BUF_LEN 32
2037 +/* arbitrary, just the max # of byts we will send to DAHDI per call */
2038 +
2039 +
2040 +/* NOTE: FIFO pointers are not declared volatile because accesses to the
2041 + * FIFOs are inherently safe.
2042 + */
2043 +
2044 +#ifdef DEBUG
2045 +extern int debug_level;
2046 +#endif
2047 +
2048 +struct hfc_chan;
2049 +
2050 +struct hfc_chan_simplex {
2051 + struct hfc_chan_duplex *chan;
2052 +
2053 + u8 dahdi_buffer[DAHDI_CHUNKSIZE];
2054 +
2055 + u8 ugly_framebuf[hfc_UGLY_FRAMEBUF];
2056 + int ugly_framebuf_size;
2057 + u16 ugly_framebuf_off;
2058 +
2059 + void *z1_base, *z2_base;
2060 + void *fifo_base;
2061 + void *z_base;
2062 + u16 z_min;
2063 + u16 z_max;
2064 + u16 fifo_size;
2065 +
2066 + u8 *f1, *f2;
2067 + u8 f_min;
2068 + u8 f_max;
2069 + u8 f_num;
2070 +
2071 + unsigned long long frames;
2072 + unsigned long long bytes;
2073 + unsigned long long fifo_full;
2074 + unsigned long long crc;
2075 + unsigned long long fifo_underrun;
2076 +};
2077 +
2078 +enum hfc_chan_status {
2079 + free,
2080 + open_framed,
2081 + open_voice,
2082 + sniff_aux,
2083 + loopback,
2084 +};
2085 +
2086 +struct hfc_chan_duplex {
2087 + struct hfc_card *card;
2088 +
2089 + char *name;
2090 + int number;
2091 +
2092 + enum hfc_chan_status status;
2093 + int open_by_netdev;
2094 + int open_by_dahdi;
2095 +
2096 + unsigned short protocol;
2097 +
2098 + spinlock_t lock;
2099 +
2100 + struct hfc_chan_simplex rx;
2101 + struct hfc_chan_simplex tx;
2102 +
2103 +};
2104 +
2105 +typedef struct hfc_card {
2106 + int cardnum;
2107 + struct pci_dev *pcidev;
2108 + struct dahdi_hfc *dahdi_dev;
2109 + struct proc_dir_entry *proc_dir;
2110 + char proc_dir_name[32];
2111 +
2112 + struct proc_dir_entry *proc_info;
2113 + struct proc_dir_entry *proc_fifos;
2114 + struct proc_dir_entry *proc_bufs;
2115 +
2116 + unsigned long io_bus_mem;
2117 + void __iomem *io_mem;
2118 +
2119 + dma_addr_t fifo_bus_mem;
2120 + void *fifo_mem;
2121 + void *fifos;
2122 +
2123 + int nt_mode;
2124 + int sync_loss_reported;
2125 + int late_irqs;
2126 +
2127 + u8 l1_state;
2128 + int fifo_suspended;
2129 + int ignore_first_timer_interrupt;
2130 +
2131 + struct {
2132 + u8 m1;
2133 + u8 m2;
2134 + u8 fifo_en;
2135 + u8 trm;
2136 + u8 connect;
2137 + u8 sctrl;
2138 + u8 sctrl_r;
2139 + u8 sctrl_e;
2140 + u8 ctmt;
2141 + u8 cirm;
2142 + } regs;
2143 +
2144 + struct hfc_chan_duplex chans[3];
2145 + int echo_enabled;
2146 +
2147 +
2148 +
2149 + int debug_event;
2150 +
2151 + spinlock_t lock;
2152 + unsigned int irq;
2153 + unsigned int iomem;
2154 + int ticks;
2155 + int clicks;
2156 + unsigned char *pci_io;
2157 + void *fifomem; /* start of the shared mem */
2158 +
2159 + unsigned int pcibus;
2160 + unsigned int pcidevfn;
2161 +
2162 + int drecinframe;
2163 +
2164 + unsigned char cardno;
2165 + struct hfc_card *next;
2166 +
2167 +} hfc_card;
2168 +
2169 +typedef struct dahdi_hfc {
2170 + unsigned int usecount;
2171 + struct dahdi_device *ddev;
2172 + struct dahdi_span span;
2173 + struct dahdi_chan chans[3];
2174 + struct dahdi_chan *_chans[3];
2175 + struct hfc_card *card;
2176 +
2177 + /* pointer to the signalling channel for this span */
2178 + struct dahdi_chan *sigchan;
2179 + /* nonzero means we're in the middle of sending an HDLC frame */
2180 + int sigactive;
2181 + /* hdlc_hard_xmit() increments, hdlc_tx_frame() decrements */
2182 + atomic_t hdlc_pending;
2183 + int frames_out;
2184 + int frames_in;
2185 +
2186 +} dahdi_hfc;
2187 +
2188 +static inline struct dahdi_hfc* dahdi_hfc_from_span(struct dahdi_span *span) {
2189 + return container_of(span, struct dahdi_hfc, span);
2190 +}
2191 +
2192 +static inline u8 hfc_inb(struct hfc_card *card, int offset)
2193 +{
2194 + return readb(card->io_mem + offset);
2195 +}
2196 +
2197 +static inline void hfc_outb(struct hfc_card *card, int offset, u8 value)
2198 +{
2199 + writeb(value, card->io_mem + offset);
2200 +}
2201 +
2202 +#endif
2203 Index: dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/fifo.c
2204 ===================================================================
2205 --- /dev/null
2206 +++ dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/fifo.c
2207 @@ -0,0 +1,380 @@
2208 +/*
2209 + * fifo.c - HFC FIFO management routines
2210 + *
2211 + * Copyright (C) 2006 headissue GmbH; Jens Wilke
2212 + * Copyright (C) 2004 Daniele Orlandi
2213 + * Copyright (C) 2002, 2003, 2004, Junghanns.NET GmbH
2214 + *
2215 + * Original author of this code is
2216 + * Daniele "Vihai" Orlandi <daniele@orlandi.com>
2217 + *
2218 + * This program is free software and may be modified and
2219 + * distributed under the terms of the GNU Public License.
2220 + *
2221 + */
2222 +
2223 +#define DEBUG
2224 +#ifdef DEBUG
2225 +extern int debug_level;
2226 +#endif
2227 +
2228 +#include <linux/kernel.h>
2229 +
2230 +#include <dahdi/kernel.h>
2231 +
2232 +#include "fifo.h"
2233 +
2234 +static void hfc_fifo_mem_read(struct hfc_chan_simplex *chan,
2235 + int z_start,
2236 + void *data, int size)
2237 +{
2238 + int bytes_to_boundary = chan->z_max - z_start + 1;
2239 + if (bytes_to_boundary >= size) {
2240 + memcpy(data,
2241 + chan->z_base + z_start,
2242 + size);
2243 + } else {
2244 + /*
2245 + * Buffer wrap
2246 + */
2247 + memcpy(data,
2248 + chan->z_base + z_start,
2249 + bytes_to_boundary);
2250 +
2251 + memcpy(data + bytes_to_boundary,
2252 + chan->fifo_base,
2253 + size - bytes_to_boundary);
2254 + }
2255 +}
2256 +
2257 +static void hfc_fifo_mem_write(struct hfc_chan_simplex *chan,
2258 + void *data, int size)
2259 +{
2260 + int bytes_to_boundary = chan->z_max - *Z1_F1(chan) + 1;
2261 + if (bytes_to_boundary >= size) {
2262 + memcpy(chan->z_base + *Z1_F1(chan),
2263 + data,
2264 + size);
2265 + } else {
2266 + /*
2267 + * FIFO wrap
2268 + */
2269 +
2270 + memcpy(chan->z_base + *Z1_F1(chan),
2271 + data,
2272 + bytes_to_boundary);
2273 +
2274 + memcpy(chan->fifo_base,
2275 + data + bytes_to_boundary,
2276 + size - bytes_to_boundary);
2277 + }
2278 +}
2279 +
2280 +int hfc_fifo_get(struct hfc_chan_simplex *chan,
2281 + void *data, int size)
2282 +{
2283 + int available_bytes;
2284 +
2285 + /*
2286 + * Some useless statistic
2287 + */
2288 + chan->bytes += size;
2289 +
2290 + available_bytes = hfc_fifo_used_rx(chan);
2291 +
2292 + if (available_bytes < size && !chan->fifo_underrun++) {
2293 + /*
2294 + * print the warning only once
2295 + */
2296 + printk(KERN_WARNING hfc_DRIVER_PREFIX
2297 + "card %d: "
2298 + "chan %s: "
2299 + "RX FIFO not enough (%d) bytes to receive!\n",
2300 + chan->chan->card->cardnum,
2301 + chan->chan->name,
2302 + available_bytes);
2303 + return -1;
2304 + }
2305 +
2306 + hfc_fifo_mem_read(chan, *Z2_F2(chan), data, size);
2307 + *Z2_F2(chan) = Z_inc(chan, *Z2_F2(chan), size);
2308 + return available_bytes - size;
2309 +}
2310 +
2311 +void hfc_fifo_put(struct hfc_chan_simplex *chan,
2312 + void *data, int size)
2313 +{
2314 + struct hfc_card *card = chan->chan->card;
2315 + int used_bytes = hfc_fifo_used_tx(chan);
2316 + int free_bytes = hfc_fifo_free_tx(chan);
2317 +
2318 + if (!used_bytes && !chan->fifo_underrun++) {
2319 + /*
2320 + * print warning only once, to make timing not worse
2321 + */
2322 + printk(KERN_WARNING hfc_DRIVER_PREFIX
2323 + "card %d: "
2324 + "chan %s: "
2325 + "TX FIFO has become empty\n",
2326 + card->cardnum,
2327 + chan->chan->name);
2328 + }
2329 + if (free_bytes < size) {
2330 + printk(KERN_CRIT hfc_DRIVER_PREFIX
2331 + "card %d: "
2332 + "chan %s: "
2333 + "TX FIFO full!\n",
2334 + chan->chan->card->cardnum,
2335 + chan->chan->name);
2336 + chan->fifo_full++;
2337 + hfc_clear_fifo_tx(chan);
2338 + }
2339 +
2340 + hfc_fifo_mem_write(chan, data, size);
2341 + chan->bytes += size;
2342 + *Z1_F1(chan) = Z_inc(chan, *Z1_F1(chan), size);
2343 +}
2344 +
2345 +int hfc_fifo_get_frame(struct hfc_chan_simplex *chan, void *data, int max_size)
2346 +{
2347 + int frame_size;
2348 + u16 newz2 ;
2349 +
2350 + if (*chan->f1 == *chan->f2) {
2351 + /*
2352 + * nothing received, strange uh?
2353 + */
2354 + printk(KERN_WARNING hfc_DRIVER_PREFIX
2355 + "card %d: "
2356 + "chan %s: "
2357 + "get_frame called with no frame in FIFO.\n",
2358 + chan->chan->card->cardnum,
2359 + chan->chan->name);
2360 +
2361 + return -1;
2362 + }
2363 +
2364 + /*
2365 + * frame_size includes CRC+CRC+STAT
2366 + */
2367 + frame_size = hfc_fifo_get_frame_size(chan);
2368 +
2369 +#ifdef DEBUG
2370 + if (debug_level == 3) {
2371 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
2372 + "card %d: "
2373 + "chan %s: "
2374 + "RX len %2d: ",
2375 + chan->chan->card->cardnum,
2376 + chan->chan->name,
2377 + frame_size);
2378 + } else if (debug_level >= 4) {
2379 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
2380 + "card %d: "
2381 + "chan %s: "
2382 + "RX (f1=%02x, f2=%02x, z1=%04x, z2=%04x) len %2d: ",
2383 + chan->chan->card->cardnum,
2384 + chan->chan->name,
2385 + *chan->f1, *chan->f2, *Z1_F2(chan), *Z2_F2(chan),
2386 + frame_size);
2387 + }
2388 +
2389 + if (debug_level >= 3) {
2390 + int i;
2391 + for (i = 0; i < frame_size; i++) {
2392 + printk("%02x", hfc_fifo_u8(chan,
2393 + Z_inc(chan, *Z2_F2(chan), i)));
2394 + }
2395 +
2396 + printk("\n");
2397 + }
2398 +#endif
2399 +
2400 + if (frame_size <= 0) {
2401 +#ifdef DEBUG
2402 + if (debug_level >= 2) {
2403 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
2404 + "card %d: "
2405 + "chan %s: "
2406 + "invalid (empty) frame received.\n",
2407 + chan->chan->card->cardnum,
2408 + chan->chan->name);
2409 + }
2410 +#endif
2411 +
2412 + hfc_fifo_drop_frame(chan);
2413 + return -1;
2414 + }
2415 +
2416 + /*
2417 + * STAT is not really received
2418 + */
2419 + chan->bytes += frame_size - 1;
2420 +
2421 + /*
2422 + * Calculate beginning of the next frame
2423 + */
2424 + newz2 = Z_inc(chan, *Z2_F2(chan), frame_size);
2425 +
2426 + /*
2427 + * We cannot use hfc_fifo_get because of different semantic of
2428 + * "available bytes" and to avoid useless increment of Z2
2429 + */
2430 + hfc_fifo_mem_read(chan, *Z2_F2(chan), data,
2431 + frame_size < max_size ? frame_size : max_size);
2432 +
2433 + if (hfc_fifo_u8(chan, Z_inc(chan, *Z2_F2(chan),
2434 + frame_size - 1)) != 0x00) {
2435 + /*
2436 + * CRC not ok, frame broken, skipping
2437 + */
2438 +#ifdef DEBUG
2439 + if (debug_level >= 2) {
2440 + printk(KERN_WARNING hfc_DRIVER_PREFIX
2441 + "card %d: "
2442 + "chan %s: "
2443 + "Received frame with wrong CRC\n",
2444 + chan->chan->card->cardnum,
2445 + chan->chan->name);
2446 + }
2447 +#endif
2448 +
2449 + chan->crc++;
2450 +
2451 + hfc_fifo_drop_frame(chan);
2452 + return -1;
2453 + }
2454 +
2455 + chan->frames++;
2456 +
2457 + *chan->f2 = F_inc(chan, *chan->f2, 1);
2458 +
2459 + /*
2460 + * Set Z2 for the next frame we're going to receive
2461 + */
2462 + *Z2_F2(chan) = newz2;
2463 +
2464 + return frame_size;
2465 +}
2466 +
2467 +void hfc_fifo_drop_frame(struct hfc_chan_simplex *chan)
2468 +{
2469 + int available_bytes;
2470 + u16 newz2;
2471 +
2472 + if (*chan->f1 == *chan->f2) {
2473 + /*
2474 + * nothing received, strange eh?
2475 + */
2476 + printk(KERN_WARNING hfc_DRIVER_PREFIX
2477 + "card %d: "
2478 + "chan %s: "
2479 + "skip_frame called with no frame in FIFO.\n",
2480 + chan->chan->card->cardnum,
2481 + chan->chan->name);
2482 +
2483 + return;
2484 + }
2485 +
2486 + available_bytes = hfc_fifo_used_rx(chan) + 1;
2487 +
2488 + /*
2489 + * Calculate beginning of the next frame
2490 + */
2491 + newz2 = Z_inc(chan, *Z2_F2(chan), available_bytes);
2492 +
2493 + *chan->f2 = F_inc(chan, *chan->f2, 1);
2494 +
2495 + /*
2496 + * Set Z2 for the next frame we're going to receive
2497 + */
2498 + *Z2_F2(chan) = newz2;
2499 +}
2500 +
2501 +void hfc_fifo_put_frame(struct hfc_chan_simplex *chan,
2502 + void *data, int size)
2503 +{
2504 + u16 newz1;
2505 + int available_frames;
2506 +
2507 +#ifdef DEBUG
2508 + if (debug_level == 3) {
2509 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
2510 + "card %d: "
2511 + "chan %s: "
2512 + "TX len %2d: ",
2513 + chan->chan->card->cardnum,
2514 + chan->chan->name,
2515 + size);
2516 + } else if (debug_level >= 4) {
2517 + printk(KERN_DEBUG hfc_DRIVER_PREFIX
2518 + "card %d: "
2519 + "chan %s: "
2520 + "TX (f1=%02x, f2=%02x, z1=%04x, z2=%04x) len %2d: ",
2521 + chan->chan->card->cardnum,
2522 + chan->chan->name,
2523 + *chan->f1, *chan->f2, *Z1_F1(chan), *Z2_F1(chan),
2524 + size);
2525 + }
2526 +
2527 + if (debug_level >= 3) {
2528 + int i;
2529 + for (i = 0; i < size; i++)
2530 + printk("%02x", ((u8 *)data)[i]);
2531 +
2532 + printk("\n");
2533 + }
2534 +#endif
2535 +
2536 + available_frames = hfc_fifo_free_frames(chan);
2537 +
2538 + if (available_frames >= chan->f_num) {
2539 + printk(KERN_CRIT hfc_DRIVER_PREFIX
2540 + "card %d: "
2541 + "chan %s: "
2542 + "TX FIFO total number of frames exceeded!\n",
2543 + chan->chan->card->cardnum,
2544 + chan->chan->name);
2545 +
2546 + chan->fifo_full++;
2547 +
2548 + return;
2549 + }
2550 +
2551 + hfc_fifo_put(chan, data, size);
2552 +
2553 + newz1 = *Z1_F1(chan);
2554 +
2555 + *chan->f1 = F_inc(chan, *chan->f1, 1);
2556 +
2557 + *Z1_F1(chan) = newz1;
2558 +
2559 + chan->frames++;
2560 +}
2561 +
2562 +void hfc_clear_fifo_rx(struct hfc_chan_simplex *chan)
2563 +{
2564 + *chan->f2 = *chan->f1;
2565 + *Z2_F2(chan) = *Z1_F2(chan);
2566 +}
2567 +
2568 +void hfc_clear_fifo_tx(struct hfc_chan_simplex *chan)
2569 +{
2570 + *chan->f1 = *chan->f2;
2571 + *Z1_F1(chan) = *Z2_F1(chan);
2572 +
2573 + if (chan->chan->status == open_voice) {
2574 + /*
2575 + * Make sure that at least hfc_TX_FIFO_PRELOAD bytes are
2576 + * present in the TX FIFOs
2577 + * Create hfc_TX_FIFO_PRELOAD bytes of empty data
2578 + * (0x7f is mute audio)
2579 + */
2580 + u8 empty_fifo[hfc_TX_FIFO_PRELOAD +
2581 + DAHDI_CHUNKSIZE + hfc_RX_FIFO_PRELOAD];
2582 + memset(empty_fifo, 0x7f, sizeof(empty_fifo));
2583 +
2584 + hfc_fifo_put(chan, empty_fifo, sizeof(empty_fifo));
2585 + }
2586 +}
2587 +
2588 Index: dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/fifo.h
2589 ===================================================================
2590 --- /dev/null
2591 +++ dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/fifo.h
2592 @@ -0,0 +1,139 @@
2593 +/*
2594 + * fifo.h - Dahdi driver for HFC-S PCI A based ISDN BRI cards
2595 + *
2596 + * Copyright (C) 2004 Daniele Orlandi
2597 + * Copyright (C) 2002, 2003, 2004, Junghanns.NET GmbH
2598 + *
2599 + * Daniele "Vihai" Orlandi <daniele@orlandi.com>
2600 + *
2601 + * Major rewrite of the driver made by
2602 + * Klaus-Peter Junghanns <kpj@junghanns.net>
2603 + *
2604 + * This program is free software and may be modified and
2605 + * distributed under the terms of the GNU Public License.
2606 + *
2607 + */
2608 +
2609 +#ifndef _HFC_FIFO_H
2610 +#define _HFC_FIFO_H
2611 +
2612 +#include "dahdi_hfcs.h"
2613 +
2614 +static inline u16 *Z1_F1(struct hfc_chan_simplex *chan)
2615 +{
2616 + return chan->z1_base + (*chan->f1 * 4);
2617 +}
2618 +
2619 +static inline u16 *Z2_F1(struct hfc_chan_simplex *chan)
2620 +{
2621 + return chan->z2_base + (*chan->f1 * 4);
2622 +}
2623 +
2624 +static inline u16 *Z1_F2(struct hfc_chan_simplex *chan)
2625 +{
2626 + return chan->z1_base + (*chan->f2 * 4);
2627 +}
2628 +
2629 +static inline u16 *Z2_F2(struct hfc_chan_simplex *chan)
2630 +{
2631 + return chan->z2_base + (*chan->f2 * 4);
2632 +}
2633 +
2634 +static inline u16 Z_inc(struct hfc_chan_simplex *chan, u16 z, u16 inc)
2635 +{
2636 + /*
2637 + * declared as u32 in order to manage overflows
2638 + */
2639 + u32 newz = z + inc;
2640 + if (newz > chan->z_max)
2641 + newz -= chan->fifo_size;
2642 +
2643 + return newz;
2644 +}
2645 +
2646 +static inline u8 F_inc(struct hfc_chan_simplex *chan, u8 f, u8 inc)
2647 +{
2648 + /*
2649 + * declared as u16 in order to manage overflows
2650 + */
2651 + u16 newf = f + inc;
2652 + if (newf > chan->f_max)
2653 + newf -= chan->f_num;
2654 +
2655 + return newf;
2656 +}
2657 +
2658 +static inline u16 hfc_fifo_used_rx(struct hfc_chan_simplex *chan)
2659 +{
2660 + return (*Z1_F2(chan) - *Z2_F2(chan) +
2661 + chan->fifo_size) % chan->fifo_size;
2662 +}
2663 +
2664 +static inline u16 hfc_fifo_get_frame_size(struct hfc_chan_simplex *chan)
2665 +{
2666 + /*
2667 + * This +1 is needed because in frame mode the available bytes are Z2-Z1+1
2668 + * while in transparent mode I wouldn't consider the byte pointed by Z2 to
2669 + * be available, otherwise, the FIFO would always contain one byte, even
2670 + * when Z1==Z2
2671 + */
2672 +
2673 + return hfc_fifo_used_rx(chan) + 1;
2674 +}
2675 +
2676 +static inline u8 hfc_fifo_u8(struct hfc_chan_simplex *chan, u16 z)
2677 +{
2678 + return *((u8 *)(chan->z_base + z));
2679 +}
2680 +
2681 +static inline u16 hfc_fifo_used_tx(struct hfc_chan_simplex *chan)
2682 +{
2683 + return (*Z1_F1(chan) - *Z2_F1(chan) +
2684 + chan->fifo_size) % chan->fifo_size;
2685 +}
2686 +
2687 +static inline u16 hfc_fifo_free_rx(struct hfc_chan_simplex *chan)
2688 +{
2689 + u16 free_bytes = *Z2_F1(chan) - *Z1_F1(chan);
2690 +
2691 + if (free_bytes > 0)
2692 + return free_bytes;
2693 + else
2694 + return free_bytes + chan->fifo_size;
2695 +}
2696 +
2697 +static inline u16 hfc_fifo_free_tx(struct hfc_chan_simplex *chan)
2698 +{
2699 + u16 free_bytes = *Z2_F1(chan) - *Z1_F1(chan);
2700 +
2701 + if (free_bytes > 0)
2702 + return free_bytes;
2703 + else
2704 + return free_bytes + chan->fifo_size;
2705 +}
2706 +
2707 +static inline int hfc_fifo_has_frames(struct hfc_chan_simplex *chan)
2708 +{
2709 + return *chan->f1 != *chan->f2;
2710 +}
2711 +
2712 +static inline u8 hfc_fifo_used_frames(struct hfc_chan_simplex *chan)
2713 +{
2714 + return (*chan->f1 - *chan->f2 + chan->f_num) % chan->f_num;
2715 +}
2716 +
2717 +static inline u8 hfc_fifo_free_frames(struct hfc_chan_simplex *chan)
2718 +{
2719 + return (*chan->f2 - *chan->f1 + chan->f_num) % chan->f_num;
2720 +}
2721 +
2722 +int hfc_fifo_get(struct hfc_chan_simplex *chan, void *data, int size);
2723 +void hfc_fifo_put(struct hfc_chan_simplex *chan, void *data, int size);
2724 +void hfc_fifo_drop(struct hfc_chan_simplex *chan, int size);
2725 +int hfc_fifo_get_frame(struct hfc_chan_simplex *chan, void *data, int max_size);
2726 +void hfc_fifo_drop_frame(struct hfc_chan_simplex *chan);
2727 +void hfc_fifo_put_frame(struct hfc_chan_simplex *chan, void *data, int size);
2728 +void hfc_clear_fifo_rx(struct hfc_chan_simplex *chan);
2729 +void hfc_clear_fifo_tx(struct hfc_chan_simplex *chan);
2730 +
2731 +#endif
2732 Index: dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/Kbuild
2733 ===================================================================
2734 --- /dev/null
2735 +++ dahdi-linux-2.10.0.1/drivers/dahdi/hfcs/Kbuild
2736 @@ -0,0 +1,10 @@
2737 +obj-m += dahdi_hfcs.o
2738 +
2739 +EXTRA_CFLAGS := -I$(src)/.. -Wno-undef
2740 +
2741 +dahdi_hfcs-objs := base.o fifo.o
2742 +
2743 +$(obj)/base.o: $(src)/dahdi_hfcs.h
2744 +$(obj)/fifo.o: $(src)/fifo.h
2745 +
2746 +
Mirror of telephony feed