79188ce435323f664a8b60380968e8124f1fb103
[openwrt/svn-archive/archive.git] / libs / libatomicops / patches / 001-mips.patch
1 diff --git a/src/atomic_ops.h b/src/atomic_ops.h
2 index c23f30b..791b360 100755
3 --- a/src/atomic_ops.h
4 +++ b/src/atomic_ops.h
5 @@ -220,6 +220,9 @@
6 # if defined(__cris__) || defined(CRIS)
7 # include "atomic_ops/sysdeps/gcc/cris.h"
8 # endif
9 +# if defined(__mips__)
10 +# include "atomic_ops/sysdeps/gcc/mips.h"
11 +# endif
12 #endif /* __GNUC__ && !AO_USE_PTHREAD_DEFS */
13
14 #if defined(__INTEL_COMPILER) && !defined(AO_USE_PTHREAD_DEFS)
15 diff --git a/src/atomic_ops/sysdeps/Makefile.am b/src/atomic_ops/sysdeps/Makefile.am
16 index 74122b4..d6737c0 100644
17 --- a/src/atomic_ops/sysdeps/Makefile.am
18 +++ b/src/atomic_ops/sysdeps/Makefile.am
19 @@ -29,6 +29,7 @@ nobase_sysdep_HEADERS= generic_pthread.h \
20 gcc/powerpc.h gcc/sparc.h \
21 gcc/hppa.h gcc/m68k.h gcc/s390.h \
22 gcc/ia64.h gcc/x86_64.h gcc/cris.h \
23 + gcc/mips.h \
24 \
25 icc/ia64.h \
26 \
27 diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h
28 new file mode 100644
29 index 0000000..e7f3a5d
30 --- /dev/null
31 +++ b/src/atomic_ops/sysdeps/gcc/mips.h
32 @@ -0,0 +1,89 @@
33 +/*
34 + * Copyright (c) 2005 Thiemo Seufer <ths@networkno.de>
35 + * Copyright (c) 2007 Zhang Le <r0bertz@gentoo.org>
36 + *
37 + * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
38 + * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
39 + *
40 + * Permission is hereby granted to use or copy this program
41 + * for any purpose, provided the above notices are retained on all copies.
42 + * Permission to modify the code and to distribute modified code is granted,
43 + * provided the above notices are retained, and a notice that the code was
44 + * modified is included with the above copyright notice.
45 + */
46 +
47 +#include "../all_aligned_atomic_load_store.h"
48 +#include "../test_and_set_t_is_ao_t.h"
49 +
50 +/* Data dependence does not imply read ordering. */
51 +#define AO_NO_DD_ORDERING
52 +
53 +AO_INLINE void
54 +AO_nop_full()
55 +{
56 + __asm__ __volatile__(
57 + " .set push \n"
58 + " .set mips3 \n"
59 + " .set noreorder \n"
60 + " .set nomacro \n"
61 + " sync \n"
62 + " .set pop "
63 + : : : "memory");
64 +}
65 +
66 +#define AO_HAVE_nop_full
67 +
68 +AO_INLINE int
69 +AO_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val)
70 +{
71 + register int was_equal = 0;
72 + register int temp;
73 +
74 + __asm__ __volatile__(
75 + " .set push \n"
76 + " .set mips3 \n"
77 + " .set noreorder \n"
78 + " .set nomacro \n"
79 + "1: ll %0, %1 \n"
80 + " bne %0, %4, 2f \n"
81 + " move %0, %3 \n"
82 + " sc %0, %1 \n"
83 + " .set pop \n"
84 + " beqz %0, 1b \n"
85 + " li %2, 1 \n"
86 + "2: "
87 + : "=&r" (temp), "+R" (*addr), "+r" (was_equal)
88 + : "r" (new_val), "r" (old)
89 + : "memory");
90 + return was_equal;
91 +}
92 +
93 +#define AO_HAVE_compare_and_swap
94 +
95 +AO_INLINE AO_t
96 +AO_fetch_and_add_full (volatile AO_t *p, AO_t incr)
97 +{
98 + AO_t result, temp;
99 + __asm__ __volatile__(
100 + " .set push \n"
101 + " .set mips3 \n"
102 + " .set noreorder \n"
103 + " .set nomacro \n"
104 + "1: ll %1, %2 \n"
105 + " addu %0, %1, %3 \n"
106 + " sc %0, %2 \n"
107 + " beqz %0, 1b \n"
108 + " addu %0, %1, %3 \n"
109 + " sync \n"
110 + " .set pop \n"
111 + : "=&r" (result), "=&r" (temp), "=m" (*p)
112 + : "r" (incr), "m" (*p)
113 + : "memory");
114 + return result;
115 +}
116 +
117 +#define AO_HAVE_fetch_and_add_full
118 +
119 +/*
120 + * FIXME: fetch_and_add_full implemented, any others?
121 + */