2 # Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
7 # Default, static values for build variables, listed in alphabetic order.
8 # Dependencies between build options, if any, are handled in the top-level
9 # Makefile, after this file is included. This ensures that the former is better
10 # poised to handle dependencies, as all build variables would have a default
14 AARCH32_INSTRUCTION_SET
:= T32
16 # The AArch32 Secure Payload to be built as BL32 image
19 # The Target build architecture. Supported values are: aarch64, aarch32.
22 # ARM Architecture major and minor versions: 8.0 by default.
26 # Base commit to perform code check on
27 BASE_COMMIT
:= origin/master
32 # BL2 image is stored in XIP memory, for now, this option is only supported
33 # when BL2_AT_EL3 is 1.
36 # Select the branch protection features to use.
37 BRANCH_PROTECTION
:= 0
39 # By default, consider that the platform may release several CPUs out of reset.
40 # The platform Makefile is free to override this value.
41 COLD_BOOT_SINGLE_CPU
:= 0
43 # Flag to compile in coreboot support code. Exclude by default. The coreboot
44 # Makefile system will set this when compiling TF as part of a coreboot image.
50 # Build flag to include AArch32 registers in cpu context save and restore during
51 # world switch. This flag must be set to 0 for AArch64-only platforms.
52 CTX_INCLUDE_AARCH32_REGS
:= 1
54 # Include FP registers in cpu context
55 CTX_INCLUDE_FPREGS
:= 0
57 # Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
58 # must be set to 1 if the platform wants to use this feature in the Secure
59 # world. It is not needed to use it in the Non-secure world.
60 CTX_INCLUDE_PAUTH_REGS
:= 0
68 # Disable the generation of the binary image (ELF only).
69 DISABLE_BIN_GENERATION
:= 0
71 # Enable capability to disable authentication dynamically. Only meant for
72 # development platforms.
75 # Build option to enable MPAM for lower ELs
76 ENABLE_MPAM_FOR_LOWER_ELS
:= 0
78 # Flag to Enable Position Independant support (PIE)
81 # Flag to enable Performance Measurement Framework
84 # Flag to enable PSCI STATs functionality
87 # Flag to enable runtime instrumentation using PMF
88 ENABLE_RUNTIME_INSTRUMENTATION
:= 0
90 # Flag to enable stack corruption protection
91 ENABLE_STACK_PROTECTOR
:= 0
93 # Flag to enable exception handling in EL3
94 EL3_EXCEPTION_HANDLING
:= 0
96 # Flag to enable Branch Target Identification.
97 # Internal flag not meant for direct setting.
98 # Use BRANCH_PROTECTION to enable BTI.
101 # Flag to enable Pointer Authentication.
102 # Internal flag not meant for direct setting.
103 # Use BRANCH_PROTECTION to enable PAUTH.
106 # Build flag to treat usage of deprecated platform and framework APIs as error.
107 ERROR_DEPRECATED
:= 0
109 # Fault injection support
110 FAULT_INJECTION_SUPPORT
:= 0
112 # Byte alignment that each component in FIP is aligned to
115 # Default FIP file name
118 # Default FWU_FIP file name
119 FWU_FIP_NAME
:= fwu_fip.bin
124 # Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
125 # default, they are for Secure EL1.
126 GICV2_G0_FOR_EL3
:= 0
128 # Route External Aborts to EL3. Disabled by default; External Aborts are handled
130 HANDLE_EA_EL3_FIRST
:= 0
132 # Whether system coherency is managed in hardware, without explicit software
134 HW_ASSISTED_COHERENCY
:= 0
136 # Set the default algorithm for the generation of Trusted Board Boot keys
139 # NS timer register save and restore
142 # Include lib/libc in the final image
145 # Build PL011 UART driver in minimal generic UART mode
146 PL011_GENERIC_UART
:= 0
148 # By default, consider that the platform's reset address is not programmable.
149 # The platform Makefile is free to override this value.
150 PROGRAMMABLE_RESET_ADDRESS
:= 0
152 # Flag used to choose the power state format: Extended State-ID or Original
153 PSCI_EXTENDED_STATE_ID
:= 0
158 # By default, BL1 acts as the reset handler, not BL31
164 # Software Delegated Exception support
167 # Whether code and read-only data should be put on separate memory pages. The
168 # platform Makefile is free to override this value.
169 SEPARATE_CODE_AND_RODATA
:= 0
171 # If the BL31 image initialisation code is recalimed after use for the secondary
173 RECLAIM_INIT_CODE
:= 0
178 # For including the Secure Partition Manager
181 # Use the SPM based on MM
184 # Flag to introduce an infinite loop in BL1 just before it exits into the next
185 # image. This is meant to help debugging the post-BL2 phase.
186 SPIN_ON_BL1_EXIT
:= 0
188 # Flags to build TF with Trusted Boot support
189 TRUSTED_BOARD_BOOT
:= 0
191 # Build option to choose whether Trusted Firmware uses Coherent memory or not.
192 USE_COHERENT_MEM
:= 1
194 # Build option to choose whether Trusted Firmware uses library at ROM
197 # Use tbbr_oid.h instead of platform_oid.h
203 # Whether to enable D-Cache early during warm boot. This is usually
204 # applicable for platforms wherein interconnect programming is not
205 # required to enable cache coherency after warm reset (eg: single cluster
207 WARMBOOT_ENABLE_DCACHE_EARLY
:= 0
209 # Build option to enable/disable the Statistical Profiling Extensions
210 ENABLE_SPE_FOR_LOWER_ELS
:= 1
212 # SPE is only supported on AArch64 so disable it on AArch32.
213 ifeq (${ARCH},aarch32
)
214 override ENABLE_SPE_FOR_LOWER_ELS
:= 0
217 # Include Memory Tagging Extension registers in cpu context. This must be set
218 # to 1 if the platform wants to use this feature in the Secure world and MTE is
220 CTX_INCLUDE_MTE_REGS
:= 0
224 # By default, enable Scalable Vector Extension if implemented for Non-secure
226 # Note SVE is only supported on AArch64 - therefore do not enable in AArch32
227 ifneq (${ARCH},aarch32
)
228 ENABLE_SVE_FOR_NS
:= 1
230 override ENABLE_SVE_FOR_NS
:= 0