2 # Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
4 # SPDX-License-Identifier: BSD-3-Clause
7 # Default, static values for build variables, listed in alphabetic order.
8 # Dependencies between build options, if any, are handled in the top-level
9 # Makefile, after this file is included. This ensures that the former is better
10 # poised to handle dependencies, as all build variables would have a default
14 AARCH32_INSTRUCTION_SET
:= T32
16 # The AArch32 Secure Payload to be built as BL32 image
19 # The Target build architecture. Supported values are: aarch64, aarch32.
22 # ARM Architecture major and minor versions: 8.0 by default.
26 # Base commit to perform code check on
27 BASE_COMMIT
:= origin/master
32 # BL2 image is stored in XIP memory, for now, this option is only supported
33 # when BL2_AT_EL3 is 1.
36 # Do dcache invalidate upon BL2 entry at EL3
39 # Select the branch protection features to use.
40 BRANCH_PROTECTION
:= 0
42 # By default, consider that the platform may release several CPUs out of reset.
43 # The platform Makefile is free to override this value.
44 COLD_BOOT_SINGLE_CPU
:= 0
46 # Flag to compile in coreboot support code. Exclude by default. The coreboot
47 # Makefile system will set this when compiling TF as part of a coreboot image.
53 # Build flag to include AArch32 registers in cpu context save and restore during
54 # world switch. This flag must be set to 0 for AArch64-only platforms.
55 CTX_INCLUDE_AARCH32_REGS
:= 1
57 # Include FP registers in cpu context
58 CTX_INCLUDE_FPREGS
:= 0
60 # Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
61 # must be set to 1 if the platform wants to use this feature in the Secure
62 # world. It is not needed to use it in the Non-secure world.
63 CTX_INCLUDE_PAUTH_REGS
:= 0
71 # Disable the generation of the binary image (ELF only).
72 DISABLE_BIN_GENERATION
:= 0
74 # Enable capability to disable authentication dynamically. Only meant for
75 # development platforms.
78 # Build option to enable MPAM for lower ELs
79 ENABLE_MPAM_FOR_LOWER_ELS
:= 0
81 # Flag to Enable Position Independant support (PIE)
84 # Flag to enable Performance Measurement Framework
87 # Flag to enable PSCI STATs functionality
90 # Flag to enable runtime instrumentation using PMF
91 ENABLE_RUNTIME_INSTRUMENTATION
:= 0
93 # Flag to enable stack corruption protection
94 ENABLE_STACK_PROTECTOR
:= 0
96 # Flag to enable exception handling in EL3
97 EL3_EXCEPTION_HANDLING
:= 0
99 # Flag to enable Branch Target Identification.
100 # Internal flag not meant for direct setting.
101 # Use BRANCH_PROTECTION to enable BTI.
104 # Flag to enable Pointer Authentication.
105 # Internal flag not meant for direct setting.
106 # Use BRANCH_PROTECTION to enable PAUTH.
109 # Build flag to treat usage of deprecated platform and framework APIs as error.
110 ERROR_DEPRECATED
:= 0
112 # Fault injection support
113 FAULT_INJECTION_SUPPORT
:= 0
115 # Byte alignment that each component in FIP is aligned to
118 # Default FIP file name
121 # Default FWU_FIP file name
122 FWU_FIP_NAME
:= fwu_fip.bin
127 # Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
128 # default, they are for Secure EL1.
129 GICV2_G0_FOR_EL3
:= 0
131 # Route External Aborts to EL3. Disabled by default; External Aborts are handled
133 HANDLE_EA_EL3_FIRST
:= 0
135 # Whether system coherency is managed in hardware, without explicit software
137 HW_ASSISTED_COHERENCY
:= 0
139 # Set the default algorithm for the generation of Trusted Board Boot keys
142 # NS timer register save and restore
145 # Include lib/libc in the final image
148 # Build PL011 UART driver in minimal generic UART mode
149 PL011_GENERIC_UART
:= 0
151 # By default, consider that the platform's reset address is not programmable.
152 # The platform Makefile is free to override this value.
153 PROGRAMMABLE_RESET_ADDRESS
:= 0
155 # Flag used to choose the power state format: Extended State-ID or Original
156 PSCI_EXTENDED_STATE_ID
:= 0
161 # By default, BL1 acts as the reset handler, not BL31
167 # Software Delegated Exception support
170 # Whether code and read-only data should be put on separate memory pages. The
171 # platform Makefile is free to override this value.
172 SEPARATE_CODE_AND_RODATA
:= 0
174 # If the BL31 image initialisation code is recalimed after use for the secondary
176 RECLAIM_INIT_CODE
:= 0
181 # For including the Secure Partition Manager
184 # Use the SPM based on MM
187 # Flag to introduce an infinite loop in BL1 just before it exits into the next
188 # image. This is meant to help debugging the post-BL2 phase.
189 SPIN_ON_BL1_EXIT
:= 0
191 # Flags to build TF with Trusted Boot support
192 TRUSTED_BOARD_BOOT
:= 0
194 # Build option to choose whether Trusted Firmware uses Coherent memory or not.
195 USE_COHERENT_MEM
:= 1
197 # Build option to choose whether Trusted Firmware uses library at ROM
200 # Use tbbr_oid.h instead of platform_oid.h
206 # Whether to enable D-Cache early during warm boot. This is usually
207 # applicable for platforms wherein interconnect programming is not
208 # required to enable cache coherency after warm reset (eg: single cluster
210 WARMBOOT_ENABLE_DCACHE_EARLY
:= 0
212 # Build option to enable/disable the Statistical Profiling Extensions
213 ENABLE_SPE_FOR_LOWER_ELS
:= 1
215 # SPE is only supported on AArch64 so disable it on AArch32.
216 ifeq (${ARCH},aarch32
)
217 override ENABLE_SPE_FOR_LOWER_ELS
:= 0
220 # Include Memory Tagging Extension registers in cpu context. This must be set
221 # to 1 if the platform wants to use this feature in the Secure world and MTE is
223 CTX_INCLUDE_MTE_REGS
:= 0
227 # By default, enable Scalable Vector Extension if implemented for Non-secure
229 # Note SVE is only supported on AArch64 - therefore do not enable in AArch32
230 ifneq (${ARCH},aarch32
)
231 ENABLE_SVE_FOR_NS
:= 1
233 override ENABLE_SVE_FOR_NS
:= 0
238 # For ARMv8.1 (AArch64) platforms, enabling this option selects the spinlock
239 # implementation variant using the ARMv8.1-LSE compare-and-swap instruction.
241 USE_SPINLOCK_CAS
:= 0