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some additions to the ar7 system code, added cpmac network driver
[openwrt/staging/mkresin.git] / openwrt / target / linux / linux-2.4 / patches / ar7 / 000-ar7_support.patch
1 diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S
2 --- linux.old/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100
3 +++ linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-07-09 08:00:15.286026000 +0200
4 @@ -0,0 +1,69 @@
5 +#include <linux/config.h>
6 +#include <linux/threads.h>
7 +
8 +#include <asm/asm.h>
9 +#include <asm/cacheops.h>
10 +#include <asm/current.h>
11 +#include <asm/offset.h>
12 +#include <asm/processor.h>
13 +#include <asm/regdef.h>
14 +#include <asm/cachectl.h>
15 +#include <asm/mipsregs.h>
16 +#include <asm/stackframe.h>
17 +
18 +.text
19 +
20 +.set noreorder
21 +.set noat
22 +
23 +/* TLB Miss Vector */
24 +
25 +LEAF(jump_tlb_miss)
26 + .set mips2
27 + lui k0,0x9400
28 + ori k0,0
29 + jr k0
30 + nop
31 +END(jump_tlb_miss)
32 +
33 + /* Unused TLB Miss Vector */
34 +
35 +LEAF(jump_tlb_miss_unused)
36 + .set mips2
37 + lui k0,0x9400
38 + ori k0,0x80
39 + jr k0
40 + nop
41 +END(jump_tlb_miss_unused)
42 +
43 + /* Cache Error Vector */
44 +
45 +LEAF(jump_cache_error)
46 + .set mips2
47 + lui k0,0x9400
48 + ori k0,0x100
49 + jr k0
50 + nop
51 +END(jump_cache_error)
52 +
53 + /* General Exception */
54 +
55 +LEAF(jump_general_exception)
56 + .set mips2
57 + lui k0,0x9400
58 + ori k0,0x180
59 + jr k0
60 + nop
61 +END(jump_general_exception)
62 +
63 + /* Dedicated Interrupt */
64 +
65 +LEAF(jump_dedicated_interrupt)
66 + .set mips2
67 + lui k0,0x9400
68 + ori k0,0x200
69 + jr k0
70 + nop
71 +END(jump_dedicated_interrupt)
72 +
73 + .set at
74 diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_misc.c linux.dev/arch/mips/ar7/avalanche/avalanche_misc.c
75 --- linux.old/arch/mips/ar7/avalanche/avalanche_misc.c 1970-01-01 01:00:00.000000000 +0100
76 +++ linux.dev/arch/mips/ar7/avalanche/avalanche_misc.c 2005-07-09 08:00:15.287026000 +0200
77 @@ -0,0 +1,327 @@
78 +#include <asm/ar7/sangam.h>
79 +#include <asm/ar7/avalanche_misc.h>
80 +#include <linux/module.h>
81 +#include <linux/spinlock.h>
82 +
83 +static unsigned int avalanche_vbus_freq;
84 +
85 +REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL;
86 +
87 +/*****************************************************************************
88 + * Reset Control Module.
89 + *****************************************************************************/
90 +void avalanche_reset_ctrl(unsigned int module_reset_bit,
91 + AVALANCHE_RESET_CTRL_T reset_ctrl)
92 +{
93 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
94 +
95 + if(module_reset_bit >= 32 && module_reset_bit < 64)
96 + return;
97 +
98 + if(module_reset_bit >= 64)
99 + {
100 + if(p_remote_vlynq_dev_reset_ctrl)
101 + return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl));
102 + else
103 + return;
104 + }
105 +
106 + if(reset_ctrl == OUT_OF_RESET)
107 + *reset_reg |= 1 << module_reset_bit;
108 + else
109 + *reset_reg &= ~(1 << module_reset_bit);
110 +}
111 +
112 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit)
113 +{
114 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
115 +
116 + return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET );
117 +}
118 +
119 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode)
120 +{
121 + volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR;
122 + *sw_reset_reg = mode;
123 +}
124 +
125 +#define AVALANCHE_RST_CTRL_RSR_MASK 0x3
126 +
127 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status()
128 +{
129 + volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR;
130 +
131 + return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) );
132 +}
133 +
134 +
135 +/*****************************************************************************
136 + * Power Control Module
137 + *****************************************************************************/
138 +#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
139 +#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
140 +
141 +
142 +void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl)
143 +{
144 + volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
145 +
146 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
147 + /* power down the module */
148 + *power_reg |= (1 << module_power_bit);
149 + else
150 + /* power on the module */
151 + *power_reg &= (~(1 << module_power_bit));
152 +}
153 +
154 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit)
155 +{
156 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
157 +
158 + return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP);
159 +}
160 +
161 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode)
162 +{
163 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
164 +
165 + *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK;
166 + *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT);
167 +}
168 +
169 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void)
170 +{
171 + volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR;
172 +
173 + return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK))
174 + >> AVALANCHE_GLOBAL_POWER_DOWN_BIT));
175 +}
176 +
177 +#if defined (CONFIG_AVALANCHE_GENERIC_GPIO)
178 +/*****************************************************************************
179 + * GPIO Control
180 + *****************************************************************************/
181 +
182 +/****************************************************************************
183 + * FUNCTION: avalanche_gpio_init
184 + ***************************************************************************/
185 +void avalanche_gpio_init(void)
186 +{
187 + spinlock_t closeLock;
188 + unsigned int closeFlag;
189 + volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR;
190 + spin_lock_irqsave(&closeLock, closeFlag);
191 + *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT);
192 + spin_unlock_irqrestore(&closeLock, closeFlag);
193 +}
194 +
195 +/****************************************************************************
196 + * FUNCTION: avalanche_gpio_ctrl
197 + ***************************************************************************/
198 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
199 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
200 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction)
201 +{
202 + spinlock_t closeLock;
203 + unsigned int closeFlag;
204 + volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL;
205 +
206 + if(gpio_pin >= 32)
207 + return(-1);
208 +
209 + spin_lock_irqsave(&closeLock, closeFlag);
210 +
211 + if(pin_mode == GPIO_PIN)
212 + {
213 + *gpio_ctrl |= (1 << gpio_pin);
214 +
215 + gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR;
216 +
217 + if(pin_direction == GPIO_INPUT_PIN)
218 + *gpio_ctrl |= (1 << gpio_pin);
219 + else
220 + *gpio_ctrl &= ~(1 << gpio_pin);
221 + }
222 + else /* FUNCTIONAL PIN */
223 + {
224 + *gpio_ctrl &= ~(1 << gpio_pin);
225 + }
226 +
227 + spin_unlock_irqrestore(&closeLock, closeFlag);
228 +
229 + return (0);
230 +}
231 +
232 +/****************************************************************************
233 + * FUNCTION: avalanche_gpio_out
234 + ***************************************************************************/
235 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value)
236 +{
237 + spinlock_t closeLock;
238 + unsigned int closeFlag;
239 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
240 +
241 + if(gpio_pin >= 32)
242 + return(-1);
243 +
244 + spin_lock_irqsave(&closeLock, closeFlag);
245 + if(value == TRUE)
246 + *gpio_out |= 1 << gpio_pin;
247 + else
248 + *gpio_out &= ~(1 << gpio_pin);
249 + spin_unlock_irqrestore(&closeLock, closeFlag);
250 +
251 + return(0);
252 +}
253 +
254 +/****************************************************************************
255 + * FUNCTION: avalanche_gpio_in
256 + ***************************************************************************/
257 +int avalanche_gpio_in_bit(unsigned int gpio_pin)
258 +{
259 + spinlock_t closeLock;
260 + unsigned int closeFlag;
261 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
262 + int ret_val = 0;
263 +
264 + if(gpio_pin >= 32)
265 + return(-1);
266 +
267 + spin_lock_irqsave(&closeLock, closeFlag);
268 + ret_val = ((*gpio_in) & (1 << gpio_pin));
269 + spin_unlock_irqrestore(&closeLock, closeFlag);
270 +
271 + return (ret_val);
272 +}
273 +
274 +/****************************************************************************
275 + * FUNCTION: avalanche_gpio_out_val
276 + ***************************************************************************/
277 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask,
278 + unsigned int reg_index)
279 +{
280 + spinlock_t closeLock;
281 + unsigned int closeFlag;
282 + volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT;
283 +
284 + if(reg_index > 0)
285 + return(-1);
286 +
287 + spin_lock_irqsave(&closeLock, closeFlag);
288 + *gpio_out &= ~out_mask;
289 + *gpio_out |= out_val;
290 + spin_unlock_irqrestore(&closeLock, closeFlag);
291 +
292 + return(0);
293 +}
294 +
295 +/****************************************************************************
296 + * FUNCTION: avalanche_gpio_in_value
297 + ***************************************************************************/
298 +int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index)
299 +{
300 + spinlock_t closeLock;
301 + unsigned int closeFlag;
302 + volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN;
303 +
304 + if(reg_index > 0)
305 + return(-1);
306 +
307 + spin_lock_irqsave(&closeLock, closeFlag);
308 + *in_val = *gpio_in;
309 + spin_unlock_irqrestore(&closeLock, closeFlag);
310 +
311 + return (0);
312 +}
313 +
314 +#endif
315 +
316 +/***********************************************************************
317 + *
318 + * Wakeup Control Module for TNETV1050 Communication Processor
319 + *
320 + ***********************************************************************/
321 +
322 +#define AVALANCHE_WAKEUP_POLARITY_BIT 16
323 +
324 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
325 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
326 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity)
327 +{
328 + volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR;
329 +
330 + /* enable/disable */
331 + if (wakeup_ctrl == WAKEUP_ENABLED)
332 + /* enable wakeup */
333 + *wakeup_status_reg |= wakeup_int;
334 + else
335 + /* disable wakeup */
336 + *wakeup_status_reg &= (~wakeup_int);
337 +
338 + /* set polarity */
339 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
340 + *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
341 + else
342 + *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT);
343 +}
344 +
345 +void avalanche_set_vbus_freq(unsigned int new_vbus_freq)
346 +{
347 + avalanche_vbus_freq = new_vbus_freq;
348 +}
349 +
350 +unsigned int avalanche_get_vbus_freq()
351 +{
352 + return(avalanche_vbus_freq);
353 +}
354 +
355 +unsigned int avalanche_get_chip_version_info()
356 +{
357 + return(*(volatile unsigned int*)AVALANCHE_CVR);
358 +}
359 +
360 +SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL;
361 +
362 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation)
363 +{
364 + if(p_set_mdix_on_chip_fn)
365 + return (p_set_mdix_on_chip_fn(base_addr, operation));
366 + else
367 + return(-1);
368 +}
369 +
370 +unsigned int avalanche_is_mdix_on_chip(void)
371 +{
372 + return(p_set_mdix_on_chip_fn ? 1:0);
373 +}
374 +
375 +/* software abstraction for HAL */
376 +
377 +
378 +EXPORT_SYMBOL(avalanche_reset_ctrl);
379 +EXPORT_SYMBOL(avalanche_get_reset_status);
380 +EXPORT_SYMBOL(avalanche_sys_reset);
381 +EXPORT_SYMBOL(avalanche_get_sys_last_reset_status);
382 +EXPORT_SYMBOL(avalanche_power_ctrl);
383 +EXPORT_SYMBOL(avalanche_get_power_status);
384 +EXPORT_SYMBOL(avalanche_set_global_power_mode);
385 +EXPORT_SYMBOL(avalanche_get_global_power_mode);
386 +EXPORT_SYMBOL(avalanche_set_mdix_on_chip);
387 +EXPORT_SYMBOL(avalanche_is_mdix_on_chip);
388 +
389 +
390 +
391 +#if defined (CONFIG_AVALANCHE_GENERIC_GPIO)
392 +EXPORT_SYMBOL(avalanche_gpio_init);
393 +EXPORT_SYMBOL(avalanche_gpio_ctrl);
394 +EXPORT_SYMBOL(avalanche_gpio_out_bit);
395 +EXPORT_SYMBOL(avalanche_gpio_in_bit);
396 +EXPORT_SYMBOL(avalanche_gpio_out_value);
397 +EXPORT_SYMBOL(avalanche_gpio_in_value);
398 +#endif
399 +
400 +EXPORT_SYMBOL(avalanche_set_vbus_freq);
401 +EXPORT_SYMBOL(avalanche_get_vbus_freq);
402 +
403 +EXPORT_SYMBOL(avalanche_get_chip_version_info);
404 +
405 diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c
406 --- linux.old/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100
407 +++ linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-07-09 08:00:15.287026000 +0200
408 @@ -0,0 +1,314 @@
409 +/*
410 + * -*- linux-c -*-
411 + * This file is subject to the terms and conditions of the GNU General Public
412 + * License. See the file "COPYING" in the main directory of this archive
413 + * for more details.
414 + *
415 + * Copyright (C) 2002 by Jeff Harrell (jharrell@ti.com)
416 + * Copyright (C) 2002 Texas Instruments, Inc.
417 + *
418 + */
419 +
420 +/*
421 + * This file takes care of the "memory hole" issue that exists with the standard
422 + * linux kernel and the TI Avalanche ASIC. The Avalanche ASIC requires an offset
423 + * of 0x14000000 due to the ASIC's memory map constraints. This file corrects the
424 + * paging tables so that the only reflect valid memory (i.e. > 0x14000000)
425 + *
426 + * -JAH
427 + */
428 +#include <linux/config.h>
429 +#include <linux/signal.h>
430 +#include <linux/sched.h>
431 +#include <linux/kernel.h>
432 +#include <linux/errno.h>
433 +#include <linux/string.h>
434 +#include <linux/types.h>
435 +#include <linux/ptrace.h>
436 +#include <linux/mman.h>
437 +#include <linux/mm.h>
438 +#include <linux/swap.h>
439 +#include <linux/smp.h>
440 +#include <linux/init.h>
441 +#ifdef CONFIG_BLK_DEV_INITRD
442 +#include <linux/blk.h>
443 +#endif /* CONFIG_BLK_DEV_INITRD */
444 +#include <linux/highmem.h>
445 +#include <linux/bootmem.h>
446 +
447 +#include <asm/processor.h>
448 +#include <asm/system.h>
449 +#include <asm/uaccess.h>
450 +#include <asm/pgtable.h>
451 +#include <asm/pgalloc.h>
452 +#include <asm/mmu_context.h>
453 +#include <asm/io.h>
454 +#include <asm/tlb.h>
455 +#include <asm/cpu.h>
456 +
457 +#define __MEMORY_START CONFIG_AR7_MEMORY
458 +
459 +#ifdef CONFIG_DISCONTIGMEM
460 +pg_data_t discontig_page_data[NR_NODES];
461 +bootmem_data_t discontig_node_bdata[NR_NODES];
462 +#endif
463 +
464 +static unsigned long totalram_pages;
465 +/* static unsigned long totalhigh_pages; */
466 +
467 +#define START_PFN (NODE_DATA(0)->bdata->node_boot_start >> PAGE_SHIFT)
468 +#define MAX_LOW_PFN (NODE_DATA(0)->bdata->node_low_pfn)
469 +
470 +#define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
471 +#define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
472 +#define PFN_PHYS(x) ((x) << PAGE_SHIFT)
473 +
474 +unsigned long bootmap_size;
475 +
476 +extern char *prom_getenv(char *envname);
477 +
478 +/*
479 + * We have upto 8 empty zeroed pages so we can map one of the right colour
480 + * when needed. This is necessary only on R4000 / R4400 SC and MC versions
481 + * where we have to avoid VCED / VECI exceptions for good performance at
482 + * any price. Since page is never written to after the initialization we
483 + * don't have to care about aliases on other CPUs.
484 + */
485 +
486 +static inline unsigned long setup_zero_pages(void)
487 +{
488 + unsigned long order, size;
489 + struct page *page;
490 + if(current_cpu_data.options & MIPS_CPU_VCE)
491 + order = 3;
492 + else
493 + order = 0;
494 +
495 + empty_zero_page = __get_free_pages(GFP_KERNEL, order);
496 +
497 + if (!empty_zero_page)
498 + panic("Oh boy, that early out of memory?");
499 +
500 + page = virt_to_page(empty_zero_page);
501 +
502 + while (page < virt_to_page(empty_zero_page + (PAGE_SIZE << order))) {
503 + set_bit(PG_reserved, &page->flags);
504 + set_page_count(page, 0);
505 + page++;
506 + }
507 +
508 + size = PAGE_SIZE << order;
509 + zero_page_mask = (size - 1) & PAGE_MASK;
510 + memset((void *)empty_zero_page, 0, size);
511 +
512 + return 1UL << order;
513 +}
514 +
515 +/*
516 + * paging_init() sets up the page tables
517 + *
518 + * This routines also unmaps the page at virtual kernel address 0, so
519 + * that we can trap those pesky NULL-reference errors in the kernel.
520 + */
521 +void __init paging_init(void)
522 +{
523 + unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
524 + unsigned long low, start_pfn;
525 +
526 + /* Initialize the entire pgd. */
527 + pgd_init((unsigned long)swapper_pg_dir);
528 + pgd_init((unsigned long)swapper_pg_dir + PAGE_SIZE / 2);
529 +
530 +
531 + start_pfn = START_PFN;
532 + // max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT;
533 + low = MAX_LOW_PFN;
534 +
535 + /* Avalanche DMA-able memory 0x14000000+memsize */
536 +
537 + zones_size[ZONE_DMA] = low - start_pfn;
538 +
539 + free_area_init_node(0, NODE_DATA(0), 0, zones_size, __MEMORY_START, 0);
540 +
541 +#ifdef CONFIG_DISCONTIGMEM
542 + zones_size[ZONE_DMA] = __MEMORY_SIZE_2ND >> PAGE_SHIFT;
543 + zones_size[ZONE_NORMAL] = 0;
544 + free_area_init_node(1, NODE_DATA(1), 0, zones_size, __MEMORY_START_2ND, 0);
545 +#endif /* CONFIG_DISCONTIGMEM */
546 +
547 +}
548 +
549 +extern char _ftext, _etext, _fdata, _edata, _end;
550 +extern char __init_begin, __init_end;
551 +
552 +void __init mem_init(void)
553 +{
554 + int codesize, reservedpages, datasize, initsize;
555 + int tmp;
556 +
557 + max_mapnr = num_physpages = MAX_LOW_PFN - START_PFN;
558 + high_memory = (void *)__va(MAX_LOW_PFN * PAGE_SIZE);
559 +
560 + /* free up the memory associated with Adam2 -
561 + * that is the, after the first page that is
562 + * reserved all the way up to the start of the kernel
563 + */
564 + free_bootmem_node(NODE_DATA(0), (__MEMORY_START+PAGE_SIZE),
565 + (__pa(&_ftext))-(__MEMORY_START+PAGE_SIZE) );
566 +
567 + /* this will put all low memory onto the freelists */
568 + totalram_pages += free_all_bootmem_node(NODE_DATA(0));
569 +
570 + /* Setup zeroed pages */
571 + totalram_pages -= setup_zero_pages();
572 +
573 +
574 +#ifdef CONFIG_DISCONTIGMEM
575 + totalram_pages += free_all_bootmem_node(NODE_DATA(1));
576 +#endif
577 + reservedpages = 0;
578 + for (tmp = 0; tmp < num_physpages; tmp++)
579 + /*
580 + * Only count reserved RAM pages
581 + */
582 + if (PageReserved(mem_map+tmp))
583 + reservedpages++;
584 +
585 + codesize = (unsigned long) &_etext - (unsigned long) &_ftext;
586 + datasize = (unsigned long) &_edata - (unsigned long) &_fdata;
587 + initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
588 +
589 + printk("Memory: %luk/%luk available (%dk kernel code, %dk reserved, %dk data, %dk init)\n",
590 + (unsigned long) nr_free_pages() << (PAGE_SHIFT-10),
591 + max_mapnr << (PAGE_SHIFT-10),
592 + codesize >> 10,
593 + reservedpages << (PAGE_SHIFT-10),
594 + datasize >> 10,
595 + initsize >> 10);
596 +
597 +}
598 +
599 +/* fixes paging routines for avalanche (utilized in /arch/mips/kernel/setup.c) */
600 +
601 +void avalanche_bootmem_init(void)
602 +{
603 + unsigned long start_pfn, max_pfn;
604 + unsigned long max_low_pfn;
605 + unsigned int memsize,memory_end,memory_start;
606 + char *memsize_str;
607 +
608 + memsize_str = prom_getenv("memsize");
609 + if (!memsize_str) {
610 + memsize = 0x02000000;
611 + } else {
612 + memsize = simple_strtol(memsize_str, NULL, 0);
613 + }
614 +
615 +
616 + memory_start = (unsigned long)PAGE_OFFSET+__MEMORY_START;
617 + memory_end = memory_start + memsize;
618 +
619 + /*
620 + * Find the highest memory page fram number we have available
621 + */
622 +
623 + max_pfn = PFN_DOWN(__pa(memory_end));
624 +
625 + /*
626 + * Determine the low and high memory ranges
627 + */
628 +
629 + max_low_pfn = max_pfn;
630 +
631 + /*
632 + * Partially used pages are not usable - thus we are
633 + * rounding upwards:
634 + */
635 +
636 + start_pfn = PFN_UP(__pa(&_end));
637 +
638 + /*
639 + * Find a proper area for the bootmem bitmap. After this
640 + * bootstrap step all allocations (until the page allocator is
641 + * intact) must be done via bootmem_alloc().
642 + */
643 +
644 + bootmap_size = init_bootmem_node(NODE_DATA(0), start_pfn,
645 + __MEMORY_START>>PAGE_SHIFT, max_low_pfn);
646 +
647 +
648 + /*
649 + * Register fully available low RAM pages with the bootmem allocator.
650 + */
651 +
652 + {
653 + unsigned long curr_pfn, last_pfn, pages;
654 +
655 + /*
656 + * We are rounding up the start address of usable memory:
657 + */
658 + curr_pfn = PFN_UP(__MEMORY_START);
659 +
660 + /*
661 + * ... and at the end of the usable range downwards:
662 + */
663 + last_pfn = PFN_DOWN(__pa(memory_end));
664 +
665 + if (last_pfn > max_low_pfn)
666 + last_pfn = max_low_pfn;
667 +
668 + pages = last_pfn - curr_pfn;
669 +
670 +
671 + free_bootmem_node(NODE_DATA(0), PFN_PHYS(curr_pfn),
672 + PFN_PHYS(pages));
673 + }
674 +
675 + /*
676 + * Reserve the kernel text and
677 + * Reserve the bootmem bitmap. We do this in two steps (first step
678 + * was init_bootmem()), because this catches the (definitely buggy)
679 + * case of us accidentally initializing the bootmem allocator with
680 + * an invalid RAM area.
681 + */
682 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START+PAGE_SIZE,
683 + (PFN_PHYS(start_pfn)+bootmap_size+PAGE_SIZE-1)-__MEMORY_START);
684 +
685 + /*
686 + * reserve physical page 0 - it's a special BIOS page on many boxes,
687 + * enabling clean reboots, SMP operation, laptop functions.
688 + */
689 + reserve_bootmem_node(NODE_DATA(0), __MEMORY_START, PAGE_SIZE);
690 +}
691 +
692 +extern char __init_begin, __init_end;
693 +
694 +void free_initmem(void)
695 +{
696 + unsigned long addr;
697 + // prom_free_prom_memory ();
698 +
699 + addr = (unsigned long) &__init_begin;
700 + while (addr < (unsigned long) &__init_end) {
701 + ClearPageReserved(virt_to_page(addr));
702 + set_page_count(virt_to_page(addr), 1);
703 + free_page(addr);
704 + totalram_pages++;
705 + addr += PAGE_SIZE;
706 + }
707 + printk("Freeing unused kernel memory: %dk freed\n",
708 + (&__init_end - &__init_begin) >> 10);
709 +}
710 +
711 +void si_meminfo(struct sysinfo *val)
712 +{
713 + val->totalram = totalram_pages;
714 + val->sharedram = 0;
715 + val->freeram = nr_free_pages();
716 + val->bufferram = atomic_read(&buffermem_pages);
717 + val->totalhigh = 0;
718 + val->freehigh = nr_free_highpages();
719 + val->mem_unit = PAGE_SIZE;
720 +
721 + return;
722 +}
723 diff -urN linux.old/arch/mips/ar7/avalanche/Makefile linux.dev/arch/mips/ar7/avalanche/Makefile
724 --- linux.old/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100
725 +++ linux.dev/arch/mips/ar7/avalanche/Makefile 2005-07-09 08:00:15.288026000 +0200
726 @@ -0,0 +1,16 @@
727 +.S.s:
728 + $(CPP) $(AFLAGS) $< -o $*.s
729 +
730 +.S.o:
731 + $(CC) $(AFLAGS) -c $< -o $*.o
732 +
733 +EXTRA_CFLAGS := -DLITTLE_ENDIAN -D_LINK_KSEG0_
734 +
735 +O_TARGET := avalanche.o
736 +
737 +export-objs := avalanche_misc.o
738 +
739 +obj-y += avalanche_paging.o avalanche_jump.o avalanche_misc.o
740 +
741 +include $(TOPDIR)/Rules.make
742 +
743 diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c
744 --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100
745 +++ linux.dev/arch/mips/ar7/cmdline.c 2005-07-09 08:00:15.288026000 +0200
746 @@ -0,0 +1,64 @@
747 +/*
748 + * Carsten Langgaard, carstenl@mips.com
749 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
750 + *
751 + * This program is free software; you can distribute it and/or modify it
752 + * under the terms of the GNU General Public License (Version 2) as
753 + * published by the Free Software Foundation.
754 + *
755 + * This program is distributed in the hope it will be useful, but WITHOUT
756 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
757 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
758 + * for more details.
759 + *
760 + * You should have received a copy of the GNU General Public License along
761 + * with this program; if not, write to the Free Software Foundation, Inc.,
762 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
763 + *
764 + * Kernel command line creation using the prom monitor (YAMON) argc/argv.
765 + */
766 +#include <linux/init.h>
767 +#include <linux/string.h>
768 +
769 +#include <asm/bootinfo.h>
770 +
771 +extern int prom_argc;
772 +extern int *_prom_argv;
773 +
774 +/*
775 + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer.
776 + * This macro take care of sign extension.
777 + */
778 +#define prom_argv(index) ((char *)(((int *)(int)_prom_argv)[(index)]))
779 +
780 +char arcs_cmdline[CL_SIZE];
781 +
782 +char * __init prom_getcmdline(void)
783 +{
784 + return &(arcs_cmdline[0]);
785 +}
786 +
787 +
788 +void __init prom_init_cmdline(void)
789 +{
790 + char *cp;
791 + int actr;
792 +
793 + actr = 1; /* Always ignore argv[0] */
794 +
795 + cp = &(arcs_cmdline[0]);
796 +#ifdef CONFIG_CMDLINE_BOOL
797 + strcpy(cp, CONFIG_CMDLINE);
798 + cp += strlen(CONFIG_CMDLINE);
799 + *cp++ = ' ';
800 +#endif
801 + while(actr < prom_argc) {
802 + strcpy(cp, prom_argv(actr));
803 + cp += strlen(prom_argv(actr));
804 + *cp++ = ' ';
805 + actr++;
806 + }
807 + if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
808 + --cp;
809 + *cp = '\0';
810 +}
811 diff -urN linux.old/arch/mips/ar7/hal/misc.c linux.dev/arch/mips/ar7/hal/misc.c
812 --- linux.old/arch/mips/ar7/hal/misc.c 1970-01-01 01:00:00.000000000 +0100
813 +++ linux.dev/arch/mips/ar7/hal/misc.c 2005-07-09 08:00:15.288026000 +0200
814 @@ -0,0 +1,22 @@
815 +#include <linux/slab.h>
816 +
817 +void *os_platform_malloc(unsigned int size)
818 +{
819 + return kmalloc(size,GFP_KERNEL);
820 +}
821 +
822 +void os_platform_free(void *p)
823 +{
824 + kfree(p);
825 +}
826 +
827 +void *os_platform_memset(void *p, int num, unsigned int size)
828 +{
829 + return memset(p,num,size);
830 +}
831 +
832 +EXPORT_SYMBOL(os_platform_malloc);
833 +EXPORT_SYMBOL(os_platform_free);
834 +EXPORT_SYMBOL(os_platform_memset);
835 +
836 +
837 diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c
838 --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100
839 +++ linux.dev/arch/mips/ar7/init.c 2005-07-09 08:11:36.592452520 +0200
840 @@ -0,0 +1,146 @@
841 +/*
842 + * Carsten Langgaard, carstenl@mips.com
843 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
844 + *
845 + * This program is free software; you can distribute it and/or modify it
846 + * under the terms of the GNU General Public License (Version 2) as
847 + * published by the Free Software Foundation.
848 + *
849 + * This program is distributed in the hope it will be useful, but WITHOUT
850 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
851 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
852 + * for more details.
853 + *
854 + * You should have received a copy of the GNU General Public License along
855 + * with this program; if not, write to the Free Software Foundation, Inc.,
856 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
857 + *
858 + * PROM library initialisation code.
859 + */
860 +#include <linux/config.h>
861 +#include <linux/init.h>
862 +#include <linux/string.h>
863 +#include <linux/kernel.h>
864 +#include <linux/module.h>
865 +
866 +#include <asm/io.h>
867 +#include <asm/mips-boards/prom.h>
868 +#include <asm/mips-boards/generic.h>
869 +
870 +/* Environment variable */
871 +typedef struct {
872 + char *name;
873 + char *val;
874 +} t_env_var;
875 +
876 +int prom_argc;
877 +int *_prom_argv, *_prom_envp;
878 +
879 +/* max # of Adam2 environment variables */
880 +#define MAX_ENV_ENTRY 80
881 +
882 +static t_env_var local_envp[MAX_ENV_ENTRY];
883 +int init_debug = 0;
884 +
885 +char *prom_getenv(char *envname)
886 +{
887 + /*
888 + * Return a pointer to the given environment variable.
889 + * In 64-bit mode: we're using 64-bit pointers, but all pointers
890 + * in the PROM structures are only 32-bit, so we need some
891 + * workarounds, if we are running in 64-bit mode.
892 + */
893 + int i, index=0;
894 + t_env_var *env = (t_env_var *) local_envp;
895 +
896 + i = strlen(envname);
897 + while (env->name) {
898 + if(strncmp(envname, env->name, i) == 0) {
899 + return(env->val);
900 + }
901 + env++;
902 + }
903 +
904 + return NULL;
905 +}
906 +
907 +static inline unsigned char str2hexnum(unsigned char c)
908 +{
909 + if (c >= '0' && c <= '9')
910 + return c - '0';
911 + if (c >= 'a' && c <= 'f')
912 + return c - 'a' + 10;
913 + return 0; /* foo */
914 +}
915 +
916 +static inline void str2eaddr(unsigned char *ea, unsigned char *str)
917 +{
918 + int i;
919 +
920 + for (i = 0; i < 6; i++) {
921 + unsigned char num;
922 +
923 + if((*str == '.') || (*str == ':'))
924 + str++;
925 + num = str2hexnum(*str++) << 4;
926 + num |= (str2hexnum(*str++));
927 + ea[i] = num;
928 + }
929 +}
930 +
931 +int get_ethernet_addr(char *ethernet_addr)
932 +{
933 + char *ethaddr_str;
934 +
935 + ethaddr_str = prom_getenv("ethaddr");
936 + if (!ethaddr_str) {
937 + printk("ethaddr not set in boot prom\n");
938 + return -1;
939 + }
940 + str2eaddr(ethernet_addr, ethaddr_str);
941 +
942 + if (init_debug > 1) {
943 + int i;
944 + printk("get_ethernet_addr: ");
945 + for (i=0; i<5; i++)
946 + printk("%02x:", (unsigned char)*(ethernet_addr+i));
947 + printk("%02x\n", *(ethernet_addr+i));
948 + }
949 +
950 + return 0;
951 +}
952 +
953 +int __init prom_init(int argc, char **argv, char **envp)
954 +{
955 + int i;
956 + t_env_var *env = (t_env_var *) envp;
957 +
958 + prom_argc = argc;
959 + _prom_argv = (int *)argv;
960 + _prom_envp = (int *)envp;
961 +
962 + /* Copy what we need locally so we are not dependent on
963 + * bootloader RAM. In Adam2, the environment parameters
964 + * are in flash but the table that references them is in
965 + * RAM
966 + */
967 + for(i=0; i < MAX_ENV_ENTRY; i++, env++) {
968 + if (env->name) {
969 + local_envp[i].name = env->name;
970 + local_envp[i].val = env->val;
971 + } else {
972 + local_envp[i].name = NULL;
973 + local_envp[i].val = NULL;
974 + }
975 + }
976 +
977 + set_io_port_base(0);
978 +
979 + prom_printf("\nLINUX started...\n");
980 + prom_init_cmdline();
981 + prom_meminit();
982 +
983 + return 0;
984 +}
985 +
986 +EXPORT_SYMBOL(prom_getenv);
987 diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c
988 --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100
989 +++ linux.dev/arch/mips/ar7/irq.c 2005-07-09 08:00:15.289026000 +0200
990 @@ -0,0 +1,669 @@
991 +/*
992 + * Nitin Dhingra, iamnd@ti.com
993 + * Copyright (C) 2002 Texas Instruments, Inc. All rights reserved.
994 + *
995 + * ########################################################################
996 + *
997 + * This program is free software; you can distribute it and/or modify it
998 + * under the terms of the GNU General Public License (Version 2) as
999 + * published by the Free Software Foundation.
1000 + *
1001 + * This program is distributed in the hope it will be useful, but WITHOUT
1002 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1003 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1004 + * for more details.
1005 + *
1006 + * You should have received a copy of the GNU General Public License along
1007 + * with this program; if not, write to the Free Software Foundation, Inc.,
1008 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1009 + *
1010 + * ########################################################################
1011 + *
1012 + * Routines for generic manipulation of the interrupts found on the Texas
1013 + * Instruments avalanche board
1014 + *
1015 + */
1016 +
1017 +#include <linux/config.h>
1018 +#include <linux/init.h>
1019 +#include <linux/sched.h>
1020 +#include <linux/slab.h>
1021 +#include <linux/interrupt.h>
1022 +#include <linux/kernel_stat.h>
1023 +#include <linux/proc_fs.h>
1024 +#include <asm/irq.h>
1025 +#include <asm/mips-boards/prom.h>
1026 +#include <asm/ar7/ar7.h>
1027 +#include <asm/ar7/avalanche_intc.h>
1028 +#include <asm/gdb-stub.h>
1029 +
1030 +
1031 +#define shutdown_avalanche_irq disable_avalanche_irq
1032 +#define mask_and_ack_avalanche_irq disable_avalanche_irq
1033 +
1034 +static unsigned int startup_avalanche_irq(unsigned int irq);
1035 +static void end_avalanche_irq(unsigned int irq);
1036 +void enable_avalanche_irq(unsigned int irq_nr);
1037 +void disable_avalanche_irq(unsigned int irq_nr);
1038 +
1039 +static struct hw_interrupt_type avalanche_irq_type = {
1040 + "TI AVALANCHE",
1041 + startup_avalanche_irq,
1042 + shutdown_avalanche_irq,
1043 + enable_avalanche_irq,
1044 + disable_avalanche_irq,
1045 + mask_and_ack_avalanche_irq,
1046 + end_avalanche_irq,
1047 + NULL
1048 +};
1049 +
1050 +irq_desc_t irq_desc_ti[AVALANCHE_INT_END+1] __cacheline_aligned =
1051 +{ [0 ... AVALANCHE_INT_END] = { 0, &avalanche_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}};
1052 +
1053 +
1054 +unsigned long spurious_count = 0;
1055 +
1056 +struct avalanche_ictrl_regs *avalanche_hw0_icregs; /* Interrupt control regs (primary) */
1057 +struct avalanche_exctrl_regs *avalanche_hw0_ecregs; /* Exception control regs (secondary) */
1058 +struct avalanche_ipace_regs *avalanche_hw0_ipaceregs;
1059 +struct avalanche_channel_int_number *avalanche_hw0_chregs; /* Channel control registers */
1060 +
1061 +extern asmlinkage void mipsIRQ(void);
1062 +
1063 +
1064 +/*
1065 + * The avalanche/MIPS interrupt line numbers are used to represent the
1066 + * interrupts within the irqaction arrays. The index notation is
1067 + * is as follows:
1068 + *
1069 + * 0-7 MIPS CPU Exceptions (HW/SW)
1070 + * 8-47 Primary Interrupts (Avalanche)
1071 + * 48-79 Secondary Interrupts (Avalanche)
1072 + *
1073 + */
1074 +
1075 +
1076 +static struct irqaction *hw0_irq_action_primary[AVINTNUM(AVALANCHE_INT_END_PRIMARY)] =
1077 +{
1078 + NULL, NULL, NULL, NULL,
1079 + NULL, NULL, NULL, NULL,
1080 + NULL, NULL, NULL, NULL,
1081 + NULL, NULL, NULL, NULL,
1082 + NULL, NULL, NULL, NULL,
1083 + NULL, NULL, NULL, NULL,
1084 + NULL, NULL, NULL, NULL,
1085 + NULL, NULL, NULL, NULL,
1086 + NULL, NULL, NULL, NULL,
1087 + NULL, NULL, NULL, NULL
1088 +};
1089 +
1090 +static struct irqaction *hw0_irq_action_secondary[AVINTNUM(AVALANCHE_INT_END_SECONDARY)] =
1091 +{
1092 + NULL, NULL, NULL, NULL,
1093 + NULL, NULL, NULL, NULL,
1094 + NULL, NULL, NULL, NULL,
1095 + NULL, NULL, NULL, NULL,
1096 + NULL, NULL, NULL, NULL,
1097 + NULL, NULL, NULL, NULL,
1098 + NULL, NULL, NULL, NULL,
1099 + NULL, NULL, NULL, NULL
1100 +};
1101 +
1102 +/*
1103 + This remaps interrupts to exist on other channels than the default
1104 + channels. essentially we can use the line # as the index for this
1105 + array
1106 + */
1107 +
1108 +
1109 +static unsigned long line_to_channel[AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1110 +unsigned long uni_secondary_interrupt = 0;
1111 +
1112 +static struct irqaction r4ktimer_action = {
1113 + NULL, 0, 0, "R4000 timer/counter", NULL, NULL,
1114 +};
1115 +
1116 +static struct irqaction *irq_action[8] = {
1117 + NULL, /* SW int 0 */
1118 + NULL, /* SW int 1 */
1119 + NULL, /* HW int 0 */
1120 + NULL,
1121 + NULL,
1122 + NULL, /* HW int 3 */
1123 + NULL, /* HW int 4 */
1124 + &r4ktimer_action /* HW int 5 */
1125 +};
1126 +
1127 +static void end_avalanche_irq(unsigned int irq)
1128 +{
1129 + if (!(irq_desc_ti[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
1130 + enable_avalanche_irq(irq);
1131 +}
1132 +
1133 +void disable_avalanche_irq(unsigned int irq_nr)
1134 +{
1135 + unsigned long flags;
1136 + unsigned long chan_nr=0;
1137 + unsigned long int_bit=0;
1138 +
1139 + if(irq_nr >= AVALANCHE_INT_END)
1140 + {
1141 + printk("whee, invalid irq_nr %d\n", irq_nr);
1142 + panic("IRQ, you lose...");
1143 + }
1144 +
1145 + save_and_cli(flags);
1146 +
1147 +
1148 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
1149 + {
1150 + /* disable mips exception */
1151 +
1152 + int_bit = read_c0_status() & ~(1 << (8+irq_nr));
1153 + change_c0_status(ST0_IM,int_bit);
1154 + restore_flags(flags);
1155 + return;
1156 + }
1157 +
1158 + /* irq_nr represents the line number for the interrupt. We must
1159 + * disable the channel number associated with that line number.
1160 + */
1161 +
1162 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1163 + chan_nr = AVINTNUM(irq_nr); /*CHECK THIS ALSO*/
1164 + else
1165 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];/* WE NEED A LINE TO CHANNEL MAPPING FUNCTION HERE*/
1166 +
1167 + /* disable the interrupt channel bit */
1168 +
1169 + /* primary interrupt #'s 0-31 */
1170 +
1171 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1172 + avalanche_hw0_icregs->intecr1 = (1 << chan_nr);
1173 +
1174 + /* primary interrupt #'s 32-39 */
1175 +
1176 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1177 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1178 + avalanche_hw0_icregs->intecr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1179 +
1180 + else /* secondary interrupt #'s 0-31 */
1181 + avalanche_hw0_ecregs->exiecr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1182 +
1183 + restore_flags(flags);
1184 +}
1185 +
1186 +void enable_avalanche_irq(unsigned int irq_nr)
1187 +{
1188 + unsigned long flags;
1189 + unsigned long chan_nr=0;
1190 + unsigned long int_bit=0;
1191 +
1192 + if(irq_nr > AVALANCHE_INT_END) {
1193 + printk("whee, invalid irq_nr %d\n", irq_nr);
1194 + panic("IRQ, you lose...");
1195 + }
1196 +
1197 + save_and_cli(flags);
1198 +
1199 +
1200 + if(irq_nr < MIPS_EXCEPTION_OFFSET)
1201 + {
1202 + /* Enable MIPS exceptions */
1203 + int_bit = read_c0_status();
1204 + change_c0_status(ST0_IM,int_bit | (1<<(8+irq_nr)));
1205 + restore_flags(flags);
1206 + return;
1207 + }
1208 +
1209 + /* irq_nr represents the line number for the interrupt. We must
1210 + * disable the channel number associated with that line number.
1211 + */
1212 +
1213 + if(irq_nr > AVALANCHE_INT_END_PRIMARY_REG2)
1214 + chan_nr = AVINTNUM(irq_nr);
1215 + else
1216 + chan_nr = line_to_channel[AVINTNUM(irq_nr)];
1217 +
1218 + /* enable the interrupt channel bit */
1219 +
1220 + /* primary interrupt #'s 0-31 */
1221 + if(chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1))
1222 + avalanche_hw0_icregs->intesr1 = (1 << chan_nr);
1223 +
1224 + /* primary interrupt #'s 32 throuth 39 */
1225 + else if ((chan_nr <= AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG2)) &&
1226 + (chan_nr > AVINTNUM(AVALANCHE_INT_END_PRIMARY_REG1)))
1227 + avalanche_hw0_icregs->intesr2 = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1228 +
1229 + else /* secondary interrupt #'s 0-31 */
1230 + avalanche_hw0_ecregs->exiesr = (1 << (chan_nr - AVINTNUM(AVALANCHE_INT_END_PRIMARY)));
1231 +
1232 + restore_flags(flags);
1233 +}
1234 +
1235 +static unsigned int startup_avalanche_irq(unsigned int irq)
1236 +{
1237 + enable_avalanche_irq(irq);
1238 + return 0; /* never anything pending */
1239 +}
1240 +
1241 +
1242 +int get_irq_list(char *buf)
1243 +{
1244 + int i, len = 0;
1245 + int num = 0;
1246 + struct irqaction *action;
1247 +
1248 + for (i = 0; i < MIPS_EXCEPTION_OFFSET; i++, num++)
1249 + {
1250 + action = irq_action[i];
1251 + if (!action)
1252 + continue;
1253 + len += sprintf(buf+len, "%2d: %8d %c %s",
1254 + num, kstat.irqs[0][num],
1255 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
1256 + action->name);
1257 + for (action=action->next; action; action = action->next) {
1258 + len += sprintf(buf+len, ",%s %s",
1259 + (action->flags & SA_INTERRUPT) ? " +" : "",
1260 + action->name);
1261 + }
1262 + len += sprintf(buf+len, " [MIPS interrupt]\n");
1263 + }
1264 +
1265 +
1266 + for (i = 0; i < AVINTNUM(AVALANCHE_INT_END); i++,num++)
1267 + {
1268 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1269 + action = hw0_irq_action_primary[i];
1270 + else
1271 + action = hw0_irq_action_secondary[i-AVINTNUM(AVALANCHE_INT_END_PRIMARY)];
1272 + if (!action)
1273 + continue;
1274 + len += sprintf(buf+len, "%2d: %8d %c %s",
1275 + num, kstat.irqs[0][ LNXINTNUM(i) ],
1276 + (action->flags & SA_INTERRUPT) ? '+' : ' ',
1277 + action->name);
1278 +
1279 + for (action=action->next; action; action = action->next)
1280 + {
1281 + len += sprintf(buf+len, ",%s %s",
1282 + (action->flags & SA_INTERRUPT) ? " +" : "",
1283 + action->name);
1284 + }
1285 +
1286 + if(i < AVINTNUM(AVALANCHE_INT_END_PRIMARY))
1287 + len += sprintf(buf+len, " [hw0 (Avalanche Primary)]\n");
1288 + else
1289 + len += sprintf(buf+len, " [hw0 (Avalanche Secondary)]\n");
1290 +
1291 + }
1292 +
1293 + return len;
1294 +}
1295 +
1296 +int request_irq(unsigned int irq,
1297 + void (*handler)(int, void *, struct pt_regs *),
1298 + unsigned long irqflags,
1299 + const char * devname,
1300 + void *dev_id)
1301 +{
1302 + struct irqaction *action;
1303 +
1304 + if (irq > AVALANCHE_INT_END)
1305 + return -EINVAL;
1306 + if (!handler)
1307 + return -EINVAL;
1308 +
1309 + action = (struct irqaction *)kmalloc(sizeof(struct irqaction), GFP_KERNEL);
1310 + if(!action)
1311 + return -ENOMEM;
1312 +
1313 + action->handler = handler;
1314 + action->flags = irqflags;
1315 + action->mask = 0;
1316 + action->name = devname;
1317 + irq_desc_ti[irq].action = action;
1318 + action->dev_id = dev_id;
1319 +
1320 + action->next = 0;
1321 +
1322 + if(irq < MIPS_EXCEPTION_OFFSET)
1323 + {
1324 + irq_action[irq] = action;
1325 + enable_avalanche_irq(irq);
1326 + return 0;
1327 + }
1328 +
1329 + if(irq < AVALANCHE_INT_END_PRIMARY)
1330 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = action;
1331 + else
1332 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = action;
1333 +
1334 + enable_avalanche_irq(irq);
1335 +
1336 + return 0;
1337 +}
1338 +
1339 +void free_irq(unsigned int irq, void *dev_id)
1340 +{
1341 + struct irqaction *action;
1342 +
1343 + if (irq > AVALANCHE_INT_END) {
1344 + printk("Trying to free IRQ%d\n",irq);
1345 + return;
1346 + }
1347 +
1348 + if(irq < MIPS_EXCEPTION_OFFSET)
1349 + {
1350 + action = irq_action[irq];
1351 + irq_action[irq] = NULL;
1352 + irq_desc_ti[irq].action = NULL;
1353 + disable_avalanche_irq(irq);
1354 + kfree(action);
1355 + return;
1356 + }
1357 +
1358 + if(irq < AVALANCHE_INT_END_PRIMARY) {
1359 + action = hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]];
1360 + hw0_irq_action_primary[line_to_channel[AVINTNUM(irq)]] = NULL;
1361 + irq_desc_ti[irq].action = NULL;
1362 + }
1363 + else {
1364 + action = hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY];
1365 + hw0_irq_action_secondary[irq - AVALANCHE_INT_END_PRIMARY] = NULL;
1366 + irq_desc_ti[irq].action = NULL;
1367 + }
1368 +
1369 + disable_avalanche_irq(irq);
1370 + kfree(action);
1371 +}
1372 +
1373 +#ifdef CONFIG_KGDB
1374 +extern void breakpoint(void);
1375 +extern int remote_debug;
1376 +#endif
1377 +
1378 +//void init_IRQ(void) __init;
1379 +void __init init_IRQ(void)
1380 +{
1381 + int i;
1382 +
1383 + avalanche_hw0_icregs = (struct avalanche_ictrl_regs *)AVALANCHE_ICTRL_REGS_BASE;
1384 + avalanche_hw0_ecregs = (struct avalanche_exctrl_regs *)AVALANCHE_ECTRL_REGS_BASE;
1385 + avalanche_hw0_ipaceregs = (struct avalanche_ipace_regs *)AVALANCHE_IPACE_REGS_BASE;
1386 + avalanche_hw0_chregs = (struct avalanche_channel_int_number *)AVALANCHE_CHCTRL_REGS_BASE;
1387 +
1388 + /* Disable interrupts and clear pending
1389 + */
1390 +
1391 + avalanche_hw0_icregs->intecr1 = 0xffffffff; /* disable interrupts 0:31 */
1392 + avalanche_hw0_icregs->intcr1 = 0xffffffff; /* clear interrupts 0:31 */
1393 + avalanche_hw0_icregs->intecr2 = 0xff; /* disable interrupts 32:39 */
1394 + avalanche_hw0_icregs->intcr2 = 0xff; /* clear interrupts 32:39 */
1395 + avalanche_hw0_ecregs->exiecr = 0xffffffff; /* disable secondary interrupts 0:31 */
1396 + avalanche_hw0_ecregs->excr = 0xffffffff; /* clear secondary interrupts 0:31 */
1397 +
1398 +
1399 + // avalanche_hw0_ipaceregs->ipacep = (2*get_avalanche_vbus_freq()/1000000)*4;
1400 + /* hack for speeding up the pacing. */
1401 + printk("the pacing pre-scalar has been set as 600.\n");
1402 + avalanche_hw0_ipaceregs->ipacep = 600;
1403 + /* Channel to line mapping, Line to Channel mapping */
1404 +
1405 + for(i = 0; i < 40; i++)
1406 + avalanche_int_set(i,i);
1407 +
1408 + /* Now safe to set the exception vector. */
1409 + set_except_vector(0, mipsIRQ);
1410 +
1411 + /* Setup the IRQ description array. These will be mapped
1412 + * as flat interrupts numbers. The mapping is as follows
1413 + *
1414 + * 0-7 MIPS CPU Exceptions (HW/SW)
1415 + * 8-46 Primary Interrupts (Avalanche)
1416 + * 47-78 Secondary Interrupts (Avalanche)
1417 + */
1418 +
1419 + for (i = 0; i <= AVALANCHE_INT_END; i++)
1420 + {
1421 + irq_desc_ti[i].status = IRQ_DISABLED;
1422 + irq_desc_ti[i].action = 0;
1423 + irq_desc_ti[i].depth = 1;
1424 + irq_desc_ti[i].handler = &avalanche_irq_type;
1425 + }
1426 +
1427 +#ifdef CONFIG_KGDB
1428 + if (remote_debug)
1429 + {
1430 + set_debug_traps();
1431 + breakpoint();
1432 + }
1433 +#endif
1434 +}
1435 +
1436 +
1437 +void avalanche_hw0_irqdispatch(struct pt_regs *regs)
1438 +{
1439 + struct irqaction *action;
1440 + int irq, cpu = smp_processor_id();
1441 + unsigned long int_line_number,status;
1442 + int i,secondary = 0;
1443 + int chan_nr=0;
1444 +
1445 + int_line_number = ((avalanche_hw0_icregs->pintir >> 16) & 0x3F);
1446 + chan_nr = ((avalanche_hw0_icregs->pintir) & 0x3F);
1447 +
1448 +
1449 + if(chan_nr < 32)
1450 + {
1451 + if( chan_nr != uni_secondary_interrupt)
1452 + avalanche_hw0_icregs->intcr1 = (1<<chan_nr);
1453 +
1454 + }
1455 +
1456 + if((chan_nr < 40) && (chan_nr > 31))
1457 + {
1458 + avalanche_hw0_icregs->intcr2 = (1<<(chan_nr-AVINTNUM(AVALANCHE_INT_END_SECONDARY)));
1459 + }
1460 +
1461 +
1462 + /* If the Priority Interrupt Index Register returns 40 then no
1463 + * interrupts are pending
1464 + */
1465 +
1466 + if(chan_nr == 40)
1467 + return;
1468 +
1469 + if(chan_nr == uni_secondary_interrupt)
1470 + {
1471 + status = avalanche_hw0_ecregs->exsr;
1472 + for(i=0; i < AVINTNUM(AVALANCHE_INT_END_SECONDARY); i++)
1473 + {
1474 + if (status & 1<<i)
1475 + {
1476 + /* clear secondary interrupt */
1477 + avalanche_hw0_ecregs->excr = 1 << i;
1478 + break;
1479 + }
1480 + }
1481 + irq = i;
1482 + secondary = 1;
1483 +
1484 + /* clear the universal secondary interrupt */
1485 + avalanche_hw0_icregs->intcr1 = 1 << uni_secondary_interrupt;
1486 +
1487 + }
1488 + else
1489 + irq = chan_nr;
1490 +
1491 + /* Suraj Add code to clear secondary interrupt */
1492 +
1493 + if(secondary)
1494 + action = hw0_irq_action_secondary[irq];
1495 + else
1496 + action = hw0_irq_action_primary[irq];
1497 +
1498 + /* if action == NULL, then we don't have a handler for the irq */
1499 +
1500 + if ( action == NULL ) {
1501 + printk("No handler for hw0 irq: %i\n", irq);
1502 + return;
1503 + }
1504 +
1505 + irq_enter(cpu,irq);
1506 + if(secondary)
1507 + {
1508 + kstat.irqs[0][(irq + AVINTNUM(AVALANCHE_INT_END_PRIMARY)) + 8]++;
1509 + action->handler((irq + AVALANCHE_INT_END_PRIMARY), action->dev_id, regs);
1510 + }
1511 + else
1512 + {
1513 + kstat.irqs[0][irq + 8]++;
1514 + action->handler(LNXINTNUM(irq), action->dev_id, regs);
1515 + }
1516 +
1517 + irq_exit(cpu,irq);
1518 +
1519 + if(softirq_pending(cpu))
1520 + do_softirq();
1521 +
1522 + return;
1523 +}
1524 +
1525 +void avalanche_int_set(int channel, int line)
1526 +{
1527 + switch(channel)
1528 + {
1529 + case(0):
1530 + avalanche_hw0_chregs->cintnr0 = line;
1531 + break;
1532 + case(1):
1533 + avalanche_hw0_chregs->cintnr1 = line;
1534 + break;
1535 + case(2):
1536 + avalanche_hw0_chregs->cintnr2 = line;
1537 + break;
1538 + case(3):
1539 + avalanche_hw0_chregs->cintnr3 = line;
1540 + break;
1541 + case(4):
1542 + avalanche_hw0_chregs->cintnr4 = line;
1543 + break;
1544 + case(5):
1545 + avalanche_hw0_chregs->cintnr5 = line;
1546 + break;
1547 + case(6):
1548 + avalanche_hw0_chregs->cintnr6 = line;
1549 + break;
1550 + case(7):
1551 + avalanche_hw0_chregs->cintnr7 = line;
1552 + break;
1553 + case(8):
1554 + avalanche_hw0_chregs->cintnr8 = line;
1555 + break;
1556 + case(9):
1557 + avalanche_hw0_chregs->cintnr9 = line;
1558 + break;
1559 + case(10):
1560 + avalanche_hw0_chregs->cintnr10 = line;
1561 + break;
1562 + case(11):
1563 + avalanche_hw0_chregs->cintnr11 = line;
1564 + break;
1565 + case(12):
1566 + avalanche_hw0_chregs->cintnr12 = line;
1567 + break;
1568 + case(13):
1569 + avalanche_hw0_chregs->cintnr13 = line;
1570 + break;
1571 + case(14):
1572 + avalanche_hw0_chregs->cintnr14 = line;
1573 + break;
1574 + case(15):
1575 + avalanche_hw0_chregs->cintnr15 = line;
1576 + break;
1577 + case(16):
1578 + avalanche_hw0_chregs->cintnr16 = line;
1579 + break;
1580 + case(17):
1581 + avalanche_hw0_chregs->cintnr17 = line;
1582 + break;
1583 + case(18):
1584 + avalanche_hw0_chregs->cintnr18 = line;
1585 + break;
1586 + case(19):
1587 + avalanche_hw0_chregs->cintnr19 = line;
1588 + break;
1589 + case(20):
1590 + avalanche_hw0_chregs->cintnr20 = line;
1591 + break;
1592 + case(21):
1593 + avalanche_hw0_chregs->cintnr21 = line;
1594 + break;
1595 + case(22):
1596 + avalanche_hw0_chregs->cintnr22 = line;
1597 + break;
1598 + case(23):
1599 + avalanche_hw0_chregs->cintnr23 = line;
1600 + break;
1601 + case(24):
1602 + avalanche_hw0_chregs->cintnr24 = line;
1603 + break;
1604 + case(25):
1605 + avalanche_hw0_chregs->cintnr25 = line;
1606 + break;
1607 + case(26):
1608 + avalanche_hw0_chregs->cintnr26 = line;
1609 + break;
1610 + case(27):
1611 + avalanche_hw0_chregs->cintnr27 = line;
1612 + break;
1613 + case(28):
1614 + avalanche_hw0_chregs->cintnr28 = line;
1615 + break;
1616 + case(29):
1617 + avalanche_hw0_chregs->cintnr29 = line;
1618 + break;
1619 + case(30):
1620 + avalanche_hw0_chregs->cintnr30 = line;
1621 + break;
1622 + case(31):
1623 + avalanche_hw0_chregs->cintnr31 = line;
1624 + break;
1625 + case(32):
1626 + avalanche_hw0_chregs->cintnr32 = line;
1627 + break;
1628 + case(33):
1629 + avalanche_hw0_chregs->cintnr33 = line;
1630 + break;
1631 + case(34):
1632 + avalanche_hw0_chregs->cintnr34 = line;
1633 + break;
1634 + case(35):
1635 + avalanche_hw0_chregs->cintnr35 = line;
1636 + break;
1637 + case(36):
1638 + avalanche_hw0_chregs->cintnr36 = line;
1639 + break;
1640 + case(37):
1641 + avalanche_hw0_chregs->cintnr37 = line;
1642 + break;
1643 + case(38):
1644 + avalanche_hw0_chregs->cintnr38 = line;
1645 + break;
1646 + case(39):
1647 + avalanche_hw0_chregs->cintnr39 = line;
1648 + break;
1649 + default:
1650 + printk("Error: Unknown Avalanche interrupt channel\n");
1651 + }
1652 +
1653 + line_to_channel[line] = channel; /* Suraj check */
1654 +
1655 + if (channel == UNIFIED_SECONDARY_INTERRUPT)
1656 + uni_secondary_interrupt = line;
1657 +
1658 +}
1659 +
1660 diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile
1661 --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100
1662 +++ linux.dev/arch/mips/ar7/Makefile 2005-07-09 08:12:52.981839568 +0200
1663 @@ -0,0 +1,14 @@
1664 +.S.s:
1665 + $(CPP) $(AFLAGS) $< -o $*.s
1666 +
1667 +.S.o:
1668 + $(CC) $(AFLAGS) -c $< -o $*.o
1669 +
1670 +O_TARGET := ar7.o
1671 +
1672 +export-objs += tnetd73xx_misc.o init.o
1673 +obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o
1674 +obj-y += tnetd73xx_misc.o
1675 +obj-y += hal/misc.o
1676 +
1677 +include $(TOPDIR)/Rules.make
1678 diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c
1679 --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100
1680 +++ linux.dev/arch/mips/ar7/memory.c 2005-07-09 08:00:15.290026000 +0200
1681 @@ -0,0 +1,130 @@
1682 +/*
1683 + * Carsten Langgaard, carstenl@mips.com
1684 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1685 + *
1686 + * ########################################################################
1687 + *
1688 + * This program is free software; you can distribute it and/or modify it
1689 + * under the terms of the GNU General Public License (Version 2) as
1690 + * published by the Free Software Foundation.
1691 + *
1692 + * This program is distributed in the hope it will be useful, but WITHOUT
1693 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1694 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1695 + * for more details.
1696 + *
1697 + * You should have received a copy of the GNU General Public License along
1698 + * with this program; if not, write to the Free Software Foundation, Inc.,
1699 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1700 + *
1701 + * ########################################################################
1702 + *
1703 + * PROM library functions for acquiring/using memory descriptors given to
1704 + * us from the YAMON.
1705 + *
1706 + */
1707 +#include <linux/config.h>
1708 +#include <linux/init.h>
1709 +#include <linux/mm.h>
1710 +#include <linux/bootmem.h>
1711 +
1712 +#include <asm/bootinfo.h>
1713 +#include <asm/page.h>
1714 +#include <asm/mips-boards/prom.h>
1715 +#include <asm/ar7/ar7.h>
1716 +
1717 +enum yamon_memtypes {
1718 + yamon_dontuse,
1719 + yamon_prom,
1720 + yamon_free,
1721 +};
1722 +struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
1723 +
1724 +/* References to section boundaries */
1725 +extern char _end;
1726 +
1727 +#define PFN_ALIGN(x) (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
1728 +
1729 +
1730 +struct prom_pmemblock * __init prom_getmdesc(void)
1731 +{
1732 + char *memsize_str;
1733 + unsigned int memsize;
1734 +
1735 + memsize_str = prom_getenv("memsize");
1736 + if (!memsize_str) {
1737 + memsize = 0x02000000;
1738 + } else {
1739 + memsize = simple_strtol(memsize_str, NULL, 0);
1740 + }
1741 +
1742 + memset(mdesc, 0, sizeof(mdesc));
1743 +
1744 + mdesc[0].type = yamon_dontuse;
1745 + mdesc[0].base = 0x00000000;
1746 + mdesc[0].size = AVALANCHE_SDRAM_BASE;
1747 +
1748 + mdesc[1].type = yamon_prom;
1749 + mdesc[1].base = AVALANCHE_SDRAM_BASE;
1750 + mdesc[1].size = 0x00020000;
1751 +
1752 + mdesc[2].type = yamon_free;
1753 + mdesc[2].base = AVALANCHE_SDRAM_BASE + 0x00020000;
1754 + mdesc[2].size = (memsize + AVALANCHE_SDRAM_BASE) - mdesc[2].base;
1755 +
1756 + return &mdesc[0];
1757 +}
1758 +
1759 +static int __init prom_memtype_classify (unsigned int type)
1760 +{
1761 + switch (type) {
1762 + case yamon_free:
1763 + return BOOT_MEM_RAM;
1764 + case yamon_prom:
1765 + return BOOT_MEM_ROM_DATA;
1766 + default:
1767 + return BOOT_MEM_RESERVED;
1768 + }
1769 +}
1770 +
1771 +void __init prom_meminit(void)
1772 +{
1773 + struct prom_pmemblock *p;
1774 +
1775 + p = prom_getmdesc();
1776 +
1777 + while (p->size) {
1778 + long type;
1779 + unsigned long base, size;
1780 +
1781 + type = prom_memtype_classify (p->type);
1782 + base = p->base;
1783 + size = p->size;
1784 +
1785 + add_memory_region(base, size, type);
1786 + p++;
1787 + }
1788 +}
1789 +
1790 +void __init prom_free_prom_memory (void)
1791 +{
1792 + int i;
1793 + unsigned long freed = 0;
1794 + unsigned long addr;
1795 +
1796 + for (i = 0; i < boot_mem_map.nr_map; i++) {
1797 + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
1798 + continue;
1799 +
1800 + addr = boot_mem_map.map[i].addr;
1801 + while (addr < boot_mem_map.map[i].addr
1802 + + boot_mem_map.map[i].size) {
1803 + ClearPageReserved(virt_to_page(__va(addr)));
1804 + set_page_count(virt_to_page(__va(addr)), 1);
1805 + free_page((unsigned long)__va(addr));
1806 + addr += PAGE_SIZE;
1807 + freed += PAGE_SIZE;
1808 + }
1809 + }
1810 + printk("Freeing prom memory: %ldkb freed\n", freed >> 10);
1811 +}
1812 diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S
1813 --- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100
1814 +++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-07-09 08:00:15.290026000 +0200
1815 @@ -0,0 +1,120 @@
1816 +/*
1817 + * Carsten Langgaard, carstenl@mips.com
1818 + * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
1819 + *
1820 + * ########################################################################
1821 + *
1822 + * This program is free software; you can distribute it and/or modify it
1823 + * under the terms of the GNU General Public License (Version 2) as
1824 + * published by the Free Software Foundation.
1825 + *
1826 + * This program is distributed in the hope it will be useful, but WITHOUT
1827 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1828 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1829 + * for more details.
1830 + *
1831 + * You should have received a copy of the GNU General Public License along
1832 + * with this program; if not, write to the Free Software Foundation, Inc.,
1833 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1834 + *
1835 + * ########################################################################
1836 + *
1837 + * Interrupt exception dispatch code.
1838 + *
1839 + */
1840 +#include <linux/config.h>
1841 +
1842 +#include <asm/asm.h>
1843 +#include <asm/mipsregs.h>
1844 +#include <asm/regdef.h>
1845 +#include <asm/stackframe.h>
1846 +
1847 +/* A lot of complication here is taken away because:
1848 + *
1849 + * 1) We handle one interrupt and return, sitting in a loop and moving across
1850 + * all the pending IRQ bits in the cause register is _NOT_ the answer, the
1851 + * common case is one pending IRQ so optimize in that direction.
1852 + *
1853 + * 2) We need not check against bits in the status register IRQ mask, that
1854 + * would make this routine slow as hell.
1855 + *
1856 + * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
1857 + * between like BSD spl() brain-damage.
1858 + *
1859 + * Furthermore, the IRQs on the MIPS board look basically (barring software
1860 + * IRQs which we don't use at all and all external interrupt sources are
1861 + * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
1862 + *
1863 + * MIPS IRQ Source
1864 + * -------- ------
1865 + * 0 Software (ignored)
1866 + * 1 Software (ignored)
1867 + * 2 Combined hardware interrupt (hw0)
1868 + * 3 Hardware (ignored)
1869 + * 4 Hardware (ignored)
1870 + * 5 Hardware (ignored)
1871 + * 6 Hardware (ignored)
1872 + * 7 R4k timer (what we use)
1873 + *
1874 + * Note: On the SEAD board thing are a little bit different.
1875 + * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
1876 + * wired to UART1.
1877 + *
1878 + * We handle the IRQ according to _our_ priority which is:
1879 + *
1880 + * Highest ---- R4k Timer
1881 + * Lowest ---- Combined hardware interrupt
1882 + *
1883 + * then we just return, if multiple IRQs are pending then we will just take
1884 + * another exception, big deal.
1885 + */
1886 +
1887 +.text
1888 +.set noreorder
1889 +.set noat
1890 + .align 5
1891 +NESTED(mipsIRQ, PT_SIZE, sp)
1892 + SAVE_ALL
1893 + CLI
1894 + .set at
1895 +
1896 + mfc0 s0, CP0_CAUSE # get irq bits
1897 +
1898 + /* First we check for r4k counter/timer IRQ. */
1899 + andi a0, s0, CAUSEF_IP7
1900 + beq a0, zero, 1f
1901 + andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
1902 +
1903 + /* Wheee, a timer interrupt. */
1904 + move a0, sp
1905 + jal ar7_timer_interrupt
1906 + nop
1907 +
1908 + j ret_from_irq
1909 + nop
1910 +
1911 + 1:
1912 + beq a0, zero, 1f # delay slot, check hw3 interrupt
1913 + nop
1914 +
1915 + /* Wheee, combined hardware level zero interrupt. */
1916 + jal avalanche_hw0_irqdispatch
1917 + move a0, sp # delay slot
1918 +
1919 + j ret_from_irq
1920 + nop # delay slot
1921 +
1922 + 1:
1923 + /*
1924 + * Here by mistake? This is possible, what can happen is that by the
1925 + * time we take the exception the IRQ pin goes low, so just leave if
1926 + * this is the case.
1927 + */
1928 + move a1,s0
1929 + PRINT("Got interrupt: c0_cause = %08x\n")
1930 + mfc0 a1, CP0_EPC
1931 + PRINT("c0_epc = %08x\n")
1932 +
1933 + j ret_from_irq
1934 + nop
1935 +END(mipsIRQ)
1936 diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c
1937 --- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100
1938 +++ linux.dev/arch/mips/ar7/printf.c 2005-07-09 08:00:15.291026000 +0200
1939 @@ -0,0 +1,51 @@
1940 +/*
1941 + * Carsten Langgaard, carstenl@mips.com
1942 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1943 + *
1944 + * This program is free software; you can distribute it and/or modify it
1945 + * under the terms of the GNU General Public License (Version 2) as
1946 + * published by the Free Software Foundation.
1947 + *
1948 + * This program is distributed in the hope it will be useful, but WITHOUT
1949 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1950 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1951 + * for more details.
1952 + *
1953 + * You should have received a copy of the GNU General Public License along
1954 + * with this program; if not, write to the Free Software Foundation, Inc.,
1955 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1956 + *
1957 + * Putting things on the screen/serial line using Adam2 facilities.
1958 + */
1959 +
1960 +#include <linux/config.h>
1961 +#include <linux/init.h>
1962 +#include <linux/kernel.h>
1963 +#include <linux/serial_reg.h>
1964 +#include <linux/spinlock.h>
1965 +#include <asm/io.h>
1966 +#include <asm/serial.h>
1967 +#include <asm/addrspace.h>
1968 +#include <asm/ar7/ar7.h>
1969 +
1970 +static char ppbuf[1024];
1971 +
1972 +void (*prom_print_str)(unsigned int out, char *s, int len);
1973 +
1974 +void prom_printf(char *fmt, ...) __init;
1975 +void prom_printf(char *fmt, ...)
1976 +{
1977 + va_list args;
1978 + int len;
1979 + prom_print_str = (void *)*(unsigned int *)AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR;
1980 +
1981 + va_start(args, fmt);
1982 + vsprintf(ppbuf, fmt, args);
1983 + len = strlen(ppbuf);
1984 +
1985 + prom_print_str(1, ppbuf, len);
1986 +
1987 + va_end(args);
1988 + return;
1989 +
1990 +}
1991 diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c
1992 --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100
1993 +++ linux.dev/arch/mips/ar7/reset.c 2005-07-09 08:00:15.291026000 +0200
1994 @@ -0,0 +1,54 @@
1995 +/*
1996 + * Carsten Langgaard, carstenl@mips.com
1997 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
1998 + *
1999 + * ########################################################################
2000 + *
2001 + * This program is free software; you can distribute it and/or modify it
2002 + * under the terms of the GNU General Public License (Version 2) as
2003 + * published by the Free Software Foundation.
2004 + *
2005 + * This program is distributed in the hope it will be useful, but WITHOUT
2006 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2007 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2008 + * for more details.
2009 + *
2010 + * You should have received a copy of the GNU General Public License along
2011 + * with this program; if not, write to the Free Software Foundation, Inc.,
2012 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2013 + *
2014 + * ########################################################################
2015 + *
2016 + * Reset the MIPS boards.
2017 + *
2018 + */
2019 +#include <linux/config.h>
2020 +
2021 +#include <asm/reboot.h>
2022 +#include <asm/mips-boards/generic.h>
2023 +
2024 +static void ar7_machine_restart(char *command);
2025 +static void ar7_machine_halt(void);
2026 +static void ar7_machine_power_off(void);
2027 +
2028 +static void ar7_machine_restart(char *command)
2029 +{
2030 +
2031 +}
2032 +
2033 +static void ar7_machine_halt(void)
2034 +{
2035 +
2036 +}
2037 +
2038 +static void ar7_machine_power_off(void)
2039 +{
2040 +
2041 +}
2042 +
2043 +void ar7_reboot_setup(void)
2044 +{
2045 + _machine_restart = ar7_machine_restart;
2046 + _machine_halt = ar7_machine_halt;
2047 + _machine_power_off = ar7_machine_power_off;
2048 +}
2049 diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c
2050 --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100
2051 +++ linux.dev/arch/mips/ar7/setup.c 2005-07-09 08:00:15.291026000 +0200
2052 @@ -0,0 +1,167 @@
2053 +/*
2054 + * Carsten Langgaard, carstenl@mips.com
2055 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
2056 + *
2057 + * This program is free software; you can distribute it and/or modify it
2058 + * under the terms of the GNU General Public License (Version 2) as
2059 + * published by the Free Software Foundation.
2060 + *
2061 + * This program is distributed in the hope it will be useful, but WITHOUT
2062 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2063 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2064 + * for more details.
2065 + *
2066 + * You should have received a copy of the GNU General Public License along
2067 + * with this program; if not, write to the Free Software Foundation, Inc.,
2068 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2069 + */
2070 +#include <linux/config.h>
2071 +#include <linux/init.h>
2072 +#include <linux/sched.h>
2073 +#include <linux/mc146818rtc.h>
2074 +#include <linux/ioport.h>
2075 +
2076 +#include <asm/cpu.h>
2077 +#include <asm/bootinfo.h>
2078 +#include <asm/irq.h>
2079 +#include <asm/mips-boards/generic.h>
2080 +#include <asm/mips-boards/prom.h>
2081 +
2082 +#include <asm/dma.h>
2083 +#include <asm/time.h>
2084 +#include <asm/traps.h>
2085 +
2086 +
2087 +#define _LINK_KSEG0_
2088 +#define LITTLE_ENDIAN
2089 +#include <asm/ar7/tnetd73xx.h>
2090 +#include <asm/ar7/tnetd73xx_misc.h>
2091 +
2092 +// Specific for ar7wrd
2093 +unsigned int tnetd73xx_vbus_freq;
2094 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2095 +#define AFECLK_FREQ 35328000
2096 +#define REFCLK_FREQ 25000000
2097 +#define OSC3_FREQ 24000000
2098 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
2099 +
2100 +#if defined(CONFIG_AR7_MARVELL)
2101 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
2102 +#else
2103 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
2104 +#endif
2105 +
2106 +
2107 +#ifdef CONFIG_KGDB
2108 +extern void rs_kgdb_hook(int);
2109 +int remote_debug = 0;
2110 +#endif
2111 +
2112 +extern struct rtc_ops no_rtc_ops;
2113 +
2114 +extern void ar7_reboot_setup(void);
2115 +
2116 +extern void ar7_time_init(void);
2117 +extern void ar7_timer_setup(struct irqaction *irq);
2118 +
2119 +/* maybe some of this is not needed? */
2120 +static void ar7_platform_init(void)
2121 +{
2122 + //tnetd73xx_gpio_init();
2123 +
2124 + tnetd73xx_reset_ctrl(RESET_MODULE_UART0, OUT_OF_RESET);
2125 + //tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
2126 + //REG32_WRITE(TNETD73XX_GPIOENR, 0xf3fc3ff0);
2127 +
2128 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, IN_RESET);
2129 + //tnetd73xx_reset_ctrl(RESET_MODULE_EPHY, OUT_OF_RESET);
2130 +
2131 + tnetd73xx_clkc_init(AFECLK_FREQ, REFCLK_FREQ, OSC3_FREQ);
2132 +
2133 + tnetd73xx_vbus_freq = tnetd73xx_clkc_get_freq(CLKC_SYS) / 2;
2134 +
2135 +#if defined(CONFIG_AR7WRD)
2136 + if(! (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE)) {
2137 + tnetd73xx_clkc_set_freq(CLKC_MIPS, CLK_MHZ(150));
2138 + }
2139 +#endif
2140 +
2141 +}
2142 +
2143 +const char *get_system_type(void)
2144 +{
2145 + return "Texas Instruments AR7";
2146 +}
2147 +
2148 +void __init ar7_setup(void)
2149 +{
2150 +#ifdef CONFIG_KGDB
2151 + int rs_putDebugChar(char);
2152 + char rs_getDebugChar(void);
2153 + extern int (*generic_putDebugChar)(char);
2154 + extern char (*generic_getDebugChar)(void);
2155 +#endif
2156 + char *argptr;
2157 +#ifdef CONFIG_SERIAL_CONSOLE
2158 + argptr = prom_getcmdline();
2159 + if ((argptr = strstr(argptr, "console=")) == NULL) {
2160 + char console[20];
2161 + char *s;
2162 + int i = 0;
2163 +
2164 + s = prom_getenv("modetty0");
2165 + strcpy(console, "38400");
2166 +
2167 + if (s != NULL) {
2168 + while (s[i] >= '0' && s[i] <= '9')
2169 + i++;
2170 +
2171 + if (i > 0) {
2172 + strncpy(console, s, i);
2173 + console[i] = 0;
2174 + }
2175 + }
2176 +
2177 + argptr = prom_getcmdline();
2178 + strcat(argptr, " console=ttyS0,");
2179 + strcat(argptr, console);
2180 + }
2181 +#endif
2182 +
2183 +#ifdef CONFIG_KGDB
2184 + argptr = prom_getcmdline();
2185 + if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) {
2186 + int line;
2187 + argptr += strlen("kgdb=ttyS");
2188 + if (*argptr != '0' && *argptr != '1')
2189 + printk("KGDB: Uknown serial line /dev/ttyS%c, "
2190 + "falling back to /dev/ttyS1\n", *argptr);
2191 + line = *argptr == '0' ? 0 : 1;
2192 + printk("KGDB: Using serial line /dev/ttyS%d for session\n",
2193 + line ? 1 : 0);
2194 +
2195 + rs_kgdb_hook(line);
2196 + generic_putDebugChar = rs_putDebugChar;
2197 + generic_getDebugChar = rs_getDebugChar;
2198 +
2199 + prom_printf("KGDB: Using serial line /dev/ttyS%d for session, "
2200 + "please connect your debugger\n", line ? 1 : 0);
2201 +
2202 + remote_debug = 1;
2203 + /* Breakpoints are in init_IRQ() */
2204 + }
2205 +#endif
2206 +
2207 + argptr = prom_getcmdline();
2208 + if ((argptr = strstr(argptr, "nofpu")) != NULL)
2209 + cpu_data[0].options &= ~MIPS_CPU_FPU;
2210 +
2211 + rtc_ops = &no_rtc_ops;
2212 +
2213 + ar7_platform_init();
2214 +
2215 + ar7_reboot_setup();
2216 +
2217 + board_time_init = ar7_time_init;
2218 + board_timer_setup = ar7_timer_setup;
2219 +}
2220 diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c
2221 --- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100
2222 +++ linux.dev/arch/mips/ar7/time.c 2005-07-09 08:00:15.292025000 +0200
2223 @@ -0,0 +1,125 @@
2224 +/*
2225 + * Carsten Langgaard, carstenl@mips.com
2226 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
2227 + *
2228 + * ########################################################################
2229 + *
2230 + * This program is free software; you can distribute it and/or modify it
2231 + * under the terms of the GNU General Public License (Version 2) as
2232 + * published by the Free Software Foundation.
2233 + *
2234 + * This program is distributed in the hope it will be useful, but WITHOUT
2235 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
2236 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
2237 + * for more details.
2238 + *
2239 + * You should have received a copy of the GNU General Public License along
2240 + * with this program; if not, write to the Free Software Foundation, Inc.,
2241 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
2242 + *
2243 + * ########################################################################
2244 + *
2245 + * Setting up the clock on the MIPS boards.
2246 + *
2247 + */
2248 +
2249 +#include <linux/types.h>
2250 +#include <linux/config.h>
2251 +#include <linux/init.h>
2252 +#include <linux/kernel_stat.h>
2253 +#include <linux/sched.h>
2254 +#include <linux/spinlock.h>
2255 +
2256 +#include <asm/mipsregs.h>
2257 +#include <asm/ptrace.h>
2258 +#include <asm/hardirq.h>
2259 +#include <asm/div64.h>
2260 +
2261 +#include <linux/interrupt.h>
2262 +#include <linux/mc146818rtc.h>
2263 +#include <linux/timex.h>
2264 +
2265 +#include <asm/mips-boards/generic.h>
2266 +#include <asm/mips-boards/prom.h>
2267 +#include <asm/ar7/ar7.h>
2268 +
2269 +extern asmlinkage void mipsIRQ(void);
2270 +
2271 +static unsigned long r4k_offset; /* Amount to increment compare reg each time */
2272 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
2273 +
2274 +#define MIPS_CPU_TIMER_IRQ 7
2275 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
2276 +
2277 +static inline void ack_r4ktimer(unsigned long newval)
2278 +{
2279 + write_c0_compare(newval);
2280 +}
2281 +
2282 +void ar7_timer_interrupt(struct pt_regs *regs)
2283 +{
2284 + int cpu = smp_processor_id();
2285 +
2286 + irq_enter(cpu, MIPS_CPU_TIMER_IRQ);
2287 +
2288 + if (r4k_offset == 0)
2289 + goto null;
2290 +
2291 + do {
2292 + kstat.irqs[cpu][MIPS_CPU_TIMER_IRQ]++;
2293 + do_timer(regs);
2294 + r4k_cur += r4k_offset;
2295 + ack_r4ktimer(r4k_cur);
2296 +
2297 + } while (((unsigned long)read_c0_count()
2298 + - r4k_cur) < 0x7fffffff);
2299 +
2300 + irq_exit(cpu, MIPS_CPU_TIMER_IRQ);
2301 +
2302 + if (softirq_pending(cpu))
2303 + do_softirq();
2304 +
2305 + return;
2306 +
2307 +null:
2308 + ack_r4ktimer(0);
2309 +}
2310 +
2311 +/*
2312 + * Figure out the r4k offset, the amount to increment the compare
2313 + * register for each time tick.
2314 + */
2315 +static unsigned long __init cal_r4koff(void)
2316 +{
2317 + return ((CONFIG_AR7_FREQUENCY*500000)/HZ);
2318 +}
2319 +
2320 +void __init ar7_time_init(void)
2321 +{
2322 + unsigned long flags;
2323 + unsigned int est_freq;
2324 +
2325 + set_except_vector(0, mipsIRQ);
2326 + write_c0_count(0);
2327 +
2328 + printk("calculating r4koff... ");
2329 + r4k_offset = cal_r4koff();
2330 + printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
2331 +
2332 + est_freq = 2*r4k_offset*HZ;
2333 + est_freq += 5000; /* round */
2334 + est_freq -= est_freq%10000;
2335 + printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
2336 + (est_freq%1000000)*100/1000000);
2337 +}
2338 +
2339 +void __init ar7_timer_setup(struct irqaction *irq)
2340 +{
2341 + /* we are using the cpu counter for timer interrupts */
2342 + irq->handler = no_action; /* we use our own handler */
2343 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
2344 +
2345 + r4k_cur = (read_c0_count() + r4k_offset);
2346 + write_c0_compare(r4k_cur);
2347 + set_c0_status(ALLINTS);
2348 +}
2349 diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c
2350 --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100
2351 +++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-07-09 08:19:34.066865376 +0200
2352 @@ -0,0 +1,927 @@
2353 +/******************************************************************************
2354 + * FILE PURPOSE: TNETD73xx Misc modules API Source
2355 + ******************************************************************************
2356 + * FILE NAME: tnetd73xx_misc.c
2357 + *
2358 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
2359 + * FSER Modules API
2360 + * As per TNETD73xx specifications
2361 + *
2362 + * REVISION HISTORY:
2363 + * 27 Nov 02 - Sharath Kumar PSP TII
2364 + * 14 Feb 03 - Anant Gole PSP TII
2365 + *
2366 + * (C) Copyright 2002, Texas Instruments, Inc
2367 + *******************************************************************************/
2368 +
2369 +#define LITTLE_ENDIAN
2370 +#define _LINK_KSEG0_
2371 +
2372 +#include <linux/types.h>
2373 +#include <linux/module.h>
2374 +#include <asm/ar7/tnetd73xx.h>
2375 +#include <asm/ar7/tnetd73xx_misc.h>
2376 +
2377 +/* TNETD73XX Revision */
2378 +u32 tnetd73xx_get_revision(void)
2379 +{
2380 + /* Read Chip revision register - This register is from GPIO module */
2381 + return ( (u32) REG32_DATA(TNETD73XX_CVR));
2382 +}
2383 +
2384 +/*****************************************************************************
2385 + * Reset Control Module
2386 + *****************************************************************************/
2387 +
2388 +
2389 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module, TNETD73XX_RESET_CTRL_T reset_ctrl)
2390 +{
2391 + u32 reset_status;
2392 +
2393 + /* read current reset register */
2394 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2395 +
2396 + if (reset_ctrl == OUT_OF_RESET)
2397 + {
2398 + /* bring module out of reset */
2399 + reset_status |= (1 << reset_module);
2400 + }
2401 + else
2402 + {
2403 + /* put module in reset */
2404 + reset_status &= (~(1 << reset_module));
2405 + }
2406 +
2407 + /* write to the reset register */
2408 + REG32_WRITE(TNETD73XX_RST_CTRL_PRCR, reset_status);
2409 +}
2410 +
2411 +
2412 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status (TNETD73XX_RESET_MODULE_T reset_module)
2413 +{
2414 + u32 reset_status;
2415 +
2416 + REG32_READ(TNETD73XX_RST_CTRL_PRCR, reset_status);
2417 + return ( (reset_status & (1 << reset_module)) ? OUT_OF_RESET : IN_RESET );
2418 +}
2419 +
2420 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode)
2421 +{
2422 + REG32_WRITE(TNETD73XX_RST_CTRL_SWRCR, mode);
2423 +}
2424 +
2425 +#define TNETD73XX_RST_CTRL_RSR_MASK 0x3
2426 +
2427 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status()
2428 +{
2429 + u32 sys_reset_status;
2430 +
2431 + REG32_READ(TNETD73XX_RST_CTRL_RSR, sys_reset_status);
2432 +
2433 + return ( (TNETD73XX_SYS_RESET_STATUS_T) (sys_reset_status & TNETD73XX_RST_CTRL_RSR_MASK) );
2434 +}
2435 +
2436 +
2437 +/*****************************************************************************
2438 + * Power Control Module
2439 + *****************************************************************************/
2440 +#define TNETD73XX_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */
2441 +#define TNETD73XX_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */
2442 +
2443 +
2444 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl)
2445 +{
2446 + u32 power_status;
2447 +
2448 + /* read current power down control register */
2449 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2450 +
2451 + if (power_ctrl == POWER_CTRL_POWER_DOWN)
2452 + {
2453 + /* power down the module */
2454 + power_status |= (1 << power_module);
2455 + }
2456 + else
2457 + {
2458 + /* power on the module */
2459 + power_status &= (~(1 << power_module));
2460 + }
2461 +
2462 + /* write to the reset register */
2463 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2464 +}
2465 +
2466 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module)
2467 +{
2468 + u32 power_status;
2469 +
2470 + /* read current power down control register */
2471 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2472 +
2473 + return ( (power_status & (1 << power_module)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP );
2474 +}
2475 +
2476 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode)
2477 +{
2478 + u32 power_status;
2479 +
2480 + /* read current power down control register */
2481 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2482 +
2483 + power_status &= TNETD73XX_GLOBAL_POWER_DOWN_MASK;
2484 + power_status |= ( power_mode << TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2485 +
2486 + /* write to power down control register */
2487 + REG32_WRITE(TNETD73XX_POWER_CTRL_PDCR, power_status);
2488 +}
2489 +
2490 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode()
2491 +{
2492 + u32 power_status;
2493 +
2494 + /* read current power down control register */
2495 + REG32_READ(TNETD73XX_POWER_CTRL_PDCR, power_status);
2496 +
2497 + power_status &= (~TNETD73XX_GLOBAL_POWER_DOWN_MASK);
2498 + power_status = ( power_status >> TNETD73XX_GLOBAL_POWER_DOWN_BIT);
2499 +
2500 + return ( (TNETD73XX_SYS_POWER_MODE_T) power_status );
2501 +}
2502 +
2503 +
2504 +/*****************************************************************************
2505 + * Wakeup Control
2506 + *****************************************************************************/
2507 +
2508 +#define TNETD73XX_WAKEUP_POLARITY_BIT 16
2509 +
2510 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
2511 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
2512 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity)
2513 +{
2514 + u32 wakeup_status;
2515 +
2516 + /* read the wakeup control register */
2517 + REG32_READ(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2518 +
2519 + /* enable/disable */
2520 + if (wakeup_ctrl == WAKEUP_ENABLED)
2521 + {
2522 + /* enable wakeup */
2523 + wakeup_status |= wakeup_int;
2524 + }
2525 + else
2526 + {
2527 + /* disable wakeup */
2528 + wakeup_status &= (~wakeup_int);
2529 + }
2530 +
2531 + /* set polarity */
2532 + if (wakeup_polarity == WAKEUP_ACTIVE_LOW)
2533 + {
2534 + wakeup_status |= (wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2535 + }
2536 + else
2537 + {
2538 + wakeup_status &= ~(wakeup_int << TNETD73XX_WAKEUP_POLARITY_BIT);
2539 + }
2540 +
2541 + /* write the wakeup control register */
2542 + REG32_WRITE(TNETD73XX_POWER_CTRL_WKCR, wakeup_status);
2543 +}
2544 +
2545 +
2546 +/*****************************************************************************
2547 + * FSER Control
2548 + *****************************************************************************/
2549 +
2550 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode)
2551 +{
2552 + REG32_WRITE(TNETD73XX_FSER_BASE, fser_mode);
2553 +}
2554 +
2555 +/*****************************************************************************
2556 + * Clock Control
2557 + *****************************************************************************/
2558 +
2559 +#define MIN(x,y) ( ((x) < (y)) ? (x) : (y) )
2560 +#define MAX(x,y) ( ((x) > (y)) ? (x) : (y) )
2561 +#define ABS(x) ( ((signed)(x) > 0) ? (x) : (-(x)) )
2562 +#define CEIL(x,y) ( ((x) + (y) / 2) / (y) )
2563 +
2564 +#define CLKC_CLKCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x20 + (0x20 * (x)))
2565 +#define CLKC_CLKPLLCR(x) (TNETD73XX_CLOCK_CTRL_BASE + 0x30 + (0x20 * (x)))
2566 +
2567 +#define CLKC_PRE_DIVIDER 0x0000001F
2568 +#define CLKC_POST_DIVIDER 0x001F0000
2569 +
2570 +#define CLKC_PLL_STATUS 0x1
2571 +#define CLKC_PLL_FACTOR 0x0000F000
2572 +
2573 +#define BOOTCR_PLL_BYPASS (1 << 5)
2574 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
2575 +
2576 +#define MIPS_PLL_SELECT 0x00030000
2577 +#define SYSTEM_PLL_SELECT 0x0000C000
2578 +#define USB_PLL_SELECT 0x000C0000
2579 +#define ADSLSS_PLL_SELECT 0x00C00000
2580 +
2581 +#define MIPS_AFECLKI_SELECT 0x00000000
2582 +#define MIPS_REFCLKI_SELECT 0x00010000
2583 +#define MIPS_XTAL3IN_SELECT 0x00020000
2584 +
2585 +#define SYSTEM_AFECLKI_SELECT 0x00000000
2586 +#define SYSTEM_REFCLKI_SELECT 0x00004000
2587 +#define SYSTEM_XTAL3IN_SELECT 0x00008000
2588 +#define SYSTEM_MIPSPLL_SELECT 0x0000C000
2589 +
2590 +#define USB_SYSPLL_SELECT 0x00000000
2591 +#define USB_REFCLKI_SELECT 0x00040000
2592 +#define USB_XTAL3IN_SELECT 0x00080000
2593 +#define USB_MIPSPLL_SELECT 0x000C0000
2594 +
2595 +#define ADSLSS_AFECLKI_SELECT 0x00000000
2596 +#define ADSLSS_REFCLKI_SELECT 0x00400000
2597 +#define ADSLSS_XTAL3IN_SELECT 0x00800000
2598 +#define ADSLSS_MIPSPLL_SELECT 0x00C00000
2599 +
2600 +#define SYS_MAX CLK_MHZ(150)
2601 +#define SYS_MIN CLK_MHZ(1)
2602 +
2603 +#define MIPS_SYNC_MAX SYS_MAX
2604 +#define MIPS_ASYNC_MAX CLK_MHZ(160)
2605 +#define MIPS_MIN CLK_MHZ(1)
2606 +
2607 +#define USB_MAX CLK_MHZ(100)
2608 +#define USB_MIN CLK_MHZ(1)
2609 +
2610 +#define ADSL_MAX CLK_MHZ(180)
2611 +#define ADSL_MIN CLK_MHZ(1)
2612 +
2613 +#define PLL_MUL_MAXFACTOR 15
2614 +#define MAX_DIV_VALUE 32
2615 +#define MIN_DIV_VALUE 1
2616 +
2617 +#define MIN_PLL_INP_FREQ CLK_MHZ(8)
2618 +#define MAX_PLL_INP_FREQ CLK_MHZ(100)
2619 +
2620 +#define DIVIDER_LOCK_TIME 10100
2621 +#define PLL_LOCK_TIME 10100 * 75
2622 +
2623 +
2624 +
2625 +/****************************************************************************
2626 +* DATA PURPOSE: PRIVATE Variables
2627 +**************************************************************************/
2628 +static u32 *clk_src[4];
2629 +static u32 mips_pll_out;
2630 +static u32 sys_pll_out;
2631 +static u32 afeclk_inp;
2632 +static u32 refclk_inp;
2633 +static u32 xtal_inp;
2634 +static u32 present_min;
2635 +static u32 present_max;
2636 +
2637 +/* Forward References */
2638 +static u32 find_gcd(u32 min, u32 max);
2639 +static u32 compute_prediv( u32 divider, u32 min, u32 max);
2640 +static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider);
2641 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id);
2642 +static void find_approx(u32 *,u32 *,u32);
2643 +
2644 +/****************************************************************************
2645 +* FUNCTION: tnetd73xx_clkc_init
2646 +****************************************************************************
2647 +* Description: The routine initializes the internal variables depending on
2648 +* on the sources selected for different clocks.
2649 +***************************************************************************/
2650 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in)
2651 +{
2652 +
2653 + u32 choice;
2654 +
2655 + afeclk_inp = afeclk;
2656 + refclk_inp = refclk;
2657 + xtal_inp = xtal3in;
2658 +
2659 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & MIPS_PLL_SELECT;
2660 + switch(choice)
2661 + {
2662 + case MIPS_AFECLKI_SELECT:
2663 + clk_src[CLKC_MIPS] = &afeclk_inp;
2664 + break;
2665 +
2666 + case MIPS_REFCLKI_SELECT:
2667 + clk_src[CLKC_MIPS] = &refclk_inp;
2668 + break;
2669 +
2670 + case MIPS_XTAL3IN_SELECT:
2671 + clk_src[CLKC_MIPS] = &xtal_inp;
2672 + break;
2673 +
2674 + default :
2675 + clk_src[CLKC_MIPS] = 0;
2676 +
2677 + }
2678 +
2679 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & SYSTEM_PLL_SELECT;
2680 + switch(choice)
2681 + {
2682 + case SYSTEM_AFECLKI_SELECT:
2683 + clk_src[CLKC_SYS] = &afeclk_inp;
2684 + break;
2685 +
2686 + case SYSTEM_REFCLKI_SELECT:
2687 + clk_src[CLKC_SYS] = &refclk_inp;
2688 + break;
2689 +
2690 + case SYSTEM_XTAL3IN_SELECT:
2691 + clk_src[CLKC_SYS] = &xtal_inp;
2692 + break;
2693 +
2694 + case SYSTEM_MIPSPLL_SELECT:
2695 + clk_src[CLKC_SYS] = &mips_pll_out;
2696 + break;
2697 +
2698 + default :
2699 + clk_src[CLKC_SYS] = 0;
2700 +
2701 + }
2702 +
2703 +
2704 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & ADSLSS_PLL_SELECT;
2705 + switch(choice)
2706 + {
2707 + case ADSLSS_AFECLKI_SELECT:
2708 + clk_src[CLKC_ADSLSS] = &afeclk_inp;
2709 + break;
2710 +
2711 + case ADSLSS_REFCLKI_SELECT:
2712 + clk_src[CLKC_ADSLSS] = &refclk_inp;
2713 + break;
2714 +
2715 + case ADSLSS_XTAL3IN_SELECT:
2716 + clk_src[CLKC_ADSLSS] = &xtal_inp;
2717 + break;
2718 +
2719 + case ADSLSS_MIPSPLL_SELECT:
2720 + clk_src[CLKC_ADSLSS] = &mips_pll_out;
2721 + break;
2722 +
2723 + default :
2724 + clk_src[CLKC_ADSLSS] = 0;
2725 +
2726 + }
2727 +
2728 +
2729 + choice = REG32_DATA(TNETD73XX_DCL_BOOTCR) & USB_PLL_SELECT;
2730 + switch(choice)
2731 + {
2732 + case USB_SYSPLL_SELECT:
2733 + clk_src[CLKC_USB] = &sys_pll_out ;
2734 + break;
2735 +
2736 + case USB_REFCLKI_SELECT:
2737 + clk_src[CLKC_USB] = &refclk_inp;
2738 + break;
2739 +
2740 + case USB_XTAL3IN_SELECT:
2741 + clk_src[CLKC_USB] = &xtal_inp;
2742 + break;
2743 +
2744 + case USB_MIPSPLL_SELECT:
2745 + clk_src[CLKC_USB] = &mips_pll_out;
2746 + break;
2747 +
2748 + default :
2749 + clk_src[CLKC_USB] = 0;
2750 +
2751 + }
2752 +}
2753 +
2754 +
2755 +
2756 +/****************************************************************************
2757 + * FUNCTION: tnetd73xx_clkc_set_freq
2758 + ****************************************************************************
2759 + * Description: The above routine is called to set the output_frequency of the
2760 + * selected clock(using clk_id) to the required value given
2761 + * by the variable output_freq.
2762 + ***************************************************************************/
2763 +TNETD73XX_ERR tnetd73xx_clkc_set_freq
2764 +(
2765 + TNETD73XX_CLKC_ID_T clk_id,
2766 + u32 output_freq
2767 + )
2768 +{
2769 + u32 base_freq;
2770 + u32 multiplier;
2771 + u32 divider;
2772 + u32 min_prediv;
2773 + u32 max_prediv;
2774 + u32 prediv;
2775 + u32 postdiv;
2776 + u32 temp;
2777 +
2778 + /* check if PLLs are bypassed*/
2779 + if(REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS)
2780 + {
2781 + return TNETD73XX_ERR_ERROR;
2782 + }
2783 +
2784 + /*check if the requested output_frequency is in valid range*/
2785 + switch( clk_id )
2786 + {
2787 + case CLKC_SYS:
2788 + if( output_freq < SYS_MIN || output_freq > SYS_MAX)
2789 + {
2790 + return TNETD73XX_ERR_ERROR;
2791 + }
2792 + present_min = SYS_MIN;
2793 + present_max = SYS_MAX;
2794 + break;
2795 +
2796 + case CLKC_MIPS:
2797 + if((output_freq < MIPS_MIN) ||
2798 + (output_freq > ((REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX)))
2799 + {
2800 + return TNETD73XX_ERR_ERROR;
2801 + }
2802 + present_min = MIPS_MIN;
2803 + present_max = (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_MIPS_ASYNC_MODE) ? MIPS_ASYNC_MAX: MIPS_SYNC_MAX;
2804 + break;
2805 +
2806 + case CLKC_USB:
2807 + if( output_freq < USB_MIN || output_freq > USB_MAX)
2808 + {
2809 + return TNETD73XX_ERR_ERROR;
2810 + }
2811 + present_min = USB_MIN;
2812 + present_max = USB_MAX;
2813 + break;
2814 +
2815 + case CLKC_ADSLSS:
2816 + if( output_freq < ADSL_MIN || output_freq > ADSL_MAX)
2817 + {
2818 + return TNETD73XX_ERR_ERROR;
2819 + }
2820 + present_min = ADSL_MIN;
2821 + present_max = ADSL_MAX;
2822 + break;
2823 + }
2824 +
2825 +
2826 + base_freq = get_base_frequency(clk_id);
2827 +
2828 +
2829 + /* check for minimum base frequency value */
2830 + if( base_freq < MIN_PLL_INP_FREQ)
2831 + {
2832 + return TNETD73XX_ERR_ERROR;
2833 + }
2834 +
2835 + get_val(output_freq, base_freq, &multiplier, &divider);
2836 +
2837 + /* check multiplier range */
2838 + if( (multiplier > PLL_MUL_MAXFACTOR) || (multiplier <= 0) )
2839 + {
2840 + return TNETD73XX_ERR_ERROR;
2841 + }
2842 +
2843 + /* check divider value */
2844 + if( divider == 0 )
2845 + {
2846 + return TNETD73XX_ERR_ERROR;
2847 + }
2848 +
2849 + /*compute minimum and maximum predivider values */
2850 + min_prediv = MAX(base_freq / MAX_PLL_INP_FREQ + 1, divider / MAX_DIV_VALUE + 1);
2851 + max_prediv = MIN(base_freq / MIN_PLL_INP_FREQ, MAX_DIV_VALUE);
2852 +
2853 + /*adjust the value of divider so that it not less than minimum predivider value*/
2854 + if (divider < min_prediv)
2855 + {
2856 + temp = CEIL(min_prediv, divider);
2857 + if ((temp * multiplier) > PLL_MUL_MAXFACTOR)
2858 + {
2859 + return TNETD73XX_ERR_ERROR ;
2860 + }
2861 + else
2862 + {
2863 + multiplier = temp * multiplier;
2864 + divider = min_prediv;
2865 + }
2866 +
2867 + }
2868 +
2869 + /* compute predivider and postdivider values */
2870 + prediv = compute_prediv (divider, min_prediv, max_prediv);
2871 + postdiv = CEIL(divider,prediv);
2872 +
2873 + /*return fail if postdivider value falls out of range */
2874 + if(postdiv > MAX_DIV_VALUE)
2875 + {
2876 + return TNETD73XX_ERR_ERROR;
2877 + }
2878 +
2879 +
2880 + /*write predivider and postdivider values*/
2881 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2882 + REG32_WRITE(CLKC_CLKCR(clk_id), ((postdiv -1) & 0x1F) << 16 | ((prediv -1) & 0x1F) );
2883 +
2884 + /*wait for divider output to stabilise*/
2885 + for(temp =0; temp < DIVIDER_LOCK_TIME; temp++);
2886 +
2887 + /*write to PLL clock register*/
2888 +
2889 + if(clk_id == CLKC_SYS)
2890 + {
2891 + /* but before writing put DRAM to hold mode */
2892 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) |= 0x80000000;
2893 + }
2894 + /*Bring PLL into div mode */
2895 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), 0x4);
2896 +
2897 + /*compute the word to be written to PLLCR
2898 + *corresponding to multiplier value
2899 + */
2900 + multiplier = (((multiplier - 1) & 0xf) << 12)| ((255 <<3) | 0x0e);
2901 +
2902 + /* wait till PLL enters div mode */
2903 + while(REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2904 + /*nothing*/;
2905 +
2906 + REG32_WRITE(CLKC_CLKPLLCR(clk_id), multiplier);
2907 +
2908 + while(!REG32_DATA(CLKC_CLKPLLCR(clk_id)) & CLKC_PLL_STATUS)
2909 + /*nothing*/;
2910 +
2911 +
2912 + /*wait for External pll to lock*/
2913 + for(temp =0; temp < PLL_LOCK_TIME; temp++);
2914 +
2915 + if(clk_id == CLKC_SYS)
2916 + {
2917 + /* Bring DRAM out of hold */
2918 + REG32_DATA(TNETD73XX_EMIF_SDRAM_CFG) &= ~0x80000000;
2919 + }
2920 +
2921 + return TNETD73XX_ERR_OK ;
2922 +}
2923 +
2924 +/****************************************************************************
2925 + * FUNCTION: tnetd73xx_clkc_get_freq
2926 + ****************************************************************************
2927 + * Description: The above routine is called to get the output_frequency of the
2928 + * selected clock( clk_id)
2929 + ***************************************************************************/
2930 +u32 tnetd73xx_clkc_get_freq
2931 +(
2932 + TNETD73XX_CLKC_ID_T clk_id
2933 + )
2934 +{
2935 +
2936 + u32 clk_ctrl_register;
2937 + u32 clk_pll_setting;
2938 + u32 clk_predivider;
2939 + u32 clk_postdivider;
2940 + u16 pll_factor;
2941 + u32 base_freq;
2942 + u32 divider;
2943 +
2944 + base_freq = get_base_frequency(clk_id);
2945 +
2946 + clk_ctrl_register = REG32_DATA(CLKC_CLKCR(clk_id));
2947 +
2948 + /* pre-Divider and post-divider are 5 bit N+1 dividers */
2949 + clk_predivider = (CLKC_PRE_DIVIDER & clk_ctrl_register) + 1;
2950 + clk_postdivider = ((CLKC_POST_DIVIDER & clk_ctrl_register) >> 16) + 1;
2951 +
2952 + divider = clk_predivider * clk_postdivider;
2953 +
2954 +
2955 + if( (REG32_DATA(TNETD73XX_DCL_BOOTCR) & BOOTCR_PLL_BYPASS))
2956 + {
2957 + return (CEIL(base_freq, divider)); /* PLLs bypassed.*/
2958 + }
2959 +
2960 +
2961 + else
2962 + {
2963 + /* return the current clock speed based upon the PLL setting */
2964 + clk_pll_setting = REG32_DATA(CLKC_CLKPLLCR(clk_id));
2965 +
2966 + /* Get the PLL multiplication factor */
2967 + pll_factor = ((clk_pll_setting & CLKC_PLL_FACTOR) >> 12) + 1;
2968 +
2969 + /* Check if we're in divide mode or multiply mode */
2970 + if((clk_pll_setting & 0x1) == 0)
2971 + {
2972 + /* We're in divide mode */
2973 + if(pll_factor < 0x10)
2974 + return (CEIL(base_freq >> 1, divider));
2975 + else
2976 + return (CEIL(base_freq >> 2, divider));
2977 + }
2978 +
2979 + else /* We're in PLL mode */
2980 + {
2981 + /* See if PLLNDIV & PLLDIV are set */
2982 + if((clk_pll_setting & 0x0800) && (clk_pll_setting & 0x2))
2983 + {
2984 + if(clk_pll_setting & 0x1000)
2985 + {
2986 + /* clk = base_freq * k/2 */
2987 + return(CEIL((base_freq * pll_factor) >> 1, divider));
2988 + }
2989 + else
2990 + {
2991 + /* clk = base_freq * (k-1) / 4)*/
2992 + return(CEIL((base_freq * (pll_factor - 1)) >>2, divider));
2993 + }
2994 + }
2995 + else
2996 + {
2997 + if(pll_factor < 0x10)
2998 + {
2999 + /* clk = base_freq * k */
3000 + return(CEIL(base_freq * pll_factor, divider));
3001 + }
3002 +
3003 + else
3004 + {
3005 + /* clk = base_freq */
3006 + return(CEIL(base_freq, divider));
3007 + }
3008 + }
3009 + }
3010 + return(0); /* Should never reach here */
3011 +
3012 + }
3013 +
3014 +}
3015 +
3016 +
3017 +/* local helper functions */
3018 +
3019 +/****************************************************************************
3020 + * FUNCTION: get_base_frequency
3021 + ****************************************************************************
3022 + * Description: The above routine is called to get base frequency of the clocks.
3023 + ***************************************************************************/
3024 +
3025 +static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id)
3026 +{
3027 + /* update the current MIPs PLL output value, if the required
3028 + * source is MIPS PLL
3029 + */
3030 + if ( clk_src[clk_id] == &mips_pll_out)
3031 + {
3032 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_MIPS);
3033 + }
3034 +
3035 +
3036 + /* update the current System PLL output value, if the required
3037 + * source is system PLL
3038 + */
3039 + if ( clk_src[clk_id] == &sys_pll_out)
3040 + {
3041 + *clk_src[clk_id] = tnetd73xx_clkc_get_freq(CLKC_SYS);
3042 + }
3043 +
3044 + return (*clk_src[clk_id]);
3045 +
3046 +}
3047 +
3048 +
3049 +
3050 +/****************************************************************************
3051 + * FUNCTION: find_gcd
3052 + ****************************************************************************
3053 + * Description: The above routine is called to find gcd of 2 numbers.
3054 + ***************************************************************************/
3055 +static u32 find_gcd
3056 +(
3057 + u32 min,
3058 + u32 max
3059 + )
3060 +{
3061 + if (max % min == 0)
3062 + {
3063 + return min;
3064 + }
3065 + else
3066 + {
3067 + return find_gcd(max % min, min);
3068 + }
3069 +}
3070 +
3071 +/****************************************************************************
3072 + * FUNCTION: compute_prediv
3073 + ****************************************************************************
3074 + * Description: The above routine is called to compute predivider value
3075 + ***************************************************************************/
3076 +static u32 compute_prediv(u32 divider, u32 min, u32 max)
3077 +{
3078 + u16 prediv;
3079 +
3080 + /* return the divider itself it it falls within the range of predivider*/
3081 + if (min <= divider && divider <= max)
3082 + {
3083 + return divider;
3084 + }
3085 +
3086 + /* find a value for prediv such that it is a factor of divider */
3087 + for (prediv = max; prediv >= min ; prediv--)
3088 + {
3089 + if ( (divider % prediv) == 0 )
3090 + {
3091 + return prediv;
3092 + }
3093 + }
3094 +
3095 + /* No such factor exists, return min as prediv */
3096 + return min;
3097 +}
3098 +
3099 +/****************************************************************************
3100 + * FUNCTION: get_val
3101 + ****************************************************************************
3102 + * Description: This routine is called to get values of divider and multiplier.
3103 + ***************************************************************************/
3104 +
3105 +static void get_val(u32 output_freq, u32 base_freq,u32 *multiplier, u32 *divider)
3106 +{
3107 + u32 temp_mul;
3108 + u32 temp_div;
3109 + u32 gcd;
3110 + u32 min_freq;
3111 + u32 max_freq;
3112 +
3113 + /* find gcd of base_freq, output_freq */
3114 + min_freq = (base_freq < output_freq) ? base_freq : output_freq;
3115 + max_freq = (base_freq > output_freq) ? base_freq : output_freq;
3116 + gcd = find_gcd(min_freq , max_freq);
3117 +
3118 + if(gcd == 0)
3119 + return; /* ERROR */
3120 +
3121 + /* compute values of multiplier and divider */
3122 + temp_mul = output_freq / gcd;
3123 + temp_div = base_freq / gcd;
3124 +
3125 +
3126 + /* set multiplier such that 1 <= multiplier <= PLL_MUL_MAXFACTOR */
3127 + if( temp_mul > PLL_MUL_MAXFACTOR )
3128 + {
3129 + if((temp_mul / temp_div) > PLL_MUL_MAXFACTOR)
3130 + return;
3131 +
3132 + find_approx(&temp_mul,&temp_div,base_freq);
3133 + }
3134 +
3135 + *multiplier = temp_mul;
3136 + *divider = temp_div;
3137 +}
3138 +
3139 +/****************************************************************************
3140 + * FUNCTION: find_approx
3141 + ****************************************************************************
3142 + * Description: This function gets the approx value of num/denom.
3143 + ***************************************************************************/
3144 +
3145 +static void find_approx(u32 *num,u32 *denom,u32 base_freq)
3146 +{
3147 + u32 num1;
3148 + u32 denom1;
3149 + u32 num2;
3150 + u32 denom2;
3151 + int32_t closest;
3152 + int32_t prev_closest;
3153 + u32 temp_num;
3154 + u32 temp_denom;
3155 + u32 normalize;
3156 + u32 gcd;
3157 + u32 output_freq;
3158 +
3159 + num1 = *num;
3160 + denom1 = *denom;
3161 +
3162 + prev_closest = 0x7fffffff; /* maximum possible value */
3163 + num2 = num1;
3164 + denom2 = denom1;
3165 +
3166 + /* start with max */
3167 + for(temp_num = 15; temp_num >=1; temp_num--)
3168 + {
3169 +
3170 + temp_denom = CEIL(temp_num * denom1, num1);
3171 + output_freq = (temp_num * base_freq) / temp_denom;
3172 +
3173 + if(temp_denom < 1)
3174 + {
3175 + break;
3176 + }
3177 + else
3178 + {
3179 + normalize = CEIL(num1,temp_num);
3180 + closest = (ABS((num1 * (temp_denom) ) - (temp_num * denom1))) * normalize;
3181 + if(closest < prev_closest && output_freq > present_min && output_freq <present_max)
3182 + {
3183 + prev_closest = closest;
3184 + num2 = temp_num;
3185 + denom2 = temp_denom;
3186 + }
3187 +
3188 + }
3189 +
3190 + }
3191 +
3192 + gcd = find_gcd(num2,denom2);
3193 + num2 = num2 / gcd;
3194 + denom2 = denom2 /gcd;
3195 +
3196 + *num = num2;
3197 + *denom = denom2;
3198 +}
3199 +
3200 +
3201 +/*****************************************************************************
3202 + * GPIO Control
3203 + *****************************************************************************/
3204 +
3205 +/****************************************************************************
3206 + * FUNCTION: tnetd73xx_gpio_init
3207 + ***************************************************************************/
3208 +void tnetd73xx_gpio_init()
3209 +{
3210 + /* Bring module out of reset */
3211 + tnetd73xx_reset_ctrl(RESET_MODULE_GPIO, OUT_OF_RESET);
3212 + REG32_WRITE(TNETD73XX_GPIOENR, 0xFFFFFFFF);
3213 +}
3214 +
3215 +/****************************************************************************
3216 + * FUNCTION: tnetd73xx_gpio_ctrl
3217 + ***************************************************************************/
3218 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
3219 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
3220 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction)
3221 +{
3222 + u32 pin_status;
3223 + REG32_READ(TNETD73XX_GPIOENR, pin_status);
3224 + if (pin_mode == GPIO_PIN)
3225 + {
3226 + pin_status |= (1 << gpio_pin);
3227 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3228 +
3229 + /* Set pin direction */
3230 + REG32_READ(TNETD73XX_GPIOPDIRR, pin_status);
3231 + if (pin_direction == GPIO_INPUT_PIN)
3232 + {
3233 + pin_status |= (1 << gpio_pin);
3234 + }
3235 + else /* GPIO_OUTPUT_PIN */
3236 + {
3237 + pin_status &= (~(1 << gpio_pin));
3238 + }
3239 + REG32_WRITE(TNETD73XX_GPIOPDIRR, pin_status);
3240 + }
3241 + else /* FUNCTIONAL PIN */
3242 + {
3243 + pin_status &= (~(1 << gpio_pin));
3244 + REG32_WRITE(TNETD73XX_GPIOENR, pin_status);
3245 + }
3246 +
3247 +}
3248 +
3249 +/****************************************************************************
3250 + * FUNCTION: tnetd73xx_gpio_out
3251 + ***************************************************************************/
3252 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value)
3253 +{
3254 + u32 pin_value;
3255 +
3256 + REG32_READ(TNETD73XX_GPIODOUTR, pin_value);
3257 + if (value == 1)
3258 + {
3259 + pin_value |= (1 << gpio_pin);
3260 + }
3261 + else
3262 + {
3263 + pin_value &= (~(1 << gpio_pin));
3264 + }
3265 + REG32_WRITE(TNETD73XX_GPIODOUTR, pin_value);
3266 +}
3267 +
3268 +/****************************************************************************
3269 + * FUNCTION: tnetd73xx_gpio_in
3270 + ***************************************************************************/
3271 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin)
3272 +{
3273 + u32 pin_value;
3274 + REG32_READ(TNETD73XX_GPIODINR, pin_value);
3275 + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 );
3276 +}
3277 +
3278 +EXPORT_SYMBOL(tnetd73xx_clkc_get_freq);
3279 +
3280 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
3281 --- linux.old/arch/mips/config-shared.in 2005-07-09 08:01:49.831653720 +0200
3282 +++ linux.dev/arch/mips/config-shared.in 2005-07-09 08:00:15.293025000 +0200
3283 @@ -20,6 +20,15 @@
3284 mainmenu_option next_comment
3285 comment 'Machine selection'
3286 dep_bool 'Support for Acer PICA 1 chipset (EXPERIMENTAL)' CONFIG_ACER_PICA_61 $CONFIG_EXPERIMENTAL
3287 +dep_bool 'Support for Texas Instruments AR7 (EXPERIMENTAL)' CONFIG_AR7 $CONFIG_MIPS32 $CONFIG_EXPERIMENTAL
3288 +if [ "$CONFIG_AR7" = "y" ]; then
3289 + choice 'Texas Instruments Reference Platform' \
3290 + "AR7DB CONFIG_AR7DB \
3291 + AR7RD CONFIG_AR7RD \
3292 + AR7WRD CONFIG_AR7WRD" AR7DB
3293 + int 'Texas Instruments AR7 CPU Frequency' CONFIG_AR7_FREQUENCY 150
3294 + hex 'Texas Instruments AR7 SDRAM Start' CONFIG_AR7_MEMORY 0x14000000
3295 +fi
3296 dep_bool 'Support for Alchemy Bosporus board' CONFIG_MIPS_BOSPORUS $CONFIG_MIPS32
3297 dep_bool 'Support for FIC Multimedia Player board' CONFIG_MIPS_FICMMP $CONFIG_MIPS32
3298 dep_bool 'Support for Alchemy Mirage board' CONFIG_MIPS_MIRAGE $CONFIG_MIPS32
3299 @@ -239,6 +248,11 @@
3300 define_bool CONFIG_NONCOHERENT_IO y
3301 define_bool CONFIG_PC_KEYB y
3302 fi
3303 +if [ "$CONFIG_AR7" = "y" ]; then
3304 + define_bool CONFIG_NONCOHERENT_IO y
3305 + define_bool CONFIG_SWAP_IO_SPACE y
3306 + define_bool CONFIG_AR7_PAGING y
3307 +fi
3308 if [ "$CONFIG_CASIO_E55" = "y" ]; then
3309 define_bool CONFIG_IRQ_CPU y
3310 define_bool CONFIG_NONCOHERENT_IO y
3311 @@ -736,6 +750,7 @@
3312 mainmenu_option next_comment
3313 comment 'General setup'
3314 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3315 + "$CONFIG_AR7" = "y" -o \
3316 "$CONFIG_CASIO_E55" = "y" -o \
3317 "$CONFIG_DDB5074" = "y" -o \
3318 "$CONFIG_DDB5476" = "y" -o \
3319 @@ -797,6 +812,7 @@
3320 bool 'Networking support' CONFIG_NET
3321
3322 if [ "$CONFIG_ACER_PICA_61" = "y" -o \
3323 + "$CONFIG_AR7" = "y" -o \
3324 "$CONFIG_CASIO_E55" = "y" -o \
3325 "$CONFIG_DECSTATION" = "y" -o \
3326 "$CONFIG_IBM_WORKPAD" = "y" -o \
3327 diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c
3328 --- linux.old/arch/mips/kernel/irq.c 2005-07-09 08:01:49.831653720 +0200
3329 +++ linux.dev/arch/mips/kernel/irq.c 2005-07-09 08:00:15.294025000 +0200
3330 @@ -76,6 +76,7 @@
3331 * Generic, controller-independent functions:
3332 */
3333
3334 +#ifndef CONFIG_AR7
3335 int get_irq_list(char *buf)
3336 {
3337 int i, j;
3338 @@ -110,6 +111,7 @@
3339 p += sprintf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
3340 return p - buf;
3341 }
3342 +#endif
3343
3344 #ifdef CONFIG_SMP
3345 int global_irq_holder = NO_PROC_ID;
3346 @@ -525,6 +527,7 @@
3347 *
3348 */
3349
3350 +#ifndef CONFIG_AR7
3351 int request_irq(unsigned int irq,
3352 void (*handler)(int, void *, struct pt_regs *),
3353 unsigned long irqflags,
3354 @@ -569,6 +572,7 @@
3355 kfree(action);
3356 return retval;
3357 }
3358 +#endif
3359
3360 /**
3361 * free_irq - free an interrupt
3362 @@ -588,6 +592,7 @@
3363 * the machine.
3364 */
3365
3366 +#ifndef CONFIG_AR7
3367 void free_irq(unsigned int irq, void *dev_id)
3368 {
3369 irq_desc_t *desc;
3370 @@ -629,6 +634,7 @@
3371 return;
3372 }
3373 }
3374 +#endif
3375
3376 /*
3377 * IRQ autodetection code..
3378 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
3379 --- linux.old/arch/mips/kernel/setup.c 2005-07-09 08:01:49.832653568 +0200
3380 +++ linux.dev/arch/mips/kernel/setup.c 2005-07-09 08:00:15.295025000 +0200
3381 @@ -109,6 +109,7 @@
3382 unsigned long isa_slot_offset;
3383 EXPORT_SYMBOL(isa_slot_offset);
3384
3385 +extern void avalanche_bootmem_init(void);
3386 extern void SetUpBootInfo(void);
3387 extern void load_mmu(void);
3388 extern asmlinkage void start_kernel(void);
3389 @@ -267,6 +268,9 @@
3390 #endif /* CONFIG_BLK_DEV_INITRD */
3391
3392 /* Find the highest page frame number we have available. */
3393 +#ifdef CONFIG_AR7_PAGING
3394 + avalanche_bootmem_init();
3395 +#else
3396 max_pfn = 0;
3397 first_usable_pfn = -1UL;
3398 for (i = 0; i < boot_mem_map.nr_map; i++) {
3399 @@ -376,7 +380,7 @@
3400
3401 /* Reserve the bootmap memory. */
3402 reserve_bootmem(PFN_PHYS(first_usable_pfn), bootmap_size);
3403 -
3404 +#endif
3405 #ifdef CONFIG_BLK_DEV_INITRD
3406 /* Board specific code should have set up initrd_start and initrd_end */
3407 ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
3408 @@ -494,6 +498,7 @@
3409 void hp_setup(void);
3410 void au1x00_setup(void);
3411 void frame_info_init(void);
3412 + void ar7_setup(void);
3413
3414 frame_info_init();
3415 #if defined(CONFIG_BLK_DEV_FD) || defined(CONFIG_BLK_DEV_FD_MODULE)
3416 @@ -691,6 +696,11 @@
3417 pmc_yosemite_setup();
3418 break;
3419 #endif
3420 +#ifdef CONFIG_AR7
3421 + case MACH_GROUP_UNKNOWN:
3422 + ar7_setup();
3423 + break;
3424 +#endif
3425 default:
3426 panic("Unsupported architecture");
3427 }
3428 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
3429 --- linux.old/arch/mips/kernel/traps.c 2005-07-09 08:01:49.832653568 +0200
3430 +++ linux.dev/arch/mips/kernel/traps.c 2005-07-09 08:00:15.295025000 +0200
3431 @@ -40,6 +40,10 @@
3432 #include <asm/uaccess.h>
3433 #include <asm/mmu_context.h>
3434
3435 +#ifdef CONFIG_AR7
3436 +#include <asm/ar7/ar7.h>
3437 +#endif
3438 +
3439 extern asmlinkage void handle_mod(void);
3440 extern asmlinkage void handle_tlbl(void);
3441 extern asmlinkage void handle_tlbs(void);
3442 @@ -869,9 +873,15 @@
3443
3444 exception_handlers[n] = handler;
3445 if (n == 0 && cpu_has_divec) {
3446 +#ifdef CONFIG_AR7
3447 + *(volatile u32 *)(AVALANCHE_VECS_KSEG0+0x200) = 0x08000000 |
3448 + (0x03ffffff & (handler >> 2));
3449 + flush_icache_range(AVALANCHE_VECS_KSEG0+0x200, AVALANCHE_VECS_KSEG0 + 0x204);
3450 +#else
3451 *(volatile u32 *)(KSEG0+0x200) = 0x08000000 |
3452 (0x03ffffff & (handler >> 2));
3453 flush_icache_range(KSEG0+0x200, KSEG0 + 0x204);
3454 +#endif
3455 }
3456 return (void *)old_handler;
3457 }
3458 @@ -920,14 +930,46 @@
3459 void __init trap_init(void)
3460 {
3461 extern char except_vec1_generic;
3462 + extern char except_vec2_generic;
3463 extern char except_vec3_generic, except_vec3_r4000;
3464 extern char except_vec_ejtag_debug;
3465 extern char except_vec4;
3466 unsigned long i;
3467
3468 +#ifdef CONFIG_AR7
3469 + extern char jump_tlb_miss, jump_tlb_miss_unused;
3470 + extern char jump_cache_error,jump_general_exception;
3471 + extern char jump_dedicated_interrupt;
3472 + clear_c0_status(ST0_BEV);
3473 +#endif
3474 +
3475 /* Copy the generic exception handler code to it's final destination. */
3476 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3477 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
3478 + memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3479
3480 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3481 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3482 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3483 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3484 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3485 +
3486 +#ifdef CONFIG_AR7
3487 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x80), &except_vec1_generic, 0x80);
3488 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x100), &except_vec2_generic, 0x80);
3489 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3490 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3491 +
3492 + memcpy((void *)(KSEG0 + 0x0), &jump_tlb_miss, 0x80);
3493 + memcpy((void *)(KSEG0 + 0x80), &jump_tlb_miss_unused, 0x80);
3494 + memcpy((void *)(KSEG0 + 0x100), &jump_cache_error, 0x80);
3495 + memcpy((void *)(KSEG0 + 0x180), &jump_general_exception, 0x80);
3496 + memcpy((void *)(KSEG0 + 0x200), &jump_dedicated_interrupt, 0x80);
3497 +#else
3498 + memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
3499 +#endif
3500 + flush_icache_range(KSEG0 + 0x80, KSEG0 + 0x200);
3501 +
3502 /*
3503 * Setup default vectors
3504 */
3505 @@ -951,8 +993,12 @@
3506 * Some MIPS CPUs have a dedicated interrupt vector which reduces the
3507 * interrupt processing overhead. Use it where available.
3508 */
3509 +#ifdef CONFIG_AR7
3510 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x200), &except_vec4, 8);
3511 +#else
3512 if (cpu_has_divec)
3513 memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
3514 +#endif
3515
3516 /*
3517 * Some CPUs can enable/disable for cache parity detection, but does
3518 @@ -991,12 +1037,17 @@
3519 if (cpu_has_mcheck)
3520 set_except_vector(24, handle_mcheck);
3521
3522 +memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3523 +#ifdef CONFIG_AR7
3524 + memcpy((void *)(AVALANCHE_VECS_KSEG0 + 0x180), &except_vec3_generic, 0x80);
3525 +#else
3526 if (cpu_has_vce)
3527 memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000, 0x80);
3528 else if (cpu_has_4kex)
3529 memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
3530 else
3531 memcpy((void *)(KSEG0 + 0x080), &except_vec3_generic, 0x80);
3532 +#endif
3533
3534 if (current_cpu_data.cputype == CPU_R6000 ||
3535 current_cpu_data.cputype == CPU_R6000A) {
3536 @@ -1023,7 +1074,11 @@
3537 if (board_nmi_handler_setup)
3538 board_nmi_handler_setup();
3539
3540 +#ifdef CONFIG_AR7
3541 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x200);
3542 +#else
3543 flush_icache_range(KSEG0, KSEG0 + 0x400);
3544 +#endif
3545
3546 per_cpu_trap_init();
3547 }
3548 diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c
3549 --- linux.old/arch/mips/lib/promlib.c 2005-07-09 08:01:49.833653416 +0200
3550 +++ linux.dev/arch/mips/lib/promlib.c 2005-07-09 08:00:15.296025000 +0200
3551 @@ -1,3 +1,4 @@
3552 +#ifndef CONFIG_AR7
3553 #include <stdarg.h>
3554 #include <linux/kernel.h>
3555
3556 @@ -22,3 +23,4 @@
3557 }
3558 va_end(args);
3559 }
3560 +#endif
3561 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
3562 --- linux.old/arch/mips/Makefile 2005-07-09 08:01:49.833653416 +0200
3563 +++ linux.dev/arch/mips/Makefile 2005-07-09 08:00:15.413007000 +0200
3564 @@ -369,6 +369,16 @@
3565 endif
3566
3567 #
3568 +# Texas Instruments AR7
3569 +#
3570 +
3571 +ifdef CONFIG_AR7
3572 +LIBS += arch/mips/ar7/ar7.o arch/mips/ar7/avalanche/avalanche.o
3573 +SUBDIRS += arch/mips/ar7 arch/mips/ar7/avalanche
3574 +LOADADDR += 0x94020000
3575 +endif
3576 +
3577 +#
3578 # DECstation family
3579 #
3580 ifdef CONFIG_DECSTATION
3581 diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c
3582 --- linux.old/arch/mips/mm/init.c 2005-07-09 08:01:49.834653264 +0200
3583 +++ linux.dev/arch/mips/mm/init.c 2005-07-09 08:00:15.297025000 +0200
3584 @@ -40,8 +40,10 @@
3585
3586 mmu_gather_t mmu_gathers[NR_CPUS];
3587 unsigned long highstart_pfn, highend_pfn;
3588 +#ifndef CONFIG_AR7_PAGING
3589 static unsigned long totalram_pages;
3590 static unsigned long totalhigh_pages;
3591 +#endif
3592
3593 void pgd_init(unsigned long page)
3594 {
3595 @@ -235,6 +237,7 @@
3596 #endif
3597 }
3598
3599 +#ifndef CONFIG_AR7_PAGING
3600 void __init paging_init(void)
3601 {
3602 unsigned long zones_size[MAX_NR_ZONES] = {0, 0, 0};
3603 @@ -272,6 +275,7 @@
3604
3605 free_area_init(zones_size);
3606 }
3607 +#endif
3608
3609 #define PFN_UP(x) (((x) + PAGE_SIZE - 1) >> PAGE_SHIFT)
3610 #define PFN_DOWN(x) ((x) >> PAGE_SHIFT)
3611 @@ -298,6 +302,7 @@
3612 return 0;
3613 }
3614
3615 +#ifndef CONFIG_AR7_PAGING
3616 void __init mem_init(void)
3617 {
3618 unsigned long codesize, reservedpages, datasize, initsize;
3619 @@ -359,6 +364,7 @@
3620 initsize >> 10,
3621 (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10)));
3622 }
3623 +#endif
3624
3625 #ifdef CONFIG_BLK_DEV_INITRD
3626 void free_initrd_mem(unsigned long start, unsigned long end)
3627 @@ -376,6 +382,7 @@
3628 }
3629 #endif
3630
3631 +#ifndef CONFIG_AR7_PAGING
3632 extern char __init_begin, __init_end;
3633 extern void prom_free_prom_memory(void) __init;
3634
3635 @@ -383,7 +390,9 @@
3636 {
3637 unsigned long addr;
3638
3639 +#ifndef CONFIG_AR7
3640 prom_free_prom_memory ();
3641 +#endif
3642
3643 addr = (unsigned long) &__init_begin;
3644 while (addr < (unsigned long) &__init_end) {
3645 @@ -409,3 +418,4 @@
3646
3647 return;
3648 }
3649 +#endif
3650 diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c
3651 --- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-09 08:01:49.834653264 +0200
3652 +++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-09 08:00:15.297025000 +0200
3653 @@ -20,6 +20,10 @@
3654 #include <asm/pgtable.h>
3655 #include <asm/system.h>
3656
3657 +#ifdef CONFIG_AR7
3658 +#include <asm/ar7/ar7.h>
3659 +#endif
3660 +
3661 extern char except_vec0_nevada, except_vec0_r4000, except_vec0_r4600;
3662
3663 /* CP0 hazard avoidance. */
3664 @@ -375,7 +379,12 @@
3665 else if (current_cpu_data.cputype == CPU_R4600)
3666 memcpy((void *)KSEG0, &except_vec0_r4600, 0x80);
3667 else
3668 +#ifdef CONFIG_AR7
3669 + memcpy((void *)AVALANCHE_VECS_KSEG0, &except_vec0_r4000, 0x80);
3670 + flush_icache_range(AVALANCHE_VECS_KSEG0, AVALANCHE_VECS_KSEG0 + 0x80);
3671 +#else
3672 memcpy((void *)KSEG0, &except_vec0_r4000, 0x80);
3673 flush_icache_range(KSEG0, KSEG0 + 0x80);
3674 +#endif
3675 }
3676 }
3677 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
3678 --- linux.old/drivers/char/serial.c 2005-07-09 08:01:49.836652960 +0200
3679 +++ linux.dev/drivers/char/serial.c 2005-07-09 08:00:15.299024000 +0200
3680 @@ -419,7 +419,40 @@
3681 return 0;
3682 }
3683
3684 -#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3685 +#if defined(CONFIG_AR7)
3686 +
3687 +static _INLINE_ unsigned int serial_in(struct async_struct *info, int offset)
3688 +{
3689 + return (inb(info->port + (offset * 4)) & 0xff);
3690 +}
3691 +
3692 +
3693 +static _INLINE_ unsigned int serial_inp(struct async_struct *info, int offset)
3694 +{
3695 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3696 + return (inb(info->port + (offset * 4)) & 0xff);
3697 +#else
3698 + return (inb_p(info->port + (offset * 4)) & 0xff);
3699 +#endif
3700 +}
3701 +
3702 +static _INLINE_ void serial_out(struct async_struct *info, int offset, int value)
3703 +{
3704 + outb(value, info->port + (offset * 4));
3705 +}
3706 +
3707 +
3708 +static _INLINE_ void serial_outp(struct async_struct *info, int offset,
3709 + int value)
3710 +{
3711 +#ifdef CONFIG_SERIAL_NOPAUSE_IO
3712 + outb(value, info->port + (offset * 4));
3713 +#else
3714 + outb_p(value, info->port + (offset * 4));
3715 +#endif
3716 +}
3717 +
3718 +#elif defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_SEAD)
3719
3720 #include <asm/mips-boards/atlas.h>
3721
3722 @@ -478,8 +511,10 @@
3723 * needed for certain old 386 machines, I've left these #define's
3724 * in....
3725 */
3726 +#ifndef CONFIG_AR7
3727 #define serial_inp(info, offset) serial_in(info, offset)
3728 #define serial_outp(info, offset, value) serial_out(info, offset, value)
3729 +#endif
3730
3731
3732 /*
3733 @@ -1728,7 +1763,15 @@
3734 /* Special case since 134 is really 134.5 */
3735 quot = (2*baud_base / 269);
3736 else if (baud)
3737 +#ifdef CONFIG_AR7
3738 + quot = get_avalanche_vbus_freq() / baud;
3739 +
3740 + if ((quot%16)>7)
3741 + quot += 8;
3742 + quot /=16;
3743 +#else
3744 quot = baud_base / baud;
3745 +#endif
3746 }
3747 /* If the quotient is zero refuse the change */
3748 if (!quot && old_termios) {
3749 @@ -5552,8 +5595,10 @@
3750 state->irq = irq_cannonicalize(state->irq);
3751 if (state->hub6)
3752 state->io_type = SERIAL_IO_HUB6;
3753 +#ifndef CONFIG_AR7
3754 if (state->port && check_region(state->port,8))
3755 continue;
3756 +#endif
3757 #ifdef CONFIG_MCA
3758 if ((state->flags & ASYNC_BOOT_ONLYMCA) && !MCA_bus)
3759 continue;
3760 @@ -6009,7 +6054,15 @@
3761 info->io_type = state->io_type;
3762 info->iomem_base = state->iomem_base;
3763 info->iomem_reg_shift = state->iomem_reg_shift;
3764 +#ifdef CONFIG_AR7
3765 + quot = get_avalanche_vbus_freq() / baud;
3766 +
3767 + if ((quot%16)>7)
3768 + quot += 8;
3769 + quot /=16;
3770 +#else
3771 quot = state->baud_base / baud;
3772 +#endif
3773 cval = cflag & (CSIZE | CSTOPB);
3774 #if defined(__powerpc__) || defined(__alpha__)
3775 cval >>= 8;
3776 diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h
3777 --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100
3778 +++ linux.dev/include/asm-mips/ar7/ar7.h 2005-07-09 08:00:15.300024000 +0200
3779 @@ -0,0 +1,137 @@
3780 +#ifndef _MIPS_AR7_H
3781 +#define _MIPS_AR7_H
3782 +
3783 +#include <linux/config.h>
3784 +#include <asm/addrspace.h>
3785 +
3786 +
3787 +#ifndef LITTLE_ENDIAN
3788 +#define LITTLE_ENDIAN
3789 +#endif
3790 +
3791 +#ifndef _LINK_KSEG0_
3792 +#define _LINK_KSEG0_
3793 +#endif
3794 +
3795 +#include <asm/ar7/tnetd73xx.h>
3796 +
3797 +#define AVALANCHE_UART0_INT 7
3798 +#define AVALANCHE_UART1_INT 8
3799 +
3800 +#define MIPS_EXCEPTION_OFFSET 8
3801 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
3802 +
3803 +/*
3804 + * AR7 board SDRAM base address. This is used to setup the
3805 + * bootmem tables
3806 + */
3807 +
3808 +#define AVALANCHE_SDRAM_BASE CONFIG_AR7_MEMORY//0x14000000UL
3809 +#define AVALANCHE_INTC_BASE TNETD73XX_INTC_BASE
3810 +
3811 +
3812 +/*
3813 + * AR7 board vectors
3814 + */
3815 +
3816 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3817 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3818 +
3819 +
3820 +/*
3821 + * Yamon Prom print address.
3822 + */
3823 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
3824 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
3825 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
3826 +
3827 +/*
3828 + * AR7 Reset and PSU standby register.
3829 + */
3830 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
3831 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
3832 +#define AVALANCHE_GORESET 0x1
3833 +#define AVALANCHE_GOSTBY 0x1
3834 +#define AVALANCHE_SWRCR (*(unsigned int *)TNETD73XX_RST_CTRL_SWRCR)
3835 +
3836 +/*
3837 + * Avalanche UART register base.
3838 + */
3839 +
3840 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3841 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3842 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3843 +
3844 +/*
3845 + * AVALANCHE DMA controller base
3846 + */
3847 +
3848 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
3849 +
3850 +
3851 +
3852 +/*
3853 + * GPIO register map
3854 + */
3855 +
3856 +/* to be obtained from avalanche_map.h */
3857 +#define AVALANCHE_GPIO_WRITE_REG (KSEG1ADDR(0xa8610904))
3858 +#define AVALANCHE_GPIO_DIRECTION_REG (KSEG1ADDR(0xa8610908))
3859 +#define AVALANCHE_GPIO_MODE_REG (KSEG1ADDR(0xa861090C))
3860 +#define AVALANCHE_GPIO_PIN_COUNT 32
3861 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0,0}
3862 +
3863 +
3864 +// Let us define board specific information here.
3865 +
3866 +#if defined(CONFIG_AR7DB)
3867 +
3868 +#define AFECLK_FREQ 35328000
3869 +#define REFCLK_FREQ 25000000
3870 +#define OSC3_FREQ 24000000
3871 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3872 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x55555555
3873 +
3874 +#endif
3875 +
3876 +
3877 +#if defined(CONFIG_AR7RD)
3878 +
3879 +#define AFECLK_FREQ 35328000
3880 +#define REFCLK_FREQ 25000000
3881 +#define OSC3_FREQ 24000000
3882 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3883 +
3884 +#if defined(CONFIG_AR7_MARVELL)
3885 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3886 +#else
3887 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3888 +#endif
3889 +
3890 +#endif
3891 +
3892 +
3893 +#if defined(CONFIG_AR7WRD)
3894 +
3895 +#define AFECLK_FREQ 35328000
3896 +#define REFCLK_FREQ 25000000
3897 +#define OSC3_FREQ 24000000
3898 +#define AVALANCHE_CPMAC_INTERNAL_PHY_MASK 0x80000000
3899 +
3900 +#if defined(CONFIG_AR7_MARVELL)
3901 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x00010000
3902 +#else
3903 +#define AVALANCHE_CPMAC_EXTERNAL_PHY_MASK 0x2
3904 +#endif
3905 +
3906 +#endif
3907 +
3908 +extern unsigned int tnetd73xx_vbus_freq;
3909 +#define AVALANCHE_VBUS_FREQ tnetd73xx_vbus_freq
3910 +
3911 +static inline unsigned int get_avalanche_vbus_freq(void)
3912 +{
3913 + return (tnetd73xx_vbus_freq);
3914 +}
3915 +
3916 +#endif /*_MIPS_AR7_H */
3917 diff -urN linux.old/include/asm-mips/ar7/avalanche.h linux.dev/include/asm-mips/ar7/avalanche.h
3918 --- linux.old/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100
3919 +++ linux.dev/include/asm-mips/ar7/avalanche.h 2005-07-09 08:00:15.301024000 +0200
3920 @@ -0,0 +1,183 @@
3921 +/* $Id$
3922 + *
3923 + * avalanche.h
3924 + *
3925 + * Jeff Harrell, jharrell@ti.com
3926 + * Copyright (C) 2000,2001,2002 Texas Instruments Inc.
3927 + *
3928 + *
3929 + * ########################################################################
3930 + *
3931 + * This program is free software; you can distribute it and/or modify it
3932 + * under the terms of the GNU General Public License (Version 2) as
3933 + * published by the Free Software Foundation.
3934 + *
3935 + * This program is distributed in the hope it will be useful, but WITHOUT
3936 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3937 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
3938 + * for more details.
3939 + *
3940 + * You should have received a copy of the GNU General Public License along
3941 + * with this program; if not, write to the Free Software Foundation, Inc.,
3942 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
3943 + *
3944 + * ########################################################################
3945 + *
3946 + * Defines of the AVALANCHE board specific address-MAP, registers, etc.
3947 + *
3948 + */
3949 +#ifndef _MIPS_AVALANCHE_H
3950 +#define _MIPS_AVALANCHE_H
3951 +
3952 +#include <asm/addrspace.h>
3953 +
3954 +/*
3955 + * AVALANCHE board SDRAM base address. This is used to setup the
3956 + * bootmem tables
3957 + */
3958 +
3959 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
3960 +
3961 +/*
3962 + * AVALANCHE board vectors
3963 + */
3964 +
3965 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
3966 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
3967 +/*
3968 + * Avalanche RTC-device indirect register access.
3969 + */
3970 +
3971 +#define EVM3_RTC_ADR_REG (KSEG1ADDR(0x1f000800))
3972 +#define EVM3_RTC_DAT_REG (KSEG1ADDR(0x1f000808))
3973 +
3974 +/*
3975 + * Evm3 interrupt controller register base (primary)
3976 + */
3977 +
3978 +#define AVALANCHE_ICTRL_REGS_BASE (KSEG1ADDR(0x08612400))
3979 +
3980 +/*
3981 + * Avalanche exception controller register base (secondary)
3982 + */
3983 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE+0x80)
3984 +
3985 +
3986 +/*
3987 + * Avalanche Interrupt Channel Control register base
3988 + */
3989 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
3990 +
3991 +
3992 +/*
3993 + * Avalanche UART register base.
3994 + */
3995 +
3996 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
3997 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 1 */
3998 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
3999 +/*
4000 + * AVALANCHE DMA controller base
4001 + */
4002 +
4003 +#define AVALANCHE_DMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* DMA 0 (channels 0-3) */
4004 +
4005 +
4006 +/*
4007 + * AVALANCHE display register base.
4008 + */
4009 +
4010 +#define EVM3_ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1D000038))
4011 +#define EVM3_ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1D00003F)) /* How is this used??? JAH */
4012 +
4013 +
4014 +#define EVM3_ASCIIPOS0 0x1D000038
4015 +#define EVM3_ASCIIPOS1 0x1D000039
4016 +#define EVM3_ASCIIPOS2 0x1D00003A
4017 +#define EVM3_ASCIIPOS3 0x1D00003B
4018 +#define EVM3_ASCIIPOS4 0x1D00003C
4019 +#define EVM3_ASCIIPOS5 0x1D00003D
4020 +#define EVM3_ASCIIPOS6 0x1D00003E
4021 +#define EVM3_ASCIIPOS7 0x1D00003F
4022 +
4023 +/*
4024 + * Yamon Prom print address.
4025 + */
4026 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
4027 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
4028 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
4029 +
4030 +/*
4031 + * Evm3 Reset and PSU standby register.
4032 + */
4033 +#define AVALANCHE_SOFTRES_REG (KSEG1ADDR(0x08611600)) /* Resets machine */
4034 +#define AVALANCHE_PSUSTBY_REG (KSEG1ADDR(0x08611600)) /* Turns off power supply unit */
4035 +#define AVALANCHE_GORESET 0x1
4036 +#define AVALANCHE_GOSTBY 0x1
4037 +
4038 +/************************************************************************
4039 + * PERIPHERAL BUS LEDs (P-LED):
4040 +*************************************************************************/
4041 +
4042 +/************************************************************************
4043 + * P-LED Register Addresses
4044 +*************************************************************************/
4045 +
4046 +#define EVM3_PLED (KSEG1ADDR(0x01C500000)) /* 0x1D200000 P-LED */
4047 +
4048 +
4049 +/************************************************************************
4050 + * Register field encodings
4051 +*************************************************************************/
4052 +
4053 +/******** reg: PLED ********/
4054 +/* bits 7:0: VAL */
4055 +#define EVM3_PLED_VAL_MSK 0xff
4056 +
4057 +/* bit 0: */
4058 +#define EVM3_PLED_BIT0_SHF 0
4059 +#define EVM3_PLED_BIT0_MSK (1 << EVM3_PLED_BIT0_SHF)
4060 +#define EVM3_PLED_BIT0_ON EVM3_PLED_BIT0_MSK
4061 +
4062 +/* bit 1: */
4063 +#define EVM3_PLED_BIT1_SHF 1
4064 +#define EVM3_PLED_BIT1_MSK (1 << EVM3_PLED_BIT1_SHF)
4065 +#define EVM3_PLED_BIT1_ON EVM3_PLED_BIT1_MSK
4066 +
4067 +/* bit 2: */
4068 +#define EVM3_PLED_BIT2_SHF 2
4069 +#define EVM3_PLED_BIT2_MSK (1 << EVM3_PLED_BIT2_SHF)
4070 +#define EVM3_PLED_BIT2_ON EVM3_PLED_BIT2_MSK
4071 +
4072 +/* bit 3: */
4073 +#define EVM3_PLED_BIT3_SHF 3
4074 +#define EVM3_PLED_BIT3_MSK (1 << EVM3_PLED_BIT3_SHF)
4075 +#define EVM3_PLED_BIT3_ON EVM3_PLED_BIT3_MSK
4076 +
4077 +/* bit 4: */
4078 +#define EVM3_PLED_BIT4_SHF 4
4079 +#define EVM3_PLED_BIT4_MSK (1 << EVM3_PLED_BIT4_SHF)
4080 +#define EVM3_PLED_BIT4_ON EVM3_PLED_BIT4_MSK
4081 +
4082 +/* bit 5: */
4083 +#define EVM3_PLED_BIT5_SHF 5
4084 +#define EVM3_PLED_BIT5_MSK (1 << EVM3_PLED_BIT5_SHF)
4085 +#define EVM3_PLED_BIT5_ON EVM3_PLED_BIT5_MSK
4086 +
4087 +/* bit 6: */
4088 +#define EVM3_PLED_BIT6_SHF 6
4089 +#define EVM3_PLED_BIT6_MSK (1 << EVM3_PLED_BIT6_SHF)
4090 +#define EVM3_PLED_BIT6_ON EVM3_PLED_BIT6_MSK
4091 +
4092 +/* bit 7: */
4093 +#define EVM3_PLED_BIT7_SHF 7
4094 +#define EVM3_PLED_BIT7_MSK (1 << EVM3_PLED_BIT7_SHF)
4095 +#define EVM3_PLED_BIT7_ON EVM3_PLED_BIT7_MSK
4096 +
4097 +#endif /* !(_MIPS_AVALANCHE_H) */
4098 +
4099 +
4100 +
4101 +
4102 +
4103 +
4104 diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h
4105 --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100
4106 +++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-07-09 08:00:15.301024000 +0200
4107 @@ -0,0 +1,273 @@
4108 + /*
4109 + * Nitin Dhingra, iamnd@ti.com
4110 + * Copyright (C) 2000 Texas Instruments Inc.
4111 + *
4112 + *
4113 + * ########################################################################
4114 + *
4115 + * This program is free software; you can distribute it and/or modify it
4116 + * under the terms of the GNU General Public License (Version 2) as
4117 + * published by the Free Software Foundation.
4118 + *
4119 + * This program is distributed in the hope it will be useful, but WITHOUT
4120 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4121 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4122 + * for more details.
4123 + *
4124 + * You should have received a copy of the GNU General Public License along
4125 + * with this program; if not, write to the Free Software Foundation, Inc.,
4126 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4127 + *
4128 + * ########################################################################
4129 + *
4130 + * Defines of the Sead board specific address-MAP, registers, etc.
4131 + *
4132 + */
4133 +#ifndef _AVALANCHE_INTC_H
4134 +#define _AVALANCHE_INTC_H
4135 +
4136 +#define MIPS_EXCEPTION_OFFSET 8
4137 +
4138 +/******************************************************************************
4139 + Avalanche Interrupt number
4140 +******************************************************************************/
4141 +#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET)
4142 +
4143 +/*******************************************************************************
4144 +*Linux Interrupt number
4145 +*******************************************************************************/
4146 +#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET)
4147 +
4148 +
4149 +
4150 +#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET)
4151 +#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET)
4152 +
4153 +#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET)
4154 +#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET)
4155 +
4156 +
4157 +#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + \
4158 + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \
4159 + + MIPS_EXCEPTION_OFFSET - 1) /* Suraj, check */
4160 +
4161 +
4162 +/*
4163 + * Avalanche interrupt controller register base (primary)
4164 + */
4165 +#define AVALANCHE_ICTRL_REGS_BASE AVALANCHE_INTC_BASE
4166 +
4167 +/******************************************************************************
4168 + * Avalanche exception controller register base (secondary)
4169 + ******************************************************************************/
4170 +#define AVALANCHE_ECTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x80)
4171 +
4172 +
4173 +/******************************************************************************
4174 + * Avalanche Interrupt pacing register base (secondary)
4175 + ******************************************************************************/
4176 +#define AVALANCHE_IPACE_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0xA0)
4177 +
4178 +
4179 +
4180 +/******************************************************************************
4181 + * Avalanche Interrupt Channel Control register base
4182 + *****************************************************************************/
4183 +#define AVALANCHE_CHCTRL_REGS_BASE (AVALANCHE_ICTRL_REGS_BASE + 0x200)
4184 +
4185 +
4186 +struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */
4187 +{
4188 + volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 0x00 */
4189 + volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 0x04 */
4190 + volatile unsigned long unused1; /*0x08 */
4191 + volatile unsigned long unused2; /*0x0C */
4192 + volatile unsigned long intcr1; /* Interrupt Clear Register 1 0x10 */
4193 + volatile unsigned long intcr2; /* Interrupt Clear Register 2 0x14 */
4194 + volatile unsigned long unused3; /*0x18 */
4195 + volatile unsigned long unused4; /*0x1C */
4196 + volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 0x20 */
4197 + volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 0x24 */
4198 + volatile unsigned long unused5; /*0x28 */
4199 + volatile unsigned long unused6; /*0x2C */
4200 + volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 0x30 */
4201 + volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 0x34 */
4202 + volatile unsigned long unused7; /* 0x38 */
4203 + volatile unsigned long unused8; /* 0x3c */
4204 + volatile unsigned long pintir; /* Priority Interrupt Index Register 0x40 */
4205 + volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg 0x44 */
4206 + volatile unsigned long unused9; /* 0x48 */
4207 + volatile unsigned long unused10; /* 0x4C */
4208 + volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 10x50 */
4209 + volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 20x54 */
4210 + volatile unsigned long unused11; /* 0x58 */
4211 + volatile unsigned long unused12; /*0x5C */
4212 + volatile unsigned long inttypr1; /* Interrupt Type Mask register 10x60 */
4213 + volatile unsigned long inttypr2; /* Interrupt Type Mask register 20x64 */
4214 +};
4215 +
4216 +struct avalanche_exctrl_regs /* Avalanche Exception control registers */
4217 +{
4218 + volatile unsigned long exsr; /* Exceptions Status/Set register 0x80 */
4219 + volatile unsigned long reserved; /*0x84 */
4220 + volatile unsigned long excr; /* Exceptions Clear Register 0x88 */
4221 + volatile unsigned long reserved1; /*0x8c */
4222 + volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) 0x90 */
4223 + volatile unsigned long reserved2; /*0x94 */
4224 + volatile unsigned long exiecr; /* Exceptions Interrupt Enable(clear)0x98 */
4225 +};
4226 +struct avalanche_ipace_regs
4227 +{
4228 +
4229 + volatile unsigned long ipacep; /* Interrupt pacing register 0xa0 */
4230 + volatile unsigned long ipacemap; /*Interrupt Pacing Map Register 0xa4 */
4231 + volatile unsigned long ipacemax; /*Interrupt Pacing Max Register 0xa8 */
4232 +};
4233 +struct avalanche_channel_int_number
4234 +{
4235 + volatile unsigned long cintnr0; /* Channel Interrupt Number Register0x200 */
4236 + volatile unsigned long cintnr1; /* Channel Interrupt Number Register0x204 */
4237 + volatile unsigned long cintnr2; /* Channel Interrupt Number Register0x208 */
4238 + volatile unsigned long cintnr3; /* Channel Interrupt Number Register0x20C */
4239 + volatile unsigned long cintnr4; /* Channel Interrupt Number Register0x210 */
4240 + volatile unsigned long cintnr5; /* Channel Interrupt Number Register0x214 */
4241 + volatile unsigned long cintnr6; /* Channel Interrupt Number Register0x218 */
4242 + volatile unsigned long cintnr7; /* Channel Interrupt Number Register0x21C */
4243 + volatile unsigned long cintnr8; /* Channel Interrupt Number Register0x220 */
4244 + volatile unsigned long cintnr9; /* Channel Interrupt Number Register0x224 */
4245 + volatile unsigned long cintnr10; /* Channel Interrupt Number Register0x228 */
4246 + volatile unsigned long cintnr11; /* Channel Interrupt Number Register0x22C */
4247 + volatile unsigned long cintnr12; /* Channel Interrupt Number Register0x230 */
4248 + volatile unsigned long cintnr13; /* Channel Interrupt Number Register0x234 */
4249 + volatile unsigned long cintnr14; /* Channel Interrupt Number Register0x238 */
4250 + volatile unsigned long cintnr15; /* Channel Interrupt Number Register0x23C */
4251 + volatile unsigned long cintnr16; /* Channel Interrupt Number Register0x240 */
4252 + volatile unsigned long cintnr17; /* Channel Interrupt Number Register0x244 */
4253 + volatile unsigned long cintnr18; /* Channel Interrupt Number Register0x248 */
4254 + volatile unsigned long cintnr19; /* Channel Interrupt Number Register0x24C */
4255 + volatile unsigned long cintnr20; /* Channel Interrupt Number Register0x250 */
4256 + volatile unsigned long cintnr21; /* Channel Interrupt Number Register0x254 */
4257 + volatile unsigned long cintnr22; /* Channel Interrupt Number Register0x358 */
4258 + volatile unsigned long cintnr23; /* Channel Interrupt Number Register0x35C */
4259 + volatile unsigned long cintnr24; /* Channel Interrupt Number Register0x260 */
4260 + volatile unsigned long cintnr25; /* Channel Interrupt Number Register0x264 */
4261 + volatile unsigned long cintnr26; /* Channel Interrupt Number Register0x268 */
4262 + volatile unsigned long cintnr27; /* Channel Interrupt Number Register0x26C */
4263 + volatile unsigned long cintnr28; /* Channel Interrupt Number Register0x270 */
4264 + volatile unsigned long cintnr29; /* Channel Interrupt Number Register0x274 */
4265 + volatile unsigned long cintnr30; /* Channel Interrupt Number Register0x278 */
4266 + volatile unsigned long cintnr31; /* Channel Interrupt Number Register0x27C */
4267 + volatile unsigned long cintnr32; /* Channel Interrupt Number Register0x280 */
4268 + volatile unsigned long cintnr33; /* Channel Interrupt Number Register0x284 */
4269 + volatile unsigned long cintnr34; /* Channel Interrupt Number Register0x288 */
4270 + volatile unsigned long cintnr35; /* Channel Interrupt Number Register0x28C */
4271 + volatile unsigned long cintnr36; /* Channel Interrupt Number Register0x290 */
4272 + volatile unsigned long cintnr37; /* Channel Interrupt Number Register0x294 */
4273 + volatile unsigned long cintnr38; /* Channel Interrupt Number Register0x298 */
4274 + volatile unsigned long cintnr39; /* Channel Interrupt Number Register0x29C */
4275 +};
4276 +
4277 +struct avalanche_interrupt_line_to_channel
4278 +{
4279 + unsigned long int_line0; /* Start of primary interrupts */
4280 + unsigned long int_line1;
4281 + unsigned long int_line2;
4282 + unsigned long int_line3;
4283 + unsigned long int_line4;
4284 + unsigned long int_line5;
4285 + unsigned long int_line6;
4286 + unsigned long int_line7;
4287 + unsigned long int_line8;
4288 + unsigned long int_line9;
4289 + unsigned long int_line10;
4290 + unsigned long int_line11;
4291 + unsigned long int_line12;
4292 + unsigned long int_line13;
4293 + unsigned long int_line14;
4294 + unsigned long int_line15;
4295 + unsigned long int_line16;
4296 + unsigned long int_line17;
4297 + unsigned long int_line18;
4298 + unsigned long int_line19;
4299 + unsigned long int_line20;
4300 + unsigned long int_line21;
4301 + unsigned long int_line22;
4302 + unsigned long int_line23;
4303 + unsigned long int_line24;
4304 + unsigned long int_line25;
4305 + unsigned long int_line26;
4306 + unsigned long int_line27;
4307 + unsigned long int_line28;
4308 + unsigned long int_line29;
4309 + unsigned long int_line30;
4310 + unsigned long int_line31;
4311 + unsigned long int_line32;
4312 + unsigned long int_line33;
4313 + unsigned long int_line34;
4314 + unsigned long int_line35;
4315 + unsigned long int_line36;
4316 + unsigned long int_line37;
4317 + unsigned long int_line38;
4318 + unsigned long int_line39;
4319 +};
4320 +
4321 +
4322 +/* Interrupt Line #'s (Sangam peripherals) */
4323 +
4324 +/*------------------------------*/
4325 +/* Sangam primary interrupts */
4326 +/*------------------------------*/
4327 +
4328 +#define UNIFIED_SECONDARY_INTERRUPT 0
4329 +#define AVALANCHE_EXT_INT_0 1
4330 +#define AVALANCHE_EXT_INT_1 2
4331 +/* Line #3 Reserved */
4332 +/* Line #4 Reserved */
4333 +#define AVALANCHE_TIMER_0_INT 5
4334 +#define AVALANCHE_TIMER_1_INT 6
4335 +#define AVALANCHE_UART0_INT 7
4336 +#define AVALANCHE_UART1_INT 8
4337 +#define AVALANCHE_PDMA_INT0 9
4338 +#define AVALANCHE_PDMA_INT1 10
4339 +/* Line #11 Reserved */
4340 +/* Line #12 Reserved */
4341 +/* Line #13 Reserved */
4342 +/* Line #14 Reserved */
4343 +#define AVALANCHE_ATM_SAR_INT 15
4344 +/* Line #16 Reserved */
4345 +/* Line #17 Reserved */
4346 +/* Line #18 Reserved */
4347 +#define AVALANCHE_MAC0_INT 19
4348 +/* Line #20 Reserved */
4349 +#define AVALANCHE_VLYNQ0_INT 21
4350 +#define AVALANCHE_CODEC_WAKE_INT 22
4351 +/* Line #23 Reserved */
4352 +#define AVALANCHE_USB_INT 24
4353 +#define AVALANCHE_VLYNQ1_INT 25
4354 +/* Line #26 Reserved */
4355 +/* Line #27 Reserved */
4356 +#define AVALANCHE_MAC1_INT 28
4357 +#define AVALANCHE_I2CM_INT 29
4358 +#define AVALANCHE_PDMA_INT2 30
4359 +#define AVALANCHE_PDMA_INT3 31
4360 +/* Line #32 Reserved */
4361 +/* Line #33 Reserved */
4362 +/* Line #34 Reserved */
4363 +/* Line #35 Reserved */
4364 +/* Line #36 Reserved */
4365 +#define AVALANCHE_VDMA_VT_RX_INT 37
4366 +#define AVALANCHE_VDMA_VT_TX_INT 38
4367 +#define AVALANCHE_ADSLSS_INT 39
4368 +
4369 +/*-----------------------------------*/
4370 +/* Sangam Secondary Interrupts */
4371 +/*-----------------------------------*/
4372 +#define PRIMARY_INTS 40
4373 +
4374 +#define EMIF_INT (7 + PRIMARY_INTS)
4375 +
4376 +
4377 +extern void avalanche_int_set(int channel, int line);
4378 +
4379 +
4380 +#endif /* _AVALANCHE_INTC_H */
4381 diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h
4382 --- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100
4383 +++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-07-09 08:00:15.302024000 +0200
4384 @@ -0,0 +1,149 @@
4385 +#ifndef _AVALANCHE_MISC_H_
4386 +#define _AVALANCHE_MISC_H_
4387 +
4388 +typedef enum AVALANCHE_ERR_t
4389 +{
4390 + AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */
4391 + AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
4392 +
4393 + /* Pointers and args */
4394 + AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */
4395 + AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */
4396 + AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
4397 +
4398 + /* Memory issues */
4399 + AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */
4400 + AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */
4401 + AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */
4402 + AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */
4403 +
4404 + /* Device issues */
4405 + AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
4406 + AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
4407 +
4408 + AVALANCHE_ERR_INVID = -30 /* Invalid ID */
4409 +
4410 +} AVALANCHE_ERR;
4411 +
4412 +/*****************************************************************************
4413 + * Reset Control Module
4414 + *****************************************************************************/
4415 +
4416 +typedef enum AVALANCHE_RESET_CTRL_tag
4417 +{
4418 + IN_RESET = 0,
4419 + OUT_OF_RESET
4420 +} AVALANCHE_RESET_CTRL_T;
4421 +
4422 +typedef enum AVALANCHE_SYS_RST_MODE_tag
4423 +{
4424 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
4425 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
4426 +} AVALANCHE_SYS_RST_MODE_T;
4427 +
4428 +typedef enum AVALANCHE_SYS_RESET_STATUS_tag
4429 +{
4430 + HARDWARE_RESET = 0,
4431 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
4432 + WATCHDOG_RESET,
4433 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
4434 +} AVALANCHE_SYS_RESET_STATUS_T;
4435 +
4436 +void avalanche_reset_ctrl(unsigned int reset_module,AVALANCHE_RESET_CTRL_T reset_ctrl);
4437 +AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int reset_module);
4438 +void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode);
4439 +AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void);
4440 +
4441 +typedef void (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module,
4442 + AVALANCHE_RESET_CTRL_T reset_ctrl);
4443 +
4444 +/*****************************************************************************
4445 + * Power Control Module
4446 + *****************************************************************************/
4447 +
4448 +typedef enum AVALANCHE_POWER_CTRL_tag
4449 +{
4450 + POWER_CTRL_POWER_UP = 0,
4451 + POWER_CTRL_POWER_DOWN
4452 +} AVALANCHE_POWER_CTRL_T;
4453 +
4454 +typedef enum AVALANCHE_SYS_POWER_MODE_tag
4455 +{
4456 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
4457 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
4458 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
4459 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
4460 +} AVALANCHE_SYS_POWER_MODE_T;
4461 +
4462 +void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl);
4463 +AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module);
4464 +void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode);
4465 +AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void);
4466 +
4467 +/*****************************************************************************
4468 + * Wakeup Control
4469 + *****************************************************************************/
4470 +
4471 +typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag
4472 +{
4473 + WAKEUP_INT0 = 1,
4474 + WAKEUP_INT1 = 2,
4475 + WAKEUP_INT2 = 4,
4476 + WAKEUP_INT3 = 8
4477 +} AVALANCHE_WAKEUP_INTERRUPT_T;
4478 +
4479 +typedef enum TNETV1050_WAKEUP_CTRL_tag
4480 +{
4481 + WAKEUP_DISABLED = 0,
4482 + WAKEUP_ENABLED
4483 +} AVALANCHE_WAKEUP_CTRL_T;
4484 +
4485 +typedef enum TNETV1050_WAKEUP_POLARITY_tag
4486 +{
4487 + WAKEUP_ACTIVE_HIGH = 0,
4488 + WAKEUP_ACTIVE_LOW
4489 +} AVALANCHE_WAKEUP_POLARITY_T;
4490 +
4491 +void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int,
4492 + AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl,
4493 + AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity);
4494 +
4495 +/*****************************************************************************
4496 + * GPIO Control
4497 + *****************************************************************************/
4498 +
4499 +typedef enum AVALANCHE_GPIO_PIN_MODE_tag
4500 +{
4501 + FUNCTIONAL_PIN = 0,
4502 + GPIO_PIN = 1
4503 +} AVALANCHE_GPIO_PIN_MODE_T;
4504 +
4505 +typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag
4506 +{
4507 + GPIO_OUTPUT_PIN = 0,
4508 + GPIO_INPUT_PIN = 1
4509 +} AVALANCHE_GPIO_PIN_DIRECTION_T;
4510 +
4511 +typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T;
4512 +
4513 +void avalanche_gpio_init(void);
4514 +int avalanche_gpio_ctrl(unsigned int gpio_pin,
4515 + AVALANCHE_GPIO_PIN_MODE_T pin_mode,
4516 + AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction);
4517 +int avalanche_gpio_out_bit(unsigned int gpio_pin, int value);
4518 +int avalanche_gpio_in_bit(unsigned int gpio_pin);
4519 +int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask,
4520 + unsigned int reg_index);
4521 +int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index);
4522 +
4523 +unsigned int avalanche_get_chip_version_info(void);
4524 +
4525 +unsigned int avalanche_get_vbus_freq(void);
4526 +void avalanche_set_vbus_freq(unsigned int);
4527 +
4528 +
4529 +typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation);
4530 +int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation);
4531 +unsigned int avalanche_is_mdix_on_chip(void);
4532 +
4533 +#endif
4534 diff -urN linux.old/include/asm-mips/ar7/avalanche_prom.h linux.dev/include/asm-mips/ar7/avalanche_prom.h
4535 --- linux.old/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100
4536 +++ linux.dev/include/asm-mips/ar7/avalanche_prom.h 2005-07-09 08:00:15.302024000 +0200
4537 @@ -0,0 +1,54 @@
4538 +/* $Id$
4539 + *
4540 + * prom.h
4541 + *
4542 + * Carsten Langgaard, carstenl@mips.com
4543 + * Copyright (C) 1999 MIPS Technologies, Inc.
4544 + *
4545 + * ########################################################################
4546 + *
4547 + * This program is free software; you can distribute it and/or modify it
4548 + * under the terms of the GNU General Public License (Version 2) as
4549 + * published by the Free Software Foundation.
4550 + *
4551 + * This program is distributed in the hope it will be useful, but WITHOUT
4552 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
4553 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
4554 + * for more details.
4555 + *
4556 + * You should have received a copy of the GNU General Public License along
4557 + * with this program; if not, write to the Free Software Foundation, Inc.,
4558 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
4559 + *
4560 + * ########################################################################
4561 + *
4562 + * Sead bootprom interface for the Linux kernel.
4563 + *
4564 + */
4565 +
4566 +#ifndef _MIPS_PROM_H
4567 +#define _MIPS_PROM_H
4568 +
4569 +extern char *prom_getcmdline(void);
4570 +extern char *prom_getenv(char *name);
4571 +extern void setup_prom_printf(void);
4572 +extern void prom_printf(char *fmt, ...);
4573 +extern void prom_init_cmdline(void);
4574 +extern void prom_meminit(void);
4575 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
4576 +extern void prom_free_prom_memory (void);
4577 +extern void sead_display_message(const char *str);
4578 +extern void sead_display_word(unsigned int num);
4579 +extern int get_ethernet_addr(char *ethernet_addr);
4580 +
4581 +/* Memory descriptor management. */
4582 +#define PROM_MAX_PMEMBLOCKS 32
4583 +struct prom_pmemblock {
4584 + unsigned long base; /* Within KSEG0. */
4585 + unsigned int size; /* In bytes. */
4586 + unsigned int type; /* free or prom memory */
4587 +};
4588 +
4589 +
4590 +#endif /* !(_MIPS_PROM_H) */
4591 +
4592 diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h
4593 --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100
4594 +++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-07-09 08:00:15.303024000 +0200
4595 @@ -0,0 +1,567 @@
4596 +/*
4597 + * $Id$
4598 + * Avalanche Register Descriptions
4599 + *
4600 + * Jeff Harrell, jharrell@ti.com
4601 + * 2000 (c) Texas Instruments Inc.
4602 + */
4603 +
4604 +#ifndef __AVALANCHE_REGS_H
4605 +#define __AVALANCHE_REGS_H
4606 +
4607 +#include <asm/addrspace.h>
4608 +#include <linux/config.h>
4609 +
4610 +/*----------------------------------------*/
4611 +/* Base offsets within the Avalanche ASIC */
4612 +/*----------------------------------------*/
4613 +
4614 +#define BBIF_SPACE0 (KSEG1ADDR(0x01000000))
4615 +#define BBIF_SPACE1 (KSEG1ADDR(0x01800000))
4616 +#define BBIF_CONTROL (KSEG1ADDR(0x02000000))
4617 +#define ATM_SAR_BASE (KSEG1ADDR(0x03000000))
4618 +#define USB_MCU_BASE (KSEG1ADDR(0x03400000))
4619 +#define DES_BASE (KSEG1ADDR(0x08600000))
4620 +#define ETH_MACA_BASE (KSEG1ADDR(0x08610000))
4621 +#define ETH_MACB_BASE (KSEG1ADDR(0x08612800))
4622 +#define MEM_CTRLR_BASE (KSEG1ADDR(0x08610800))
4623 +#define GPIO_BASE (KSEG1ADDR(0x08610900))
4624 +#define CLK_CTRL_BASE (KSEG1ADDR(0x08610A00))
4625 +#define WATCH_DOG_BASE (KSEG1ADDR(0x08610B00))
4626 +#define TMR1_BASE (KSEG1ADDR(0x08610C00))
4627 +#define TRM2_BASE (KSEG1ADDR(0x08610D00))
4628 +#define UARTA_BASE (KSEG1ADDR(0x08610E00))
4629 +#define UARTB_BASE (KSEG1ADDR(0x08610F00))
4630 +#define I2C_BASE (KSEG1ADDR(0x08611000))
4631 +#define DEV_ID_BASE (KSEG1ADDR(0x08611100))
4632 +#define USB_BASE (KSEG1ADDR(0x08611200))
4633 +#define PCI_CONFIG_BASE (KSEG1ADDR(0x08611300))
4634 +#define DMA_BASE (KSEG1ADDR(0x08611400))
4635 +#define RESET_CTRL_BASE (KSEG1ADDR(0x08611600))
4636 +#define DSL_IF_BASE (KSEG1ADDR(0x08611B00))
4637 +#define INT_CTL_BASE (KSEG1ADDR(0x08612400))
4638 +#define PHY_BASE (KSEG1ADDR(0x1E000000))
4639 +
4640 +/*---------------------------------*/
4641 +/* Device ID, chip version number */
4642 +/*---------------------------------*/
4643 +
4644 +#define AVALANCHE_CHVN (*(volatile unsigned int *)(DEV_ID_BASE+0x14))
4645 +#define AVALANCHE_DEVID1 (*(volatile unsigned int *)(DEV_ID_BASE+0x18))
4646 +#define AVALANCHE_DEVID2 (*(volatile unsigned int *)(DEV_ID_BASE+0x1C))
4647 +
4648 +/*----------------------------------*/
4649 +/* Reset Control VW changed to ptrs */
4650 +/*----------------------------------*/
4651 +
4652 +#define AVALANCHE_PRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x0)) /* Peripheral reset control */
4653 +#define AVALANCHE_SWRCR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x4)) /* Software reset control */
4654 +#define AVALANCHE_RSR (*(volatile unsigned int *)(RESET_CTRL_BASE + 0x8)) /* Reset status register */
4655 +
4656 +/* reset control bits */
4657 +
4658 +#define AV_RST_UART0 (1<<0) /* Brings UART0 out of reset */
4659 +#define AV_RST_UART1 (1<<1) /* Brings UART1 out of reset */
4660 +#define AV_RST_IICM (1<<2) /* Brings the I2CM out of reset */
4661 +#define AV_RST_TIMER0 (1<<3) /* Brings Timer 0 out of reset */
4662 +#define AV_RST_TIMER1 (1<<4) /* Brings Timer 1 out of reset */
4663 +#define AV_RST_DES (1<<5) /* Brings the DES module out of reset */
4664 +#define AV_RST_GPIO (1<<6) /* Brings the GPIO module out of reset (see note below) */
4665 +/*
4666 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4667 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4668 + interface pins are inputs and must be reconfigured so as not to lose the
4669 + serial console interface
4670 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4671 +*/
4672 +#define AV_RST_BBIF (1<<7) /* Brings the Broadband interface out of reset */
4673 +#define AV_RST_USB (1<<8) /* Brings the USB module out of reset */
4674 +#define AV_RST_SAR (1<<9) /* Brings the SAR out of reset */
4675 +#define AV_RST_HDLC (1<<10) /* Brings the HDLC module out of reset */
4676 +#define AV_RST_PCI (1<<16) /* Brings the PCI module out of reset */
4677 +#define AV_RST_ETH_MAC0 (1<<17) /* Brings the Ethernet MAC0 out of reset */
4678 +#define AV_RST_PICO_DMA (1<<18) /* Brings the PICO DMA module out of reset */
4679 +#define AV_RST_BIST (1<<19) /* Brings the BIST module out of reset */
4680 +#define AV_RST_DSP (1<<20) /* Brings the DSP sub system out of reset */
4681 +#define AV_RST_ETH_MAC1 (1<<21) /* Brings the Ethernet MAC1 out of reset */
4682 +
4683 +/*----------------------*/
4684 +/* Physical interfaces */
4685 +/*----------------------*/
4686 +
4687 +/* Phy loopback */
4688 +#define PHY_LOOPBACK 1
4689 +
4690 +
4691 +/* Phy 0 */
4692 +#define PHY0BASE (PHY_BASE)
4693 +#define PHY0RST (*(volatile unsigned char *) (PHY0BASE)) /* reset */
4694 +#define PHY0CTRL (*(volatile unsigned char *) (PHY0BASE+0x5)) /* control */
4695 +#define PHY0RACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x50)) /* RACP control/status */
4696 +#define PHY0TACPCTRL (*(volatile unsigned char *) (PHY0BASE+0x60)) /* TACP idle/unassigned cell hdr */
4697 +#define PHY0RACPINT (*(volatile unsigned char *) (PHY0BASE+0x51)) /* RACP interrupt enable/Status */
4698 +
4699 +
4700 +/* Phy 1 */
4701 +
4702 +#define PHY1BASE (PHY_BASE + 0x100000)
4703 +#define PHY1RST (*(volatile unsigned char *) (PHY1BASE)) /* reset */
4704 +#define PHY1CTRL (*(volatile unsigned char *) (PHY1BASE+0x5)) /* control */
4705 +#define PHY1RACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x50))
4706 +#define PHY1TACPCTRL (*(volatile unsigned char *) (PHY1BASE+0x60))
4707 +#define PHY1RACPINT (*(volatile unsigned char *) (PHY1BASE+0x51))
4708 +
4709 +/* Phy 2 */
4710 +
4711 +#define PHY2BASE (PHY_BASE + 0x200000)
4712 +#define PHY2RST (*(volatile unsigned char *) (PHY2BASE)) /* reset */
4713 +#define PHY2CTRL (*(volatile unsigned char *) (PHY2BASE+0x5)) /* control */
4714 +#define PHY2RACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x50))
4715 +#define PHY2TACPCTRL (*(volatile unsigned char *) (PHY2BASE+0x60))
4716 +#define PHY2RACPINT (*(volatile unsigned char *) (PHY2BASE+0x51))
4717 +
4718 +/*-------------------*/
4719 +/* Avalanche ATM SAR */
4720 +/*-------------------*/
4721 +
4722 +#define AVSAR_SYSCONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000000)) /* SAR system config register */
4723 +#define AVSAR_SYSSTATUS (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000004)) /* SAR system status register */
4724 +#define AVSAR_INT_ENABLE (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000008)) /* SAR interrupt enable register */
4725 +#define AVSAR_CONN_VPI_VCI (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000000c)) /* VPI/VCI connection config */
4726 +#define AVSAR_CONN_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000010)) /* Connection config register */
4727 +#define AVSAR_OAM_CONFIG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018)) /* OAM configuration register */
4728 +
4729 +/* Transmit completion ring registers */
4730 +
4731 +#define AVSAR_TCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000100))
4732 +#define AVSAR_TCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000104))
4733 +#define AVSAR_TCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000108))
4734 +#define AVSAR_TCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000010c))
4735 +#define AVSAR_TCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000110))
4736 +#define AVSAR_TCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000114))
4737 +#define AVSAR_TCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000118))
4738 +#define AVSAR_TCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000011c))
4739 +#define AVSAR_TCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000120))
4740 +#define AVSAR_TCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000124))
4741 +#define AVSAR_TCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000128))
4742 +#define AVSAR_TCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000012c))
4743 +#define AVSAR_TCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000130))
4744 +#define AVSAR_TCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000134))
4745 +
4746 +/* Transmit Queue Packet registers */
4747 +#define AVSAR_TXQUEUE_PKT0 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000140))
4748 +#define AVSAR_TXQUEUE_PKT1 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000144))
4749 +#define AVSAR_TXQUEUE_PKT2 (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000148))
4750 +#define AVSAR_TX_FLUSH (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000014C))
4751 +/* Receive completion ring registers */
4752 +
4753 +#define AVSAR_RCRAPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000200))
4754 +#define AVSAR_RCRASIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000204))
4755 +#define AVSAR_RCRAINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000208))
4756 +#define AVSAR_RCRATOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000020c))
4757 +#define AVSAR_RCRAFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000210))
4758 +#define AVSAR_RCRAPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000214))
4759 +#define AVSAR_RCRAENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000218))
4760 +#define AVSAR_RCRBPTR (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000021c))
4761 +#define AVSAR_RCRBSIZE (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000220))
4762 +#define AVSAR_RCRBINTTHRESH (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000224))
4763 +#define AVSAR_RCRBTOTENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000228))
4764 +#define AVSAR_RCRBFREEENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x0000022c))
4765 +#define AVSAR_RCRBPENDENT (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000230))
4766 +#define AVSAR_RCRBENTINC (*(volatile unsigned int *)(ATM_SAR_BASE+0x00000234))
4767 +
4768 +#define AVSAR_RXFBL_ADD0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000240)) /* Rx Free buffer list add 0 */
4769 +#define AVSAR_RXFBL_ADD1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000244)) /* Rx Free buffer list add 1 */
4770 +#define AVSAR_RXFBL_ADD2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000248)) /* Rx Free buffer list add 2 */
4771 +#define AVSAR_RXFBLSIZE_0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000028c)) /* Rx Free buffer list size 0 */
4772 +#define AVSAR_RXFBLSIZE_1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x0000029c)) /* Rx Free buffer list size 1 */
4773 +#define AVSAR_RXFBLSIZE_2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002ac)) /* Rx Free buffer list size 2 */
4774 +#define AVSAR_RXFBLSIZE_3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000002bc)) /* Rx Free buffer list size 3 */
4775 +
4776 +
4777 +#if defined(CONFIG_MIPS_EVM3D) || defined(CONFIG_MIPS_AR5D01) || defined(CONFIG_MIPS_AR5W01)
4778 +
4779 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010480))
4780 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010484))
4781 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010488))
4782 +#define AVSAR_OAM_CPID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E0))
4783 +#define AVSAR_OAM_LLID0 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F0))
4784 +#define AVSAR_OAM_CPID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E4))
4785 +#define AVSAR_OAM_LLID1 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F4))
4786 +#define AVSAR_OAM_CPID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104E8))
4787 +#define AVSAR_OAM_LLID2 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104F8))
4788 +#define AVSAR_OAM_CPID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104EC))
4789 +#define AVSAR_OAM_LLID3 (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104FC))
4790 +#define AVSAR_OAM_CORR_TAG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010500))
4791 +#define AVSAR_OAM_FAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010520))
4792 +#define AVSAR_OAM_NEAR_COUNT (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010540))
4793 +#define AVSAR_OAM_CONFIG_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00000018))
4794 +#define AVSAR_FAIRNESS_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x000104B8))
4795 +#define AVSAR_UBR_PCR_REG (*(volatile unsigned int*)(ATM_SAR_BASE+0x00010490))
4796 +
4797 +
4798 +/*
4799 +
4800 +#define OAM_CPID_ADD 0xa30104e0
4801 +
4802 +#define OAM_LLID_ADD 0xa30104f0
4803 +
4804 +#define OAM_LLID_VAL 0xffffffff
4805 +
4806 +#define OAM_CORR_TAG 0xa3010500
4807 +
4808 +#define OAM_FAR_COUNT_ADD 0xa3010520
4809 +
4810 +#define OAM_NEAR_COUNT_ADD 0xa3010540
4811 +
4812 +#define OAM_CONFIG_REG_ADD 0xa3000018
4813 +*/
4814 +
4815 +
4816 +#else /* CONFIG_MIPS_EVM3 || CONFIG_MIPS_ACPEP */
4817 +
4818 +#define AVSAR_SAR_FREQUENCY (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012000))
4819 +#define AVSAR_OAM_CC_SINK (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012004))
4820 +#define AVSAR_OAM_AIS_RDI_RX (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012008))
4821 +#define AVSAR_OAM_CPID (*(volatile unsigned int*)(ATM_SAR_BASE+0x00012300))
4822 +
4823 +#endif /* CONFIG_MIPS_EVM3D || CONFIG_MIPS_AR5D01 || CONFIG_MIPS_AR5W01 */
4824 +
4825 +
4826 +#define AVSAR_STATE_RAM (ATM_SAR_BASE + 0x010000) /* SAR state RAM */
4827 +#define AVSAR_PDSP_BASE (ATM_SAR_BASE + 0x020000) /* SAR PDSP base address */
4828 +#define AVSAR_TXDMA_BASE (ATM_SAR_BASE + 0x030000) /* Transmit DMA state base */
4829 +#define AVSAR_TDMASTATE6 0x18 /* Transmit DMA state word 6 */
4830 +#define AVSAR_RXDMA_BASE (ATM_SAR_BASE + 0x040000) /* Receive DMA state base */
4831 +#define AVSAR_RDMASTATE0 0x0 /* Receive DMA state word 0 */
4832 +
4833 +/*------------------------------------------*/
4834 +/* DSL Interface */
4835 +/*------------------------------------------*/
4836 +
4837 +#define AVDSL_TX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000000))
4838 +#define AVDSL_RX_EN (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000004))
4839 +#define AVDSL_POLL (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000008))
4840 +
4841 +/* Fast */
4842 +
4843 +#define AVDSL_TX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000000C))
4844 +#define AVDSL_TX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000010))
4845 +#define AVDSL_TX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000014))
4846 +#define AVDSL_TX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000018))
4847 +#define AVDSL_RX_FIFO_ADDR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000001C))
4848 +#define AVDSL_RX_FIFO_BASE0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000020))
4849 +#define AVDSL_RX_FIFO_LEN0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000024))
4850 +#define AVDSL_RX_FIFO_PR0 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000028))
4851 +
4852 +/* Interleaved */
4853 +
4854 +#define AVDSL_TX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000002C))
4855 +#define AVDSL_TX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000030))
4856 +#define AVDSL_TX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000034))
4857 +#define AVDSL_TX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000038))
4858 +#define AVDSL_RX_FIFO_ADDR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x0000003C))
4859 +#define AVDSL_RX_FIFO_BASE1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000040))
4860 +#define AVDSL_RX_FIFO_LEN1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000044))
4861 +#define AVDSL_RX_FIFO_PR1 (*(volatile unsigned int *)(DSL_IF_BASE + 0x00000048))
4862 +
4863 +/*------------------------------------------*/
4864 +/* Broadband I/F */
4865 +/*------------------------------------------*/
4866 +
4867 +#define AVBBIF_BBIF_CNTRL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000000))
4868 +#define AVBBIF_ADDR_TRANS_0 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000004))
4869 +#define AVBBIF_ADDR_TRANS_1 (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000008))
4870 +#define AVBBIF_ADDR_XB_MX_BL (*(volatile unsigned int *)(BBIF_CONTROL + 0x0000000C))
4871 +#define AVBBIF_INFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000010))
4872 +#define AVBBIF_OUTFIFO_LVL (*(volatile unsigned int *)(BBIF_CONTROL + 0x00000014))
4873 +
4874 +#define AVBBIF_DISABLED 0x0
4875 +#define AVBBIF_LBT4040_INT 0x1
4876 +#define AVBBIF_XBUS 0x2
4877 +#define AVBBIF_LBT4040_EXT 0x4
4878 +
4879 +#define AVBBIF_ADDR_MASK0 0xff000000 /* handles upper bits of BBIF 0 address */
4880 +#define AVBBIF_ADDR_MASK1 0xff800000 /* handles upper bits of BBIF 1 address */
4881 +#define AVBBIF_TRANS_MASK 0xff000000
4882 +/*------------------------------------------*/
4883 +/* GPIO I/F */
4884 +/*------------------------------------------*/
4885 +
4886 +#define GPIO_DATA_INPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000000))
4887 +#define GPIO_DATA_OUTPUT (*(volatile unsigned int *)(GPIO_BASE + 0x00000004))
4888 +#define GPIO_DATA_DIR (*(volatile unsigned int *)(GPIO_BASE + 0x00000008)) /* 0=output 1=input */
4889 +#define GPIO_DATA_ENABLE (*(volatile unsigned int *)(GPIO_BASE + 0x0000000C)) /* 0=GPIO Mux 1=GPIO */
4890 +
4891 +#define GPIO_0 (1<<21)
4892 +#define GPIO_1 (1<<22)
4893 +#define GPIO_2 (1<<23)
4894 +#define GPIO_3 (1<<24)
4895 +#define EINT_1 (1<<18)
4896 +
4897 +/*
4898 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4899 + If you reset the GPIO interface all of the directions (i/o) of the UART B
4900 + interface pins are inputs and must be reconfigured so as not to lose the
4901 + serial console interface
4902 + JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE JAH NOTE
4903 +*/
4904 +
4905 +/*------------------------------------------*/
4906 +/* CLK_CTRL */
4907 +/*------------------------------------------*/
4908 +#define PERIPH_CLK_CTL (*(volatile unsigned int *)(CLK_CTRL_BASE + 0x00000004))
4909 +
4910 +#define PCLK_0_HALF_VBUS (0<<16)
4911 +#define PCLK_EQ_INPUT (1<<16)
4912 +#define BBIF_CLK_HALF_VBUS (0<<17)
4913 +#define BBIF_CLK_EQ_VBUS (1<<17)
4914 +#define BBIF_CLK_EQ_BBCLK (3<<17)
4915 +#define DSP_MODCLK_DSPCLKI (0<<20)
4916 +#define DSP_MODCLK_REFCLKI (1<<20)
4917 +#define USB_CLK_EQ_USBCLKI (0<<21)
4918 +#define USB_CLK_EQ_REFCLKI (1<<21)
4919 +
4920 +/*------------------------------------------*/
4921 +/* PCI Control Registers */
4922 +/*------------------------------------------*/
4923 +#define PCIC_CONTROL (*(volatile unsigned int *)(PCI_CONFIG_BASE))
4924 +#define PCIC_CONTROL_CFG_DONE (1<<0)
4925 +#define PCIC_CONTROL_DIS_SLAVE_TO (1<<1)
4926 +#define PCIC_CONTROL_FORCE_DELAY_READ (1<<2)
4927 +#define PCIC_CONTROL_FORCE_DELAY_READ_LINE (1<<3)
4928 +#define PCIC_CONTROL_FORCE_DELAY_READ_MULT (1<<4)
4929 +#define PCIC_CONTROL_MEM_SPACE_EN (1<<5)
4930 +#define PCIC_CONTROL_MEM_MASK (1<<6)
4931 +#define PCIC_CONTROL_IO_SPACE_EN (1<<7)
4932 +#define PCIC_CONTROL_IO_MASK (1<<8)
4933 +/* PCIC_CONTROL_RESERVED (1<<9) */
4934 +#define PCIC_CONTROL_BASE0_EN (1<<10)
4935 +#define PCIC_CONTROL_BASE1_EN (1<<11)
4936 +#define PCIC_CONTROL_BASE2_EN (1<<12)
4937 +#define PCIC_CONTROL_HOLD_MASTER_WRITE (1<<13)
4938 +#define PCIC_CONTROL_ARBITER_EN (1<<14)
4939 +#define PCIC_INT_SOURCE (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000004))
4940 +#define PCIC_INT_SOURCE_PWR_MGMT (1<<0)
4941 +#define PCIC_INT_SOURCE_PCI_TARGET (1<<1)
4942 +#define PCIC_INT_SOURCE_PCI_MASTER (1<<2)
4943 +#define PCIC_INT_SOURCE_POWER_WAKEUP (1<<3)
4944 +#define PCIC_INT_SOURCE_PMEIN (1<<4)
4945 +/* PCIC_INT_SOURCE_RESERVED (1<<5) */
4946 +/* PCIC_INT_SOURCE_RESERVED (1<<6) */
4947 +#define PCIC_INT_SOURCE_PIC_INTA (1<<7)
4948 +#define PCIC_INT_SOURCE_PIC_INTB (1<<8)
4949 +#define PCIC_INT_SOURCE_PIC_INTC (1<<9)
4950 +#define PCIC_INT_SOURCE_PIC_INTD (1<<10)
4951 +#define PCIC_INT_SOURCE_SOFT_INT0 (1<<11)
4952 +#define PCIC_INT_SOURCE_SOFT_INT1 (1<<12)
4953 +#define PCIC_INT_SOURCE_SOFT_INT2 (1<<13)
4954 +#define PCIC_INT_SOURCE_SOFT_INT3 (1<<14)
4955 +#define PCIC_INT_CLEAR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000008))
4956 +#define PCIC_INT_CLEAR_PM (1<<0)
4957 +#define PCIC_INT_CLEAR_PCI_TARGET (1<<1)
4958 +#define PCIC_INT_CLEAR_PCI_MASTER (1<<2)
4959 +/* PCIC_INT_CLEAR_RESERVED (1<<3) */
4960 +#define PCIC_INT_CLEAR_PMEIN (1<<4)
4961 +/* PCIC_INT_CLEAR_RESERVED (1<<5) */
4962 +/* PCIC_INT_CLEAR_RESERVED (1<<6) */
4963 +#define PCIC_INT_CLEAR_PCI_INTA (1<<7)
4964 +#define PCIC_INT_CLEAR_PCI_INTB (1<<8)
4965 +#define PCIC_INT_CLEAR_PCI_INTC (1<<9)
4966 +#define PCIC_INT_CLEAR_PCI_INTD (1<<10)
4967 +#define PCIC_INT_CLEAR_SOFT_INT0 (1<<11)
4968 +#define PCIC_INT_CLEAR_SOFT_INT1 (1<<12)
4969 +#define PCIC_INT_CLEAR_SOFT_INT2 (1<<13)
4970 +#define PCIC_INT_CLEAR_SOFT_INT3 (1<<14)
4971 +#define PCIC_INT_EN_AVAL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000000c))
4972 +#define PCIC_INT_EN_AVAL_PM (1<<0)
4973 +#define PCIC_INT_EN_AVAL_PCI_TARGET (1<<1)
4974 +#define PCIC_INT_EN_AVAL_PCI_MASTER (1<<2)
4975 +/* PCIC_INT_EN_AVAL_RESERVED (1<<3) */
4976 +#define PCIC_INT_EN_AVAL_PMEIN (1<<4)
4977 +/* PCIC_INT_EN_AVAL_RESERVED (1<<5) */
4978 +/* PCIC_INT_EN_AVAL_RESERVED (1<<6) */
4979 +#define PCIC_INT_EN_AVAL_PCI_INTA (1<<7)
4980 +#define PCIC_INT_EN_AVAL_PCI_INTB (1<<8)
4981 +#define PCIC_INT_EN_AVAL_PCI_INTC (1<<9)
4982 +#define PCIC_INT_EN_AVAL_PCI_INTD (1<<10)
4983 +#define PCIC_INT_EN_AVAL_SOFT_INT0 (1<<11)
4984 +#define PCIC_INT_EN_AVAL_SOFT_INT1 (1<<12)
4985 +#define PCIC_INT_EN_AVAL_SOFT_INT2 (1<<13)
4986 +#define PCIC_INT_EN_AVAL_SOFT_INT3 (1<<14)
4987 +#define PCIC_INT_EN_PCI (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000010))
4988 +#define PCIC_INT_EN_PCI_PM (1<<0)
4989 +#define PCIC_INT_EN_PCI_PCI_TARGET (1<<1)
4990 +#define PCIC_INT_EN_PCI_PCI_MASTER (1<<2)
4991 +/* PCIC_INT_EN_PCI_RESERVED (1<<3) */
4992 +#define PCIC_INT_EN_PCI_PMEIN (1<<4)
4993 +/* PCIC_INT_EN_PCI_RESERVED (1<<5) */
4994 +/* PCIC_INT_EN_PCI_RESERVED (1<<6) */
4995 +#define PCIC_INT_EN_PCI_PCI_INTA (1<<7)
4996 +#define PCIC_INT_EN_PCI_PCI_INTB (1<<8)
4997 +#define PCIC_INT_EN_PCI_PCI_INTC (1<<9)
4998 +#define PCIC_INT_EN_PCI_PCI_INTD (1<<10)
4999 +#define PCIC_INT_EN_PCI_SOFT_INT0 (1<<11)
5000 +#define PCIC_INT_EN_PCI_SOFT_INT1 (1<<12)
5001 +#define PCIC_INT_EN_PCI_SOFT_INT2 (1<<13)
5002 +#define PCIC_INT_EN_PCI_SOFT_INT3 (1<<14)
5003 +#define PCIC_INT_SWSET (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000014))
5004 +#define PCIC_INT_SWSET_SOFT_INT0 (1<<0)
5005 +#define PCIC_INT_SWSET_SOFT_INT1 (1<<1)
5006 +#define PCIC_INT_SWSET_SOFT_INT2 (1<<2)
5007 +#define PCIC_INT_SWSET_SOFT_INT3 (1<<3)
5008 +#define PCIC_PM_CTL (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000018))
5009 +#define PCIC_PM_CTL_PWR_STATE_MASK (0x02)
5010 +/* PCIC_PM_CTL_RESERVED (1<<2) */
5011 +/* PCIC_PM_CTL_RESERVED (1<<3) */
5012 +/* PCIC_PM_CTL_RESERVED (1<<4) */
5013 +/* PCIC_PM_CTL_RESERVED (1<<5) */
5014 +/* PCIC_PM_CTL_RESERVED (1<<6) */
5015 +/* PCIC_PM_CTL_RESERVED (1<<7) */
5016 +/* PCIC_PM_CTL_RESERVED (1<<8) */
5017 +/* PCIC_PM_CTL_RESERVED (1<<9) */
5018 +#define PCIC_PM_CTL_PWR_SUPPORT (1<<10)
5019 +#define PCIC_PM_CTL_PMEIN (1<<11)
5020 +#define PCIC_PM_CTL_CAP_MASK (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x0000001a))
5021 +#define PCIC_PM_CONSUME (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000001c))
5022 +#define PCIC_PM_CONSUME_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001c))
5023 +#define PCIC_PM_CONSUME_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001d))
5024 +#define PCIC_PM_CONSUME_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001e))
5025 +#define PCIC_PM_CONSUME_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x0000001f))
5026 +#define PCIC_PM_DISSAPATED (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000020))
5027 +#define PCIC_PM_DISSAPATED_D0 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000020))
5028 +#define PCIC_PM_DISSAPATED_D1 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000021))
5029 +#define PCIC_PM_DISSAPATED_D2 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000022))
5030 +#define PCIC_PM_DISSAPATED_D3 (*(volatile unsigned char *)(PCI_CONFIG_BASE + 0x00000023))
5031 +#define PCIC_PM_DATA_SCALE (*(volatile unsigned short int *)(PCI_CONFIG_BASE + 0x00000024))
5032 +#define PCIC_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000028))
5033 +#define PCIC_SUB_VEND_DEV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000002c))
5034 +#define PCIC_CLASS_REV_ID (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000030))
5035 +#define PCIC_MAX_MIN (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000034))
5036 +#define PCIC_MAST_MEM_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000003c))
5037 +#define PCIC_MAST_MEM_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000040))
5038 +#define PCIC_MAST_MEM_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000044))
5039 +#define PCIC_SLAVE_MASK0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000004c))
5040 +#define PCIC_SLAVE_MASK1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000050))
5041 +#define PCIC_SLAVE_MASK2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000054))
5042 +#define PCIC_SLAVE_BASE_AT0 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000058))
5043 +#define PCIC_SLAVE_BASE_AT1 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x0000005c))
5044 +#define PCIC_SLAVE_BASE_AT2 (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000060))
5045 +#define PCIC_CONF_COMMAND (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000090))
5046 +#define PCIC_CONF_ADDR (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000094))
5047 +#define PCIC_CONF_DATA (*(volatile unsigned int *)(PCI_CONFIG_BASE + 0x00000098))
5048 +
5049 +/*------------------------------------------*/
5050 +/* IIC_INTERFACE */
5051 +/*------------------------------------------*/
5052 +#define I2C_DATA_HI (*(volatile unsigned int *)(I2C_BASE + 0x0))
5053 +#define I2C_DATA_LOW (*(volatile unsigned int *)(I2C_BASE + 0x4))
5054 +#define I2C_CONFIG (*(volatile unsigned int *)(I2C_BASE + 0x8))
5055 +#define I2C_DATA_READ (*(volatile unsigned int *)(I2C_BASE + 0xC))
5056 +#define I2C_CLOCK_DIV (*(volatile unsigned int *)(I2C_BASE + 0x10))
5057 +
5058 +#define I2CWRITE 0x200
5059 +#define I2CREAD 0x300
5060 +#define I2C_END_BURST 0x400
5061 +
5062 +/* read bits */
5063 +#define I2C_READ_ERROR 0x8000
5064 +#define I2C_READ_COMPLETE 0x4000
5065 +#define I2C_READ_BUSY 0x2000
5066 +
5067 +/* device types */
5068 +#define I2C_IO_EXPANDER 0x2
5069 +#define I2C_RTC 0xd
5070 +
5071 +/* device Addresses on I2C bus (EVM3) */
5072 +#define SEVEN_SEGMENT_DISP 0x23 /* Device type = 0x2, Addr = 3 */
5073 +#define EVM3_RTC 0xd0 /* Device type = 0xd, Addr = 0 */
5074 +#define EVM3_RTC_I2C_ADDR 0x0
5075 +
5076 +/*------------------------------------------*/
5077 +/* Ethernet MAC register offset definitions */
5078 +/*------------------------------------------*/
5079 +#define VMAC_DMACONFIG(X) (*(volatile unsigned int *)(X + 0x00000000))
5080 +#define VMAC_INTSTS(X) (*(volatile unsigned int *)(X + 0x00000004))
5081 +#define VMAC_INTMASK(X) (*(volatile unsigned int *)(X + 0x00000008))
5082 +
5083 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
5084 +#define VMAC_STATSBASE(X) (*(volatile unsigned int *)(X + 0x00000400))
5085 +
5086 +#define VMAC_TCRPTR(X) (*(volatile unsigned int *)(X + 0x00000100))
5087 +#define VMAC_TCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000104))
5088 +#define VMAC_TCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000108))
5089 +#define VMAC_TCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000010C))
5090 +#define VMAC_TCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000110))
5091 +#define VMAC_TCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000114))
5092 +#define VMAC_TCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000118))
5093 +#define VMAC_TXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000011c))
5094 +
5095 +
5096 +#define VMAC_TDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000120))
5097 +#define VMAC_TDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000124))
5098 +#define VMAC_TDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000128))
5099 +#define VMAC_TDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000012C))
5100 +#define VMAC_TDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000130))
5101 +#define VMAC_TDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000134))
5102 +#define VMAC_TDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000138))
5103 +#define VMAC_TDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000013C))
5104 +#define VMAC_TXPADDCNT(X) (*(volatile unsigned int *)(X + 0x00000140))
5105 +#define VMAC_TXPADDSTART(X) (*(volatile unsigned int *)(X + 0x00000144))
5106 +#define VMAC_TXPADDEND(X) (*(volatile unsigned int *)(X + 0x00000148))
5107 +#define VMAC_TXQFLUSH(X) (*(volatile unsigned int *)(X + 0x0000014C))
5108 +
5109 +#define VMAC_RCRPTR(X) (*(volatile unsigned int *)(X + 0x00000200))
5110 +#define VMAC_RCRSIZE(X) (*(volatile unsigned int *)(X + 0x00000204))
5111 +#define VMAC_RCRINTTHRESH(X) (*(volatile unsigned int *)(X + 0x00000208))
5112 +#define VMAC_RCRTOTENT(X) (*(volatile unsigned int *)(X + 0x0000020C))
5113 +#define VMAC_RCRFREEENT(X) (*(volatile unsigned int *)(X + 0x00000210))
5114 +#define VMAC_RCRPENDENT(X) (*(volatile unsigned int *)(X + 0x00000214))
5115 +#define VMAC_RCRENTINC(X) (*(volatile unsigned int *)(X + 0x00000218))
5116 +#define VMAC_RXISRPACE(X) (*(volatile unsigned int *)(X + 0x0000021c))
5117 +
5118 +#define VMAC_RDMASTATE0(X) (*(volatile unsigned int *)(X + 0x00000220))
5119 +#define VMAC_RDMASTATE1(X) (*(volatile unsigned int *)(X + 0x00000224))
5120 +#define VMAC_RDMASTATE2(X) (*(volatile unsigned int *)(X + 0x00000228))
5121 +#define VMAC_RDMASTATE3(X) (*(volatile unsigned int *)(X + 0x0000022C))
5122 +#define VMAC_RDMASTATE4(X) (*(volatile unsigned int *)(X + 0x00000230))
5123 +#define VMAC_RDMASTATE5(X) (*(volatile unsigned int *)(X + 0x00000234))
5124 +#define VMAC_RDMASTATE6(X) (*(volatile unsigned int *)(X + 0x00000238))
5125 +#define VMAC_RDMASTATE7(X) (*(volatile unsigned int *)(X + 0x0000023C))
5126 +#define VMAC_FBLADDCNT(X) (*(volatile unsigned int *)(X + 0x00000240))
5127 +#define VMAC_FBLADDSTART(X) (*(volatile unsigned int *)(X + 0x00000244))
5128 +#define VMAC_FBLADDEND(X) (*(volatile unsigned int *)(X + 0x00000248))
5129 +#define VMAC_RXONOFF(X) (*(volatile unsigned int *)(X + 0x0000024C))
5130 +
5131 +#define VMAC_FBL0NEXTD(X) (*(volatile unsigned int *)(X + 0x00000280))
5132 +#define VMAC_FBL0LASTD(X) (*(volatile unsigned int *)(X + 0x00000284))
5133 +#define VMAC_FBL0COUNTD(X) (*(volatile unsigned int *)(X + 0x00000288))
5134 +#define VMAC_FBL0BUFSIZE(X) (*(volatile unsigned int *)(X + 0x0000028C))
5135 +
5136 +#define VMAC_MACCONTROL(X) (*(volatile unsigned int *)(X + 0x00000300))
5137 +#define VMAC_MACSTATUS(X) (*(volatile unsigned int *)(X + 0x00000304))
5138 +#define VMAC_MACADDRHI(X) (*(volatile unsigned int *)(X + 0x00000308))
5139 +#define VMAC_MACADDRLO(X) (*(volatile unsigned int *)(X + 0x0000030C))
5140 +#define VMAC_MACHASH1(X) (*(volatile unsigned int *)(X + 0x00000310))
5141 +#define VMAC_MACHASH2(X) (*(volatile unsigned int *)(X + 0x00000314))
5142 +
5143 +#define VMAC_WRAPCLK(X) (*(volatile unsigned int *)(X + 0x00000340))
5144 +#define VMAC_BOFTEST(X) (*(volatile unsigned int *)(X + 0x00000344))
5145 +#define VMAC_PACTEST(X) (*(volatile unsigned int *)(X + 0x00000348))
5146 +#define VMAC_PAUSEOP(X) (*(volatile unsigned int *)(X + 0x0000034C))
5147 +
5148 +#define VMAC_MDIOCONTROL(X) (*(volatile unsigned int *)(X + 0x00000380))
5149 +#define VMAC_MDIOUSERACCESS(X) (*(volatile unsigned int *)(X +0x00000384))
5150 +#define VMAC_MDIOACK(X) (*(volatile unsigned int *)(X + 0x00000388))
5151 +#define VMAC_MDIOLINK(X) (*(volatile unsigned int *)(X + 0x0000038C))
5152 +#define VMAC_MDIOMACPHY(X) (*(volatile unsigned int *)(X + 0x00000390))
5153 +
5154 +#define VMAC_STATS_BASE(X) (X + 0x00000400)
5155 +
5156 +#endif
5157 +
5158 +
5159 +
5160 +
5161 +
5162 +
5163 diff -urN linux.old/include/asm-mips/ar7/hal/haltypes.h linux.dev/include/asm-mips/ar7/hal/haltypes.h
5164 --- linux.old/include/asm-mips/ar7/hal/haltypes.h 1970-01-01 01:00:00.000000000 +0100
5165 +++ linux.dev/include/asm-mips/ar7/hal/haltypes.h 2005-07-09 08:00:15.303024000 +0200
5166 @@ -0,0 +1,46 @@
5167 +/******************************************************************************
5168 + * FILE PURPOSE: Platform dependent type information Header
5169 + ********************************************************************************
5170 + * FILE NAME: haltypes.h
5171 + *
5172 + * DESCRIPTION: Platform dependent (tuned) types definations.
5173 + * Intented to be used by HAL/Drivers etc.
5174 + *
5175 + * REVISION HISTORY:
5176 + * 27 Nov 02 - PSP TII
5177 + *
5178 + * (C) Copyright 2002, Texas Instruments, Inc
5179 + *******************************************************************************/
5180 +
5181 +#ifndef __HAL_TYPES_H__
5182 +#define __HAL_TYPES_H__
5183 +
5184 +typedef char INT8;
5185 +typedef short INT16;
5186 +typedef int INT32;
5187 +
5188 +typedef unsigned char UINT8;
5189 +typedef unsigned short UINT16;
5190 +typedef unsigned int UINT32;
5191 +
5192 +typedef unsigned char UCHAR;
5193 +typedef unsigned short USHORT;
5194 +typedef unsigned int UINT;
5195 +typedef unsigned long ULONG;
5196 +
5197 +typedef int BOOL;
5198 +typedef int STATUS;
5199 +
5200 +#ifndef FALSE
5201 +#define FALSE 0
5202 +#endif
5203 +
5204 +#ifndef TRUE
5205 +#define TRUE 1
5206 +#endif
5207 +
5208 +#ifndef NULL
5209 +#define NULL 0
5210 +#endif
5211 +
5212 +#endif /* __HAL_TYPES_H__ */
5213 diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h
5214 --- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100
5215 +++ linux.dev/include/asm-mips/ar7/if_port.h 2005-07-09 08:00:15.304024000 +0200
5216 @@ -0,0 +1,26 @@
5217 +/*******************************************************************************
5218 + * FILE PURPOSE: Interface port id Header file
5219 + *******************************************************************************
5220 + * FILE NAME: if_port.h
5221 + *
5222 + * DESCRIPTION: Header file carrying information about port ids of interfaces
5223 + *
5224 + *
5225 + * (C) Copyright 2003, Texas Instruments, Inc
5226 + ******************************************************************************/
5227 +#ifndef _IF_PORT_H_
5228 +#define _IF_PORT_H_
5229 +
5230 +#define AVALANCHE_CPMAC_LOW_PORT_ID 0
5231 +#define AVALANCHE_CPMAC_HIGH_PORT_ID 1
5232 +#define AVALANCHE_USB_PORT_ID 2
5233 +#define AVALANCHE_WLAN_PORT_ID 3
5234 +
5235 +
5236 +#define AVALANCHE_MARVELL_BASE_PORT_ID 4
5237 +
5238 +/* The marvell ports occupy port ids from 4 to 8 */
5239 +/* so the next port id number should start at 9 */
5240 +
5241 +
5242 +#endif /* _IF_PORT_H_ */
5243 diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h
5244 --- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100
5245 +++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-07-09 08:00:15.304024000 +0200
5246 @@ -0,0 +1,77 @@
5247 +#ifndef _SANGAM_BOARDS_H
5248 +#define _SANGAM_BOARDS_H
5249 +
5250 +// Let us define board specific information here.
5251 +
5252 +
5253 +#if defined(CONFIG_AR7DB)
5254 +
5255 +#define AFECLK_FREQ 35328000
5256 +#define REFCLK_FREQ 25000000
5257 +#define OSC3_FREQ 24000000
5258 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5259 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
5260 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5261 +
5262 +#endif
5263 +
5264 +
5265 +#if defined(CONFIG_AR7RD)
5266 +#define AFECLK_FREQ 35328000
5267 +#define REFCLK_FREQ 25000000
5268 +#define OSC3_FREQ 24000000
5269 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5270 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
5271 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5272 +#endif
5273 +
5274 +
5275 +#if defined(CONFIG_AR7WI)
5276 +#define AFECLK_FREQ 35328000
5277 +#define REFCLK_FREQ 25000000
5278 +#define OSC3_FREQ 24000000
5279 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5280 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
5281 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5282 +#endif
5283 +
5284 +
5285 +#if defined(CONFIG_AR7V)
5286 +#define AFECLK_FREQ 35328000
5287 +#define REFCLK_FREQ 25000000
5288 +#define OSC3_FREQ 24000000
5289 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5290 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2
5291 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5292 +#endif
5293 +
5294 +
5295 +#if defined(CONFIG_AR7WRD)
5296 +#define AFECLK_FREQ 35328000
5297 +#define REFCLK_FREQ 25000000
5298 +#define OSC3_FREQ 24000000
5299 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5300 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
5301 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5302 +#endif
5303 +
5304 +
5305 +#if defined(CONFIG_AR7VWI)
5306 +#define AFECLK_FREQ 35328000
5307 +#define REFCLK_FREQ 25000000
5308 +#define OSC3_FREQ 24000000
5309 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000
5310 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000
5311 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000
5312 +#endif
5313 +
5314 +
5315 +#if defined CONFIG_SEAD2
5316 +#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA
5317 +#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555
5318 +#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0
5319 +#include <asm/mips-boards/sead.h>
5320 +#endif
5321 +
5322 +
5323 +#endif
5324 diff -urN linux.old/include/asm-mips/ar7/sangam_clk_cntl.h linux.dev/include/asm-mips/ar7/sangam_clk_cntl.h
5325 --- linux.old/include/asm-mips/ar7/sangam_clk_cntl.h 1970-01-01 01:00:00.000000000 +0100
5326 +++ linux.dev/include/asm-mips/ar7/sangam_clk_cntl.h 2005-07-09 08:00:15.304024000 +0200
5327 @@ -0,0 +1,25 @@
5328 +/*****************************************************************************
5329 + * Clock Control
5330 + *****************************************************************************/
5331 +#ifndef _SANGAM_CLK_CNTL_H_
5332 +#define _SANGAM_CLK_CNTL_H_
5333 +#include <asm/ar7/avalanche_misc.h>
5334 +
5335 +#define CLK_MHZ(x) ( (x) * 1000000 )
5336 +
5337 +/* The order of ENUMs here should not be altered since
5338 + * the register addresses are derived from the order
5339 + */
5340 +
5341 +typedef enum AVALANCHE_CLKC_ID_tag
5342 +{
5343 + CLKC_VBUS,
5344 + CLKC_MIPS,
5345 + CLKC_USB,
5346 + CLKC_SYS
5347 +} AVALANCHE_CLKC_ID_T;
5348 +
5349 +void avalanche_clkc_init(unsigned int afe_clk,unsigned int refclk, unsigned int xtal3in);
5350 +int avalanche_clkc_set_freq(AVALANCHE_CLKC_ID_T clk_id, unsigned int output_freq);
5351 +unsigned int avalanche_clkc_get_freq(AVALANCHE_CLKC_ID_T clk_id);
5352 +#endif
5353 diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h
5354 --- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100
5355 +++ linux.dev/include/asm-mips/ar7/sangam.h 2005-07-09 08:00:15.305023000 +0200
5356 @@ -0,0 +1,180 @@
5357 +#ifndef _SANGAM_H_
5358 +#define _SANGAM_H_
5359 +
5360 +#include <linux/config.h>
5361 +#include <asm/addrspace.h>
5362 +
5363 +/*----------------------------------------------------
5364 + * Sangam's Module Base Addresses
5365 + *--------------------------------------------------*/
5366 +#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */
5367 +#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */
5368 +#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */
5369 +#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */
5370 +#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */
5371 +#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */
5372 +#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */
5373 +#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */
5374 +#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */
5375 +#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */
5376 +#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */
5377 +#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */
5378 +#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */
5379 +#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */
5380 +#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */
5381 +#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */
5382 +#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */
5383 +#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */
5384 +#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */
5385 +#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */
5386 +#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */
5387 +#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */
5388 +#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */
5389 +#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */
5390 +#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */
5391 +#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */
5392 +#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */
5393 +
5394 +#define AVALANCHE_SDRAM_BASE 0x14000000UL
5395 +
5396 +
5397 +/*----------------------------------------------------
5398 + * Sangam Interrupt Map (Primary Interrupts)
5399 + *--------------------------------------------------*/
5400 +
5401 +#define AVALANCHE_UNIFIED_SECONDARY_INT 0
5402 +#define AVALANCHE_EXT_INT_0 1
5403 +#define AVALANCHE_EXT_INT_1 2
5404 +/* Line# 3 to 4 are reserved */
5405 +#define AVALANCHE_TIMER_0_INT 5
5406 +#define AVALANCHE_TIMER_1_INT 6
5407 +#define AVALANCHE_UART0_INT 7
5408 +#define AVALANCHE_UART1_INT 8
5409 +#define AVALANCHE_DMA_INT0 9
5410 +#define AVALANCHE_DMA_INT1 10
5411 +/* Line# 11 to 14 are reserved */
5412 +#define AVALANCHE_ATM_SAR_INT 15
5413 +/* Line# 16 to 18 are reserved */
5414 +#define AVALANCHE_LOW_CPMAC_INT 19
5415 +/* Line# 20 is reserved */
5416 +#define AVALANCHE_LOW_VLYNQ_INT 21
5417 +#define AVALANCHE_CODEC_WAKEUP_INT 22
5418 +/* Line# 23 is reserved */
5419 +#define AVALANCHE_USB_SLAVE_INT 24
5420 +#define AVALANCHE_HIGH_VLYNQ_INT 25
5421 +/* Line# 26 to 27 are reserved */
5422 +#define AVALANCHE_UNIFIED_PHY_INT 28
5423 +#define AVALANCHE_I2C_INT 29
5424 +#define AVALANCHE_DMA_INT2 30
5425 +#define AVALANCHE_DMA_INT3 31
5426 +/* Line# 32 is reserved */
5427 +#define AVALANCHE_HIGH_CPMAC_INT 33
5428 +/* Line# 34 to 36 is reserved */
5429 +#define AVALANCHE_VDMA_VT_RX_INT 37
5430 +#define AVALANCHE_VDMA_VT_TX_INT 38
5431 +#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39
5432 +
5433 +
5434 +#define AVALANCHE_EMIF_INT 47
5435 +
5436 +
5437 +
5438 +/*-----------------------------------------------------------
5439 + * Sangam's Reset Bits
5440 + *---------------------------------------------------------*/
5441 +
5442 +#define AVALANCHE_UART0_RESET_BIT 0
5443 +#define AVALANCHE_UART1_RESET_BIT 1
5444 +#define AVALANCHE_I2C_RESET_BIT 2
5445 +#define AVALANCHE_TIMER0_RESET_BIT 3
5446 +#define AVALANCHE_TIMER1_RESET_BIT 4
5447 +/* Reset bit 5 is reserved. */
5448 +#define AVALANCHE_GPIO_RESET_BIT 6
5449 +#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7
5450 +#define AVALANCHE_USB_SLAVE_RESET_BIT 8
5451 +#define AVALANCHE_ATM_SAR_RESET_BIT 9
5452 +/* Reset bit 10 is reserved. */
5453 +#define AVALANCHE_VDMA_VT_RESET_BIT 11
5454 +#define AVALANCHE_FSER_RESET_BIT 12
5455 +/* Reset bit 13 to 15 are reserved */
5456 +#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16
5457 +#define AVALANCHE_LOW_CPMAC_RESET_BIT 17
5458 +#define AVALANCHE_MCDMA_RESET_BIT 18
5459 +#define AVALANCHE_BIST_RESET_BIT 19
5460 +#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20
5461 +#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21
5462 +#define AVALANCHE_MDIO_RESET_BIT 22
5463 +#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23
5464 +/* Reset bit 24 to 25 are reserved */
5465 +#define AVALANCHE_LOW_EPHY_RESET_BIT 26
5466 +/* Reset bit 27 to 31 are reserved */
5467 +
5468 +
5469 +#define AVALANCHE_POWER_MODULE_USBSP 0
5470 +#define AVALANCHE_POWER_MODULE_WDTP 1
5471 +#define AVALANCHE_POWER_MODULE_UT0P 2
5472 +#define AVALANCHE_POWER_MODULE_UT1P 3
5473 +#define AVALANCHE_POWER_MODULE_IICP 4
5474 +#define AVALANCHE_POWER_MODULE_VDMAP 5
5475 +#define AVALANCHE_POWER_MODULE_GPIOP 6
5476 +#define AVALANCHE_POWER_MODULE_VLYNQ1P 7
5477 +#define AVALANCHE_POWER_MODULE_SARP 8
5478 +#define AVALANCHE_POWER_MODULE_ADSLP 9
5479 +#define AVALANCHE_POWER_MODULE_EMIFP 10
5480 +#define AVALANCHE_POWER_MODULE_ADSPP 12
5481 +#define AVALANCHE_POWER_MODULE_RAMP 13
5482 +#define AVALANCHE_POWER_MODULE_ROMP 14
5483 +#define AVALANCHE_POWER_MODULE_DMAP 15
5484 +#define AVALANCHE_POWER_MODULE_BISTP 16
5485 +#define AVALANCHE_POWER_MODULE_TIMER0P 18
5486 +#define AVALANCHE_POWER_MODULE_TIMER1P 19
5487 +#define AVALANCHE_POWER_MODULE_EMAC0P 20
5488 +#define AVALANCHE_POWER_MODULE_EMAC1P 22
5489 +#define AVALANCHE_POWER_MODULE_EPHYP 24
5490 +#define AVALANCHE_POWER_MODULE_VLYNQ0P 27
5491 +
5492 +
5493 +
5494 +
5495 +
5496 +/*
5497 + * Sangam board vectors
5498 + */
5499 +
5500 +#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE))
5501 +#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE))
5502 +
5503 +/*-----------------------------------------------------------------------------
5504 + * Sangam's system register.
5505 + *
5506 + *---------------------------------------------------------------------------*/
5507 +#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00))
5508 +#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8)
5509 +#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600))
5510 +#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604))
5511 +#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600))
5512 +
5513 +#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00))
5514 +#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C))
5515 +
5516 +#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0)
5517 +#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4)
5518 +#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8)
5519 +#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC)
5520 +#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14)
5521 +
5522 +/*
5523 + * Yamon Prom print address.
5524 + */
5525 +#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500))
5526 +#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */
5527 +#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34)
5528 +
5529 +#define AVALANCHE_BASE_BAUD ( 3686400 / 16 )
5530 +
5531 +#define AVALANCHE_GPIO_PIN_COUNT 32
5532 +#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0}
5533 +
5534 +#include "sangam_boards.h"
5535 +
5536 +#endif /*_SANGAM_H_ */
5537 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h
5538 --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100
5539 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-09 08:00:15.305023000 +0200
5540 @@ -0,0 +1,42 @@
5541 +/******************************************************************************
5542 + * FILE PURPOSE: TNETD73xx Error Definations Header File
5543 + ******************************************************************************
5544 + * FILE NAME: tnetd73xx_err.h
5545 + *
5546 + * DESCRIPTION: Error definations for TNETD73XX
5547 + *
5548 + * REVISION HISTORY:
5549 + * 27 Nov 02 - PSP TII
5550 + *
5551 + * (C) Copyright 2002, Texas Instruments, Inc
5552 + *******************************************************************************/
5553 +
5554 +
5555 +#ifndef __TNETD73XX_ERR_H__
5556 +#define __TNETD73XX_ERR_H__
5557 +
5558 +typedef enum TNETD73XX_ERR_t
5559 +{
5560 + TNETD73XX_ERR_OK = 0, /* OK or SUCCESS */
5561 + TNETD73XX_ERR_ERROR = -1, /* Unspecified/Generic ERROR */
5562 +
5563 + /* Pointers and args */
5564 + TNETD73XX_ERR_INVARG = -2, /* Invaild argument to the call */
5565 + TNETD73XX_ERR_NULLPTR = -3, /* NULL pointer */
5566 + TNETD73XX_ERR_BADPTR = -4, /* Bad (out of mem) pointer */
5567 +
5568 + /* Memory issues */
5569 + TNETD73XX_ERR_ALLOC_FAIL = -10, /* allocation failed */
5570 + TNETD73XX_ERR_FREE_FAIL = -11, /* free failed */
5571 + TNETD73XX_ERR_MEM_CORRUPT = -12, /* corrupted memory */
5572 + TNETD73XX_ERR_BUF_LINK = -13, /* buffer linking failed */
5573 +
5574 + /* Device issues */
5575 + TNETD73XX_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */
5576 + TNETD73XX_ERR_DEVICE_MALFUNC = -21, /* device malfunction */
5577 +
5578 + TNETD73XX_ERR_INVID = -30 /* Invalid ID */
5579 +
5580 +} TNETD73XX_ERR;
5581 +
5582 +#endif /* __TNETD73XX_ERR_H__ */
5583 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h
5584 --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100
5585 +++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-09 08:00:15.306023000 +0200
5586 @@ -0,0 +1,340 @@
5587 +/******************************************************************************
5588 + * FILE PURPOSE: TNETD73xx Common Header File
5589 + ******************************************************************************
5590 + * FILE NAME: tnetd73xx.h
5591 + *
5592 + * DESCRIPTION: shared typedef's, constants and API for TNETD73xx
5593 + *
5594 + * REVISION HISTORY:
5595 + * 27 Nov 02 - PSP TII
5596 + *
5597 + * (C) Copyright 2002, Texas Instruments, Inc
5598 + *******************************************************************************/
5599 +
5600 +/*
5601 + *
5602 + *
5603 + * These are const, typedef, and api definitions for tnetd73xx.
5604 + *
5605 + * NOTES:
5606 + * 1. This file may be included into both C and Assembly files.
5607 + * - for .s files, please do #define _ASMLANGUAGE in your ASM file to
5608 + * avoid C data types (typedefs) below;
5609 + * - for .c files, you don't have to do anything special.
5610 + *
5611 + * 2. This file has a number of sections for each SOC subsystem. When adding
5612 + * a new constant, find the subsystem you are working on and follow the
5613 + * name pattern. If you are adding another typedef for your interface, please,
5614 + * place it with other typedefs and function prototypes.
5615 + *
5616 + * 3. Please, DO NOT add any macros or types that are local to a subsystem to avoid
5617 + * cluttering. Include such items directly into the module's .c file or have a
5618 + * local .h file to pass data between smaller modules. This file defines only
5619 + * shared items.
5620 + */
5621 +
5622 +#ifndef __TNETD73XX_H__
5623 +#define __TNETD73XX_H__
5624 +
5625 +#ifndef _ASMLANGUAGE /* This part not for assembly language */
5626 +
5627 +#include <linux/types.h>
5628 +
5629 +extern unsigned int tnetd73xx_mips_freq;
5630 +extern unsigned int tnetd73xx_vbus_freq;
5631 +
5632 +#include "tnetd73xx_err.h"
5633 +
5634 +#endif /* _ASMLANGUAGE */
5635 +
5636 +
5637 +/*******************************************************************************************
5638 +* Emerald core specific
5639 +******************************************************************************************** */
5640 +
5641 +#ifdef BIG_ENDIAN
5642 +#elif defined(LITTLE_ENDIAN)
5643 +#else
5644 +#error Need to define endianism
5645 +#endif
5646 +
5647 +#ifndef KSEG_MSK
5648 +#define KSEG_MSK 0xE0000000 /* Most significant 3 bits denote kseg choice */
5649 +#endif
5650 +
5651 +#ifndef KSEG_INV_MASK
5652 +#define KSEG_INV_MASK 0x1FFFFFFF /* Inverted mask for kseg address */
5653 +#endif
5654 +
5655 +#ifndef KSEG0_BASE
5656 +#define KSEG0_BASE 0x80000000
5657 +#endif
5658 +
5659 +#ifndef KSEG1_BASE
5660 +#define KSEG1_BASE 0xA0000000
5661 +#endif
5662 +
5663 +#ifndef KSEG0
5664 +#define KSEG0(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG0_BASE)
5665 +#endif
5666 +
5667 +#ifndef KSEG1
5668 +#define KSEG1(addr) (((u32)(addr) & ~KSEG_MSK) | KSEG1_BASE)
5669 +#endif
5670 +
5671 +#ifndef KUSEG
5672 +#define KUSEG(addr) ((u32)(addr) & ~KSEG_MSK)
5673 +#endif
5674 +
5675 +#ifndef PHYS_ADDR
5676 +#define PHYS_ADDR(addr) ((addr) & KSEG_INV_MASK)
5677 +#endif
5678 +
5679 +#ifndef PHYS_TO_K0
5680 +#define PHYS_TO_K0(addr) (PHYS_ADDR(addr)|KSEG0_BASE)
5681 +#endif
5682 +
5683 +#ifndef PHYS_TO_K1
5684 +#define PHYS_TO_K1(addr) (PHYS_ADDR(addr)|KSEG1_BASE)
5685 +#endif
5686 +
5687 +#ifndef REG8_ADDR
5688 +#define REG8_ADDR(addr) (volatile u8 *)(PHYS_TO_K1(addr))
5689 +#define REG8_DATA(addr) (*(volatile u8 *)(PHYS_TO_K1(addr)))
5690 +#define REG8_WRITE(addr, data) REG8_DATA(addr) = data;
5691 +#define REG8_READ(addr, data) data = (u8) REG8_DATA(addr);
5692 +#endif
5693 +
5694 +#ifndef REG16_ADDR
5695 +#define REG16_ADDR(addr) (volatile u16 *)(PHYS_TO_K1(addr))
5696 +#define REG16_DATA(addr) (*(volatile u16 *)(PHYS_TO_K1(addr)))
5697 +#define REG16_WRITE(addr, data) REG16_DATA(addr) = data;
5698 +#define REG16_READ(addr, data) data = (u16) REG16_DATA(addr);
5699 +#endif
5700 +
5701 +#ifndef REG32_ADDR
5702 +#define REG32_ADDR(addr) (volatile u32 *)(PHYS_TO_K1(addr))
5703 +#define REG32_DATA(addr) (*(volatile u32 *)(PHYS_TO_K1(addr)))
5704 +#define REG32_WRITE(addr, data) REG32_DATA(addr) = data;
5705 +#define REG32_READ(addr, data) data = (u32) REG32_DATA(addr);
5706 +#endif
5707 +
5708 +#ifdef _LINK_KSEG0_ /* Application is linked into KSEG0 space */
5709 +#define VIRT_ADDR(addr) PHYS_TO_K0(PHYS_ADDR(addr))
5710 +#endif
5711 +
5712 +#ifdef _LINK_KSEG1_ /* Application is linked into KSEG1 space */
5713 +#define VIRT_ADDR(addr) PHYS_TO_K1(PHYS_ADDR(addr))
5714 +#endif
5715 +
5716 +#if !defined(_LINK_KSEG0_) && !defined(_LINK_KSEG1_)
5717 +#error You must define _LINK_KSEG0_ or _LINK_KSEG1_ to compile the code.
5718 +#endif
5719 +
5720 +/* TNETD73XX chip definations */
5721 +
5722 +#define FREQ_1MHZ 1000000
5723 +#define TNETD73XX_MIPS_FREQ tnetd73xx_mips_freq /* CPU clock frequency */
5724 +#define TNETD73XX_VBUS_FREQ tnetd73xx_vbus_freq /* originally (TNETD73XX_MIPS_FREQ/2) */
5725 +
5726 +#ifdef AR7SEAD2
5727 +#define TNETD73XX_MIPS_FREQ_DEFAULT 25000000 /* 25 Mhz for sead2 board crystal */
5728 +#else
5729 +#define TNETD73XX_MIPS_FREQ_DEFAULT 125000000 /* 125 Mhz */
5730 +#endif
5731 +#define TNETD73XX_VBUS_FREQ_DEFAULT (TNETD73XX_MIPS_FREQ_DEFAULT / 2) /* Sync mode */
5732 +
5733 +
5734 +
5735 +/* Module base addresses */
5736 +#define TNETD73XX_ADSLSS_BASE PHYS_TO_K1(0x01000000) /* ADSLSS Module */
5737 +#define TNETD73XX_BBIF_CTRL_BASE PHYS_TO_K1(0x02000000) /* BBIF Control */
5738 +#define TNETD73XX_ATMSAR_BASE PHYS_TO_K1(0x03000000) /* ATM SAR */
5739 +#define TNETD73XX_USB_BASE PHYS_TO_K1(0x03400000) /* USB Module */
5740 +#define TNETD73XX_VLYNQ0_BASE PHYS_TO_K1(0x04000000) /* VLYNQ0 Module */
5741 +#define TNETD73xx_EMAC0_BASE PHYS_TO_K1(0x08610000) /* EMAC0 Module*/
5742 +#define TNETD73XX_EMIF_BASE PHYS_TO_K1(0x08610800) /* EMIF Module */
5743 +#define TNETD73XX_GPIO_BASE PHYS_TO_K1(0x08610900) /* GPIO control */
5744 +#define TNETD73XX_CLOCK_CTRL_BASE PHYS_TO_K1(0x08610A00) /* Clock Control */
5745 +#define TNETD73XX_WDTIMER_BASE PHYS_TO_K1(0x08610B00) /* WDTIMER Module */
5746 +#define TNETD73XX_TIMER0_BASE PHYS_TO_K1(0x08610C00) /* TIMER0 Module */
5747 +#define TNETD73XX_TIMER1_BASE PHYS_TO_K1(0x08610D00) /* TIMER1 Module */
5748 +#define TNETD73XX_UARTA_BASE PHYS_TO_K1(0x08610E00) /* UART A */
5749 +#define TNETD73XX_UARTB_BASE PHYS_TO_K1(0x08610F00) /* UART B */
5750 +#define TNETD73XX_I2C_BASE PHYS_TO_K1(0x08611000) /* I2C Module */
5751 +#define TNETD73XX_USB_DMA_BASE PHYS_TO_K1(0x08611200) /* USB Module */
5752 +#define TNETD73XX_MCDMA_BASE PHYS_TO_K1(0x08611400) /* MC-DMA */
5753 +#define TNETD73xx_VDMAVT_BASE PHYS_TO_K1(0x08611500) /* VDMAVT Control */
5754 +#define TNETD73XX_RST_CTRL_BASE PHYS_TO_K1(0x08611600) /* Reset Control */
5755 +#define TNETD73xx_BIST_CTRL_BASE PHYS_TO_K1(0x08611700) /* BIST Control */
5756 +#define TNETD73xx_VLYNQ0_CTRL_BASE PHYS_TO_K1(0x08611800) /* VLYNQ0 Control */
5757 +#define TNETD73XX_DCL_BASE PHYS_TO_K1(0x08611A00) /* Device Configuration Latch */
5758 +#define TNETD73xx_VLYNQ1_CTRL_BASE PHYS_TO_K1(0x08611C00) /* VLYNQ1 Control */
5759 +#define TNETD73xx_MDIO_BASE PHYS_TO_K1(0x08611E00) /* MDIO Control */
5760 +#define TNETD73XX_FSER_BASE PHYS_TO_K1(0x08612000) /* FSER Control */
5761 +#define TNETD73XX_INTC_BASE PHYS_TO_K1(0x08612400) /* Interrupt Controller */
5762 +#define TNETD73xx_EMAC1_BASE PHYS_TO_K1(0x08612800) /* EMAC1 Module*/
5763 +#define TNETD73XX_VLYNQ1_BASE PHYS_TO_K1(0x0C000000) /* VLYNQ1 Module */
5764 +
5765 +/* BBIF Registers */
5766 +#define TNETD73XX_BBIF_ADSLADR (TNETD73XX_BBIF_CTRL_BASE + 0x0)
5767 +
5768 +/* Device Configuration Latch Registers */
5769 +#define TNETD73XX_DCL_BOOTCR (TNETD73XX_DCL_BASE + 0x0)
5770 +#define TNETD73XX_DCL_DPLLSELR (TNETD73XX_DCL_BASE + 0x10)
5771 +#define TNETD73XX_DCL_SPEEDCTLR (TNETD73XX_DCL_BASE + 0x14)
5772 +#define TNETD73XX_DCL_SPEEDPWDR (TNETD73XX_DCL_BASE + 0x18)
5773 +#define TNETD73XX_DCL_SPEEDCAPR (TNETD73XX_DCL_BASE + 0x1C)
5774 +
5775 +/* GPIO Control */
5776 +#define TNETD73XX_GPIODINR (TNETD73XX_GPIO_BASE + 0x0)
5777 +#define TNETD73XX_GPIODOUTR (TNETD73XX_GPIO_BASE + 0x4)
5778 +#define TNETD73XX_GPIOPDIRR (TNETD73XX_GPIO_BASE + 0x8)
5779 +#define TNETD73XX_GPIOENR (TNETD73XX_GPIO_BASE + 0xC)
5780 +#define TNETD73XX_CVR (TNETD73XX_GPIO_BASE + 0x14)
5781 +#define TNETD73XX_DIDR1 (TNETD73XX_GPIO_BASE + 0x18)
5782 +#define TNETD73XX_DIDR2 (TNETD73XX_GPIO_BASE + 0x1C)
5783 +
5784 +/* Reset Control */
5785 +#define TNETD73XX_RST_CTRL_PRCR (TNETD73XX_RST_CTRL_BASE + 0x0)
5786 +#define TNETD73XX_RST_CTRL_SWRCR (TNETD73XX_RST_CTRL_BASE + 0x4)
5787 +#define TNETD73XX_RST_CTRL_RSR (TNETD73XX_RST_CTRL_BASE + 0x8)
5788 +
5789 +/* Power Control */
5790 +#define TNETD73XX_POWER_CTRL_PDCR (TNETD73XX_CLOCK_CTRL_BASE + 0x0)
5791 +#define TNETD73XX_POWER_CTRL_PCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x4)
5792 +#define TNETD73XX_POWER_CTRL_PDUCR (TNETD73XX_CLOCK_CTRL_BASE + 0x8)
5793 +#define TNETD73XX_POWER_CTRL_WKCR (TNETD73XX_CLOCK_CTRL_BASE + 0xC)
5794 +
5795 +/* Clock Control */
5796 +#define TNETD73XX_CLK_CTRL_SCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x20)
5797 +#define TNETD73XX_CLK_CTRL_SCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x30)
5798 +#define TNETD73XX_CLK_CTRL_MCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x40)
5799 +#define TNETD73XX_CLK_CTRL_MCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x50)
5800 +#define TNETD73XX_CLK_CTRL_UCLKCR (TNETD73XX_CLOCK_CTRL_BASE + 0x60)
5801 +#define TNETD73XX_CLK_CTRL_UCLKPLLCR (TNETD73XX_CLOCK_CTRL_BASE + 0x70)
5802 +#define TNETD73XX_CLK_CTRL_ACLKCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x80)
5803 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR0 (TNETD73XX_CLOCK_CTRL_BASE + 0x90)
5804 +#define TNETD73XX_CLK_CTRL_ACLKCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xA0)
5805 +#define TNETD73XX_CLK_CTRL_ACLKPLLCR1 (TNETD73XX_CLOCK_CTRL_BASE + 0xB0)
5806 +
5807 +/* EMIF control */
5808 +#define TNETD73XX_EMIF_SDRAM_CFG ( TNETD73XX_EMIF_BASE + 0x08 )
5809 +
5810 +/* UART */
5811 +#ifdef AR7SEAD2
5812 +#define TNETD73XX_UART_FREQ 3686400
5813 +#else
5814 +#define TNETD73XX_UART_FREQ TNETD73XX_VBUS_FREQ
5815 +#endif
5816 +
5817 +/* Interrupt Controller */
5818 +
5819 +/* Primary interrupts */
5820 +#define TNETD73XX_INTC_UNIFIED_SECONDARY 0 /* Unified secondary interrupt */
5821 +#define TNETD73XX_INTC_EXTERNAL0 1 /* External Interrupt Line 0 */
5822 +#define TNETD73XX_INTC_EXTERNAL1 2 /* External Interrupt Line 1 */
5823 +#define TNETD73XX_INTC_RESERVED3 3 /* Reserved */
5824 +#define TNETD73XX_INTC_RESERVED4 4 /* Reserved */
5825 +#define TNETD73XX_INTC_TIMER0 5 /* TIMER 0 int */
5826 +#define TNETD73XX_INTC_TIMER1 6 /* TIMER 1 int */
5827 +#define TNETD73XX_INTC_UART0 7 /* UART 0 int */
5828 +#define TNETD73XX_INTC_UART1 8 /* UART 1 int */
5829 +#define TNETD73XX_INTC_MCDMA0 9 /* MCDMA 0 int */
5830 +#define TNETD73XX_INTC_MCDMA1 10 /* MCDMA 1 int */
5831 +#define TNETD73XX_INTC_RESERVED11 11 /* Reserved */
5832 +#define TNETD73XX_INTC_RESERVED12 12 /* Reserved */
5833 +#define TNETD73XX_INTC_RESERVED13 13 /* Reserved */
5834 +#define TNETD73XX_INTC_RESERVED14 14 /* Reserved */
5835 +#define TNETD73XX_INTC_ATMSAR 15 /* ATM SAR int */
5836 +#define TNETD73XX_INTC_RESERVED16 16 /* Reserved */
5837 +#define TNETD73XX_INTC_RESERVED17 17 /* Reserved */
5838 +#define TNETD73XX_INTC_RESERVED18 18 /* Reserved */
5839 +#define TNETD73XX_INTC_EMAC0 19 /* EMAC 0 int */
5840 +#define TNETD73XX_INTC_RESERVED20 20 /* Reserved */
5841 +#define TNETD73XX_INTC_VLYNQ0 21 /* VLYNQ 0 int */
5842 +#define TNETD73XX_INTC_CODEC 22 /* CODEC int */
5843 +#define TNETD73XX_INTC_RESERVED23 23 /* Reserved */
5844 +#define TNETD73XX_INTC_USBSLAVE 24 /* USB Slave int */
5845 +#define TNETD73XX_INTC_VLYNQ1 25 /* VLYNQ 1 int */
5846 +#define TNETD73XX_INTC_RESERVED26 26 /* Reserved */
5847 +#define TNETD73XX_INTC_RESERVED27 27 /* Reserved */
5848 +#define TNETD73XX_INTC_ETH_PHY 28 /* Ethernet PHY */
5849 +#define TNETD73XX_INTC_I2C 29 /* I2C int */
5850 +#define TNETD73XX_INTC_MCDMA2 30 /* MCDMA 2 int */
5851 +#define TNETD73XX_INTC_MCDMA3 31 /* MCDMA 3 int */
5852 +#define TNETD73XX_INTC_RESERVED32 32 /* Reserved */
5853 +#define TNETD73XX_INTC_EMAC1 33 /* EMAC 1 int */
5854 +#define TNETD73XX_INTC_RESERVED34 34 /* Reserved */
5855 +#define TNETD73XX_INTC_RESERVED35 35 /* Reserved */
5856 +#define TNETD73XX_INTC_RESERVED36 36 /* Reserved */
5857 +#define TNETD73XX_INTC_VDMAVTRX 37 /* VDMAVTRX */
5858 +#define TNETD73XX_INTC_VDMAVTTX 38 /* VDMAVTTX */
5859 +#define TNETD73XX_INTC_ADSLSS 39 /* ADSLSS */
5860 +
5861 +/* Secondary interrupts */
5862 +#define TNETD73XX_INTC_SEC0 40 /* Secondary */
5863 +#define TNETD73XX_INTC_SEC1 41 /* Secondary */
5864 +#define TNETD73XX_INTC_SEC2 42 /* Secondary */
5865 +#define TNETD73XX_INTC_SEC3 43 /* Secondary */
5866 +#define TNETD73XX_INTC_SEC4 44 /* Secondary */
5867 +#define TNETD73XX_INTC_SEC5 45 /* Secondary */
5868 +#define TNETD73XX_INTC_SEC6 46 /* Secondary */
5869 +#define TNETD73XX_INTC_EMIF 47 /* EMIF */
5870 +#define TNETD73XX_INTC_SEC8 48 /* Secondary */
5871 +#define TNETD73XX_INTC_SEC9 49 /* Secondary */
5872 +#define TNETD73XX_INTC_SEC10 50 /* Secondary */
5873 +#define TNETD73XX_INTC_SEC11 51 /* Secondary */
5874 +#define TNETD73XX_INTC_SEC12 52 /* Secondary */
5875 +#define TNETD73XX_INTC_SEC13 53 /* Secondary */
5876 +#define TNETD73XX_INTC_SEC14 54 /* Secondary */
5877 +#define TNETD73XX_INTC_SEC15 55 /* Secondary */
5878 +#define TNETD73XX_INTC_SEC16 56 /* Secondary */
5879 +#define TNETD73XX_INTC_SEC17 57 /* Secondary */
5880 +#define TNETD73XX_INTC_SEC18 58 /* Secondary */
5881 +#define TNETD73XX_INTC_SEC19 59 /* Secondary */
5882 +#define TNETD73XX_INTC_SEC20 60 /* Secondary */
5883 +#define TNETD73XX_INTC_SEC21 61 /* Secondary */
5884 +#define TNETD73XX_INTC_SEC22 62 /* Secondary */
5885 +#define TNETD73XX_INTC_SEC23 63 /* Secondary */
5886 +#define TNETD73XX_INTC_SEC24 64 /* Secondary */
5887 +#define TNETD73XX_INTC_SEC25 65 /* Secondary */
5888 +#define TNETD73XX_INTC_SEC26 66 /* Secondary */
5889 +#define TNETD73XX_INTC_SEC27 67 /* Secondary */
5890 +#define TNETD73XX_INTC_SEC28 68 /* Secondary */
5891 +#define TNETD73XX_INTC_SEC29 69 /* Secondary */
5892 +#define TNETD73XX_INTC_SEC30 70 /* Secondary */
5893 +#define TNETD73XX_INTC_SEC31 71 /* Secondary */
5894 +
5895 +/* These ugly macros are to access the -1 registers, like config1 */
5896 +#define MFC0_SEL1_OPCODE(dst, src)\
5897 + .word (0x40000000 | ((dst)<<16) | ((src)<<11) | 1);\
5898 + nop; \
5899 + nop; \
5900 + nop
5901 +
5902 +#define MTC0_SEL1_OPCODE(dst, src)\
5903 + .word (0x40800000 | ((dst)<<16) | ((src)<<11) | 1);\
5904 + nop; \
5905 + nop; \
5906 + nop
5907 +
5908 +
5909 +/* Below are Jade core specific */
5910 +#define CFG0_4K_IL_MASK 0x00380000
5911 +#define CFG0_4K_IL_SHIFT 19
5912 +#define CFG0_4K_IA_MASK 0x00070000
5913 +#define CFG0_4K_IA_SHIFT 16
5914 +#define CFG0_4K_IS_MASK 0x01c00000
5915 +#define CFG0_4K_IS_SHIFT 22
5916 +
5917 +#define CFG0_4K_DL_MASK 0x00001c00
5918 +#define CFG0_4K_DL_SHIFT 10
5919 +#define CFG0_4K_DA_MASK 0x00000380
5920 +#define CFG0_4K_DA_SHIFT 7
5921 +#define CFG0_4K_DS_MASK 0x0000E000
5922 +#define CFG0_4K_DS_SHIFT 13
5923 +
5924 +
5925 +
5926 +#endif /* __TNETD73XX_H_ */
5927 diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h
5928 --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100
5929 +++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-09 08:00:15.306023000 +0200
5930 @@ -0,0 +1,243 @@
5931 +/******************************************************************************
5932 + * FILE PURPOSE: TNETD73xx Misc modules API Header
5933 + ******************************************************************************
5934 + * FILE NAME: tnetd73xx_misc.h
5935 + *
5936 + * DESCRIPTION: Clock Control, Reset Control, Power Management, GPIO
5937 + * FSER Modules API
5938 + * As per TNETD73xx specifications
5939 + *
5940 + * REVISION HISTORY:
5941 + * 27 Nov 02 - Sharath Kumar PSP TII
5942 + * 14 Feb 03 - Anant Gole PSP TII
5943 + *
5944 + * (C) Copyright 2002, Texas Instruments, Inc
5945 + *******************************************************************************/
5946 +
5947 +#ifndef __TNETD73XX_MISC_H__
5948 +#define __TNETD73XX_MISC_H__
5949 +
5950 +#include <linux/types.h>
5951 +
5952 +#define BOOTCR_MIPS_ASYNC_MODE (1 << 25)
5953 +
5954 +/*****************************************************************************
5955 + * Reset Control Module
5956 + *****************************************************************************/
5957 +
5958 +typedef enum TNETD73XX_RESET_MODULE_tag
5959 +{
5960 + RESET_MODULE_UART0 = 0,
5961 + RESET_MODULE_UART1 = 1,
5962 + RESET_MODULE_I2C = 2,
5963 + RESET_MODULE_TIMER0 = 3,
5964 + RESET_MODULE_TIMER1 = 4,
5965 + RESET_MODULE_GPIO = 6,
5966 + RESET_MODULE_ADSLSS = 7,
5967 + RESET_MODULE_USBS = 8,
5968 + RESET_MODULE_SAR = 9,
5969 + RESET_MODULE_VDMA_VT = 11,
5970 + RESET_MODULE_FSER = 12,
5971 + RESET_MODULE_VLYNQ1 = 16,
5972 + RESET_MODULE_EMAC0 = 17,
5973 + RESET_MODULE_DMA = 18,
5974 + RESET_MODULE_BIST = 19,
5975 + RESET_MODULE_VLYNQ0 = 20,
5976 + RESET_MODULE_EMAC1 = 21,
5977 + RESET_MODULE_MDIO = 22,
5978 + RESET_MODULE_ADSLSS_DSP = 23,
5979 + RESET_MODULE_EPHY = 26
5980 +} TNETD73XX_RESET_MODULE_T;
5981 +
5982 +typedef enum TNETD73XX_RESET_CTRL_tag
5983 +{
5984 + IN_RESET = 0,
5985 + OUT_OF_RESET
5986 +} TNETD73XX_RESET_CTRL_T;
5987 +
5988 +typedef enum TNETD73XX_SYS_RST_MODE_tag
5989 +{
5990 + RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */
5991 + RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */
5992 +} TNETD73XX_SYS_RST_MODE_T;
5993 +
5994 +typedef enum TNETD73XX_SYS_RESET_STATUS_tag
5995 +{
5996 + HARDWARE_RESET = 0,
5997 + SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */
5998 + WATCHDOG_RESET,
5999 + SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */
6000 +} TNETD73XX_SYS_RESET_STATUS_T;
6001 +
6002 +void tnetd73xx_reset_ctrl(TNETD73XX_RESET_MODULE_T reset_module,
6003 + TNETD73XX_RESET_CTRL_T reset_ctrl);
6004 +TNETD73XX_RESET_CTRL_T tnetd73xx_get_reset_status(TNETD73XX_RESET_MODULE_T reset_module);
6005 +void tnetd73xx_sys_reset(TNETD73XX_SYS_RST_MODE_T mode);
6006 +TNETD73XX_SYS_RESET_STATUS_T tnetd73xx_get_sys_last_reset_status(void);
6007 +
6008 +/*****************************************************************************
6009 + * Power Control Module
6010 + *****************************************************************************/
6011 +
6012 +typedef enum TNETD73XX_POWER_MODULE_tag
6013 +{
6014 + POWER_MODULE_USBSP = 0,
6015 + POWER_MODULE_WDTP = 1,
6016 + POWER_MODULE_UT0P = 2,
6017 + POWER_MODULE_UT1P = 3,
6018 + POWER_MODULE_IICP = 4,
6019 + POWER_MODULE_VDMAP = 5,
6020 + POWER_MODULE_GPIOP = 6,
6021 + POWER_MODULE_VLYNQ1P = 7,
6022 + POWER_MODULE_SARP = 8,
6023 + POWER_MODULE_ADSLP = 9,
6024 + POWER_MODULE_EMIFP = 10,
6025 + POWER_MODULE_ADSPP = 12,
6026 + POWER_MODULE_RAMP = 13,
6027 + POWER_MODULE_ROMP = 14,
6028 + POWER_MODULE_DMAP = 15,
6029 + POWER_MODULE_BISTP = 16,
6030 + POWER_MODULE_TIMER0P = 18,
6031 + POWER_MODULE_TIMER1P = 19,
6032 + POWER_MODULE_EMAC0P = 20,
6033 + POWER_MODULE_EMAC1P = 22,
6034 + POWER_MODULE_EPHYP = 24,
6035 + POWER_MODULE_VLYNQ0P = 27,
6036 +} TNETD73XX_POWER_MODULE_T;
6037 +
6038 +typedef enum TNETD73XX_POWER_CTRL_tag
6039 +{
6040 + POWER_CTRL_POWER_UP = 0,
6041 + POWER_CTRL_POWER_DOWN
6042 +} TNETD73XX_POWER_CTRL_T;
6043 +
6044 +typedef enum TNETD73XX_SYS_POWER_MODE_tag
6045 +{
6046 + GLOBAL_POWER_MODE_RUN = 0, /* All system is up */
6047 + GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */
6048 + GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */
6049 + GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */
6050 +} TNETD73XX_SYS_POWER_MODE_T;
6051 +
6052 +void tnetd73xx_power_ctrl(TNETD73XX_POWER_MODULE_T power_module, TNETD73XX_POWER_CTRL_T power_ctrl);
6053 +TNETD73XX_POWER_CTRL_T tnetd73xx_get_pwr_status(TNETD73XX_POWER_MODULE_T power_module);
6054 +void tnetd73xx_set_global_pwr_mode(TNETD73XX_SYS_POWER_MODE_T power_mode);
6055 +TNETD73XX_SYS_POWER_MODE_T tnetd73xx_get_global_pwr_mode(void);
6056 +
6057 +/*****************************************************************************
6058 + * Wakeup Control
6059 + *****************************************************************************/
6060 +
6061 +typedef enum TNETD73XX_WAKEUP_INTERRUPT_tag
6062 +{
6063 + WAKEUP_INT0 = 1,
6064 + WAKEUP_INT1 = 2,
6065 + WAKEUP_INT2 = 4,
6066 + WAKEUP_INT3 = 8
6067 +} TNETD73XX_WAKEUP_INTERRUPT_T;
6068 +
6069 +typedef enum TNETD73XX_WAKEUP_CTRL_tag
6070 +{
6071 + WAKEUP_DISABLED = 0,
6072 + WAKEUP_ENABLED
6073 +} TNETD73XX_WAKEUP_CTRL_T;
6074 +
6075 +typedef enum TNETD73XX_WAKEUP_POLARITY_tag
6076 +{
6077 + WAKEUP_ACTIVE_HIGH = 0,
6078 + WAKEUP_ACTIVE_LOW
6079 +} TNETD73XX_WAKEUP_POLARITY_T;
6080 +
6081 +void tnetd73xx_wakeup_ctrl(TNETD73XX_WAKEUP_INTERRUPT_T wakeup_int,
6082 + TNETD73XX_WAKEUP_CTRL_T wakeup_ctrl,
6083 + TNETD73XX_WAKEUP_POLARITY_T wakeup_polarity);
6084 +
6085 +/*****************************************************************************
6086 + * FSER Control
6087 + *****************************************************************************/
6088 +
6089 +typedef enum TNETD73XX_FSER_MODE_tag
6090 +{
6091 + FSER_I2C = 0,
6092 + FSER_UART = 1
6093 +} TNETD73XX_FSER_MODE_T;
6094 +
6095 +void tnetd73xx_fser_ctrl(TNETD73XX_FSER_MODE_T fser_mode);
6096 +
6097 +/*****************************************************************************
6098 + * Clock Control
6099 + *****************************************************************************/
6100 +
6101 +#define CLK_MHZ(x) ( (x) * 1000000 )
6102 +
6103 +typedef enum TNETD73XX_CLKC_ID_tag
6104 +{
6105 + CLKC_SYS = 0,
6106 + CLKC_MIPS,
6107 + CLKC_USB,
6108 + CLKC_ADSLSS
6109 +} TNETD73XX_CLKC_ID_T;
6110 +
6111 +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in);
6112 +TNETD73XX_ERR tnetd73xx_clkc_set_freq(TNETD73XX_CLKC_ID_T clk_id, u32 output_freq);
6113 +u32 tnetd73xx_clkc_get_freq(TNETD73XX_CLKC_ID_T clk_id);
6114 +
6115 +/*****************************************************************************
6116 + * GPIO Control
6117 + *****************************************************************************/
6118 +
6119 +typedef enum TNETD73XX_GPIO_PIN_tag
6120 +{
6121 + GPIO_UART0_RD = 0,
6122 + GPIO_UART0_TD = 1,
6123 + GPIO_UART0_RTS = 2,
6124 + GPIO_UART0_CTS = 3,
6125 + GPIO_FSER_CLK = 4,
6126 + GPIO_FSER_D = 5,
6127 + GPIO_EXT_AFE_SCLK = 6,
6128 + GPIO_EXT_AFE_TX_FS = 7,
6129 + GPIO_EXT_AFE_TXD = 8,
6130 + GPIO_EXT_AFE_RS_FS = 9,
6131 + GPIO_EXT_AFE_RXD1 = 10,
6132 + GPIO_EXT_AFE_RXD0 = 11,
6133 + GPIO_EXT_AFE_CDIN = 12,
6134 + GPIO_EXT_AFE_CDOUT = 13,
6135 + GPIO_EPHY_SPEED100 = 14,
6136 + GPIO_EPHY_LINKON = 15,
6137 + GPIO_EPHY_ACTIVITY = 16,
6138 + GPIO_EPHY_FDUPLEX = 17,
6139 + GPIO_EINT0 = 18,
6140 + GPIO_EINT1 = 19,
6141 + GPIO_MBSP0_TCLK = 20,
6142 + GPIO_MBSP0_RCLK = 21,
6143 + GPIO_MBSP0_RD = 22,
6144 + GPIO_MBSP0_TD = 23,
6145 + GPIO_MBSP0_RFS = 24,
6146 + GPIO_MBSP0_TFS = 25,
6147 + GPIO_MII_DIO = 26,
6148 + GPIO_MII_DCLK = 27,
6149 +} TNETD73XX_GPIO_PIN_T;
6150 +
6151 +typedef enum TNETD73XX_GPIO_PIN_MODE_tag
6152 +{
6153 + FUNCTIONAL_PIN = 0,
6154 + GPIO_PIN = 1
6155 +} TNETD73XX_GPIO_PIN_MODE_T;
6156 +
6157 +typedef enum TNETD73XX_GPIO_PIN_DIRECTION_tag
6158 +{
6159 + GPIO_OUTPUT_PIN = 0,
6160 + GPIO_INPUT_PIN = 1
6161 +} TNETD73XX_GPIO_PIN_DIRECTION_T;
6162 +
6163 +void tnetd73xx_gpio_init(void);
6164 +void tnetd73xx_gpio_ctrl(TNETD73XX_GPIO_PIN_T gpio_pin,
6165 + TNETD73XX_GPIO_PIN_MODE_T pin_mode,
6166 + TNETD73XX_GPIO_PIN_DIRECTION_T pin_direction);
6167 +void tnetd73xx_gpio_out(TNETD73XX_GPIO_PIN_T gpio_pin, int value);
6168 +int tnetd73xx_gpio_in(TNETD73XX_GPIO_PIN_T gpio_pin);
6169 +
6170 +/* TNETD73XX Revision */
6171 +u32 tnetd73xx_get_revision(void);
6172 +
6173 +#endif /* __TNETD73XX_MISC_H__ */
6174 diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h
6175 --- linux.old/include/asm-mips/io.h 2005-07-09 08:01:49.846651440 +0200
6176 +++ linux.dev/include/asm-mips/io.h 2005-07-09 08:00:15.307023000 +0200
6177 @@ -63,8 +63,12 @@
6178 #ifdef CONFIG_64BIT_PHYS_ADDR
6179 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
6180 #else
6181 +#ifdef CONFIG_AR7_PAGING
6182 +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + CONFIG_AR7_MEMORY)
6183 +#else
6184 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
6185 #endif
6186 +#endif
6187
6188 #define IO_SPACE_LIMIT 0xffff
6189
6190 diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h
6191 --- linux.old/include/asm-mips/irq.h 2005-07-09 08:01:49.847651288 +0200
6192 +++ linux.dev/include/asm-mips/irq.h 2005-07-09 08:00:15.307023000 +0200
6193 @@ -14,7 +14,12 @@
6194 #include <linux/config.h>
6195 #include <linux/linkage.h>
6196
6197 +#ifdef CONFIG_AR7
6198 +#include <asm/ar7/avalanche_intc.h>
6199 +#define NR_IRQS AVALANCHE_INT_END + 1
6200 +#else
6201 #define NR_IRQS 128 /* Largest number of ints of all machines. */
6202 +#endif
6203
6204 #ifdef CONFIG_I8259
6205 static inline int irq_cannonicalize(int irq)
6206 diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h
6207 --- linux.old/include/asm-mips/page.h 2005-07-09 08:01:49.847651288 +0200
6208 +++ linux.dev/include/asm-mips/page.h 2005-07-09 08:00:15.308023000 +0200
6209 @@ -129,7 +129,11 @@
6210
6211 #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
6212 #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
6213 +#ifdef CONFIG_AR7_PAGING
6214 +#define virt_to_page(kaddr) phys_to_page(__pa(kaddr))
6215 +#else
6216 #define virt_to_page(kaddr) (mem_map + (__pa(kaddr) >> PAGE_SHIFT))
6217 +#endif
6218 #define VALID_PAGE(page) ((page - mem_map) < max_mapnr)
6219
6220 #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
6221 diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h
6222 --- linux.old/include/asm-mips/pgtable-32.h 2005-07-09 08:01:49.847651288 +0200
6223 +++ linux.dev/include/asm-mips/pgtable-32.h 2005-07-09 08:00:15.308023000 +0200
6224 @@ -108,7 +108,18 @@
6225 * and a page entry and page directory to the page they refer to.
6226 */
6227
6228 -#ifdef CONFIG_CPU_VR41XX
6229 +#if defined(CONFIG_AR7_PAGING)
6230 +#define mk_pte(page, pgprot) \
6231 +({ \
6232 + pte_t __pte; \
6233 + \
6234 + pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT) | \
6235 + CONFIG_AR7_MEMORY) | \
6236 + pgprot_val(pgprot); \
6237 + \
6238 + __pte; \
6239 +})
6240 +#elif defined(CONFIG_CPU_VR41XX)
6241 #define mk_pte(page, pgprot) \
6242 ({ \
6243 pte_t __pte; \
6244 @@ -130,6 +141,7 @@
6245 })
6246 #endif
6247
6248 +
6249 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
6250 {
6251 #ifdef CONFIG_CPU_VR41XX
6252 @@ -175,7 +187,10 @@
6253 set_pte(ptep, __pte(0));
6254 }
6255
6256 -#ifdef CONFIG_CPU_VR41XX
6257 +#if defined(CONFIG_AR7_PAGING)
6258 +#define phys_to_page(phys) (mem_map + (((phys)-CONFIG_AR7_MEMORY) >> PAGE_SHIFT))
6259 +#define pte_page(x) phys_to_page(pte_val(x))
6260 +#elif defined(CONFIG_CPU_VR41XX)
6261 #define pte_page(x) (mem_map+((unsigned long)(((x).pte_low >> (PAGE_SHIFT+2)))))
6262 #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot))
6263 #else
6264 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
6265 --- linux.old/include/asm-mips/serial.h 2005-07-09 08:01:49.848651136 +0200
6266 +++ linux.dev/include/asm-mips/serial.h 2005-07-09 08:00:15.308023000 +0200
6267 @@ -65,6 +65,15 @@
6268
6269 #define C_P(card,port) (((card)<<6|(port)<<3) + 1)
6270
6271 +#ifdef CONFIG_AR7
6272 +#include <asm/ar7/ar7.h>
6273 +#define AR7_SERIAL_PORT_DEFNS \
6274 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART0_REGS_BASE, LNXINTNUM(AVALANCHE_UART0_INT), STD_COM_FLAGS }, \
6275 + { 0, AVALANCHE_BASE_BAUD, AVALANCHE_UART1_REGS_BASE, LNXINTNUM(AVALANCHE_UART1_INT), STD_COM_FLAGS },
6276 +#else
6277 +#define AR7_SERIAL_PORT_DEFNS
6278 +#endif
6279 +
6280 #ifdef CONFIG_MIPS_JAZZ
6281 #define _JAZZ_SERIAL_INIT(int, base) \
6282 { .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
6283 @@ -468,6 +477,7 @@
6284 #endif
6285
6286 #define SERIAL_PORT_DFNS \
6287 + AR7_SERIAL_PORT_DEFNS \
6288 ATLAS_SERIAL_PORT_DEFNS \
6289 AU1000_SERIAL_PORT_DEFNS \
6290 COBALT_SERIAL_PORT_DEFNS \
6291 diff -urN linux.old/Makefile linux.dev/Makefile
6292 --- linux.old/Makefile 2005-07-09 08:01:49.848651136 +0200
6293 +++ linux.dev/Makefile 2005-07-09 08:00:15.404008000 +0200
6294 @@ -91,7 +91,7 @@
6295
6296 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
6297
6298 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
6299 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
6300 -fno-strict-aliasing -fno-common
6301 ifndef CONFIG_FRAME_POINTER
6302 CFLAGS += -fomit-frame-pointer
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