4 #include <linux/hw_random.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
9 #include <linux/netdevice.h>
10 #include <linux/pci.h>
11 #include <asm/atomic.h>
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_driver_chipcommon.h>
17 #include <linux/wireless.h>
18 #include <net/mac80211.h>
20 #include "bcm43xx_debugfs.h"
21 #include "bcm43xx_leds.h"
22 #include "bcm43xx_lo.h"
23 #include "bcm43xx_phy.h"
26 #define PFX KBUILD_MODNAME ": "
28 #define BCM43xx_IRQWAIT_MAX_RETRIES 50
30 #define BCM43xx_IO_SIZE 8192
32 #define BCM43xx_RX_MAX_SSI 60
35 #define BCM43xx_MMIO_DMA0_REASON 0x20
36 #define BCM43xx_MMIO_DMA0_IRQ_MASK 0x24
37 #define BCM43xx_MMIO_DMA1_REASON 0x28
38 #define BCM43xx_MMIO_DMA1_IRQ_MASK 0x2C
39 #define BCM43xx_MMIO_DMA2_REASON 0x30
40 #define BCM43xx_MMIO_DMA2_IRQ_MASK 0x34
41 #define BCM43xx_MMIO_DMA3_REASON 0x38
42 #define BCM43xx_MMIO_DMA3_IRQ_MASK 0x3C
43 #define BCM43xx_MMIO_DMA4_REASON 0x40
44 #define BCM43xx_MMIO_DMA4_IRQ_MASK 0x44
45 #define BCM43xx_MMIO_DMA5_REASON 0x48
46 #define BCM43xx_MMIO_DMA5_IRQ_MASK 0x4C
47 #define BCM43xx_MMIO_MACCTL 0x120
48 #define BCM43xx_MMIO_STATUS_BITFIELD 0x120//TODO replace all instances by MACCTL
49 #define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
50 #define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
51 #define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C
52 #define BCM43xx_MMIO_RAM_CONTROL 0x130
53 #define BCM43xx_MMIO_RAM_DATA 0x134
54 #define BCM43xx_MMIO_PS_STATUS 0x140
55 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
56 #define BCM43xx_MMIO_SHM_CONTROL 0x160
57 #define BCM43xx_MMIO_SHM_DATA 0x164
58 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
59 #define BCM43xx_MMIO_XMITSTAT_0 0x170
60 #define BCM43xx_MMIO_XMITSTAT_1 0x174
61 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
62 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
65 #define BCM43xx_MMIO_DMA32_BASE0 0x200
66 #define BCM43xx_MMIO_DMA32_BASE1 0x220
67 #define BCM43xx_MMIO_DMA32_BASE2 0x240
68 #define BCM43xx_MMIO_DMA32_BASE3 0x260
69 #define BCM43xx_MMIO_DMA32_BASE4 0x280
70 #define BCM43xx_MMIO_DMA32_BASE5 0x2A0
72 #define BCM43xx_MMIO_DMA64_BASE0 0x200
73 #define BCM43xx_MMIO_DMA64_BASE1 0x240
74 #define BCM43xx_MMIO_DMA64_BASE2 0x280
75 #define BCM43xx_MMIO_DMA64_BASE3 0x2C0
76 #define BCM43xx_MMIO_DMA64_BASE4 0x300
77 #define BCM43xx_MMIO_DMA64_BASE5 0x340
79 #define BCM43xx_MMIO_PIO1_BASE 0x300
80 #define BCM43xx_MMIO_PIO2_BASE 0x310
81 #define BCM43xx_MMIO_PIO3_BASE 0x320
82 #define BCM43xx_MMIO_PIO4_BASE 0x330
84 #define BCM43xx_MMIO_PHY_VER 0x3E0
85 #define BCM43xx_MMIO_PHY_RADIO 0x3E2
86 #define BCM43xx_MMIO_PHY0 0x3E6
87 #define BCM43xx_MMIO_ANTENNA 0x3E8
88 #define BCM43xx_MMIO_CHANNEL 0x3F0
89 #define BCM43xx_MMIO_CHANNEL_EXT 0x3F4
90 #define BCM43xx_MMIO_RADIO_CONTROL 0x3F6
91 #define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8
92 #define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA
93 #define BCM43xx_MMIO_PHY_CONTROL 0x3FC
94 #define BCM43xx_MMIO_PHY_DATA 0x3FE
95 #define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
96 #define BCM43xx_MMIO_MACFILTER_DATA 0x422
97 #define BCM43xx_MMIO_RCMTA_COUNT 0x43C
98 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
99 #define BCM43xx_MMIO_GPIO_CONTROL 0x49C
100 #define BCM43xx_MMIO_GPIO_MASK 0x49E
101 #define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */
102 #define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
103 #define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
104 #define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
105 #define BCM43xx_MMIO_RNG 0x65A
106 #define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
108 /* SPROM boardflags_lo values */
109 #define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
110 #define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
111 #define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
112 #define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
113 #define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
114 #define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
115 #define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
116 #define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */
117 #define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */
118 #define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
119 #define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
120 #define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
121 #define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
122 #define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
123 #define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
124 #define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
126 /* GPIO register offset, in both ChipCommon and PCI core. */
127 #define BCM43xx_GPIO_CONTROL 0x6c
131 BCM43xx_SHM_UCODE
, /* Microcode memory */
132 BCM43xx_SHM_SHARED
, /* Shared memory */
133 BCM43xx_SHM_SCRATCH
, /* Scratch memory */
134 BCM43xx_SHM_HW
, /* Internal hardware register */
135 BCM43xx_SHM_RCMTA
, /* Receive match transmitter address (rev >= 5 only) */
137 /* SHM Routing modifiers */
138 #define BCM43xx_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
139 #define BCM43xx_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
140 #define BCM43xx_SHM_AUTOINC_RW (BCM43xx_SHM_AUTOINC_R | \
141 BCM43xx_SHM_AUTOINC_W)
143 /* Misc SHM_SHARED offsets */
144 #define BCM43xx_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
145 #define BCM43xx_SHM_SH_PCTLWDPOS 0x0008
146 #define BCM43xx_SHM_SH_RXPADOFF 0x0034 /* RX Padding data offset (PIO only) */
147 #define BCM43xx_SHM_SH_PHYVER 0x0050 /* PHY version */
148 #define BCM43xx_SHM_SH_PHYTYPE 0x0052 /* PHY type */
149 #define BCM43xx_SHM_SH_ANTSWAP 0x005C /* Antenna swap threshold */
150 #define BCM43xx_SHM_SH_HOSTFLO 0x005E /* Hostflags for ucode options (low) */
151 #define BCM43xx_SHM_SH_HOSTFHI 0x0060 /* Hostflags for ucode options (high) */
152 #define BCM43xx_SHM_SH_RADAR 0x0066 /* Radar register */
153 #define BCM43xx_SHM_SH_PHYTXNOI 0x006E /* PHY noise directly after TX (lower 8bit only) */
154 #define BCM43xx_SHM_SH_RFRXSP1 0x0072 /* RF RX SP Register 1 */
155 #define BCM43xx_SHM_SH_CHAN 0x00A0 /* Current channel (low 8bit only) */
156 #define BCM43xx_SHM_SH_CHAN_5GHZ 0x0100 /* Bit set, if 5Ghz channel */
157 #define BCM43xx_SHM_SH_BCMCFIFOID 0x0108 /* Last posted cookie to the bcast/mcast FIFO */
158 /* SHM_SHARED TX FIFO variables */
159 #define BCM43xx_SHM_SH_SIZE01 0x0098 /* TX FIFO size for FIFO 0 (low) and 1 (high) */
160 #define BCM43xx_SHM_SH_SIZE23 0x009A /* TX FIFO size for FIFO 2 and 3 */
161 #define BCM43xx_SHM_SH_SIZE45 0x009C /* TX FIFO size for FIFO 4 and 5 */
162 #define BCM43xx_SHM_SH_SIZE67 0x009E /* TX FIFO size for FIFO 6 and 7 */
163 /* SHM_SHARED background noise */
164 #define BCM43xx_SHM_SH_JSSI0 0x0088 /* Measure JSSI 0 */
165 #define BCM43xx_SHM_SH_JSSI1 0x008A /* Measure JSSI 1 */
166 #define BCM43xx_SHM_SH_JSSIAUX 0x008C /* Measure JSSI AUX */
167 /* SHM_SHARED crypto engine */
168 #define BCM43xx_SHM_SH_DEFAULTIV 0x003C /* Default IV location */
169 #define BCM43xx_SHM_SH_NRRXTRANS 0x003E /* # of soft RX transmitter addresses (max 8) */
170 #define BCM43xx_SHM_SH_KTP 0x0056 /* Key table pointer */
171 #define BCM43xx_SHM_SH_TKIPTSCTTAK 0x0318
172 #define BCM43xx_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block (v4 firmware) */
173 #define BCM43xx_SHM_SH_PSM 0x05F4 /* PSM transmitter address match block (rev < 5) */
174 /* SHM_SHARED WME variables */
175 #define BCM43xx_SHM_SH_EDCFSTAT 0x000E /* EDCF status */
176 #define BCM43xx_SHM_SH_TXFCUR 0x0030 /* TXF current index */
177 #define BCM43xx_SHM_SH_EDCFQ 0x0240 /* EDCF Q info */
178 /* SHM_SHARED powersave mode related */
179 #define BCM43xx_SHM_SH_SLOTT 0x0010 /* Slot time */
180 #define BCM43xx_SHM_SH_DTIMPER 0x0012 /* DTIM period */
181 #define BCM43xx_SHM_SH_NOSLPZNATDTIM 0x004C /* NOSLPZNAT DTIM */
182 /* SHM_SHARED beacon variables */
183 #define BCM43xx_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
184 #define BCM43xx_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
185 #define BCM43xx_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
186 #define BCM43xx_SHM_SH_TIMBPOS 0x001E /* TIM B position in beacon */
187 #define BCM43xx_SHM_SH_SFFBLIM 0x0044 /* Short frame fallback retry limit */
188 #define BCM43xx_SHM_SH_LFFBLIM 0x0046 /* Long frame fallback retry limit */
189 #define BCM43xx_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word (see PHY TX control) */
190 /* SHM_SHARED ACK/CTS control */
191 #define BCM43xx_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word (see PHY TX control) */
192 /* SHM_SHARED probe response variables */
193 #define BCM43xx_SHM_SH_PRSSID 0x0160 /* Probe Response SSID */
194 #define BCM43xx_SHM_SH_PRSSIDLEN 0x0048 /* Probe Response SSID length */
195 #define BCM43xx_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
196 #define BCM43xx_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
197 #define BCM43xx_SHM_SH_PRPHYCTL 0x0188 /* Probe Response PHY TX control word */
198 /* SHM_SHARED rate tables */
199 #define BCM43xx_SHM_SH_OFDMDIRECT 0x01C0 /* Pointer to OFDM direct map */
200 #define BCM43xx_SHM_SH_OFDMBASIC 0x01E0 /* Pointer to OFDM basic rate map */
201 #define BCM43xx_SHM_SH_CCKDIRECT 0x0200 /* Pointer to CCK direct map */
202 #define BCM43xx_SHM_SH_CCKBASIC 0x0220 /* Pointer to CCK basic rate map */
203 /* SHM_SHARED microcode soft registers */
204 #define BCM43xx_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
205 #define BCM43xx_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
206 #define BCM43xx_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
207 #define BCM43xx_SHM_SH_UCODETIME 0x0006 /* Microcode time */
208 #define BCM43xx_SHM_SH_UCODESTAT 0x0040 /* Microcode debug status code */
209 #define BCM43xx_SHM_SH_UCODESTAT_INVALID 0
210 #define BCM43xx_SHM_SH_UCODESTAT_INIT 1
211 #define BCM43xx_SHM_SH_UCODESTAT_ACTIVE 2
212 #define BCM43xx_SHM_SH_UCODESTAT_SUSP 3 /* suspended */
213 #define BCM43xx_SHM_SH_UCODESTAT_SLEEP 4 /* asleep (PS) */
214 #define BCM43xx_SHM_SH_MAXBFRAMES 0x0080 /* Maximum number of frames in a burst */
215 #define BCM43xx_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
216 #define BCM43xx_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
218 /* SHM_SCRATCH offsets */
219 #define BCM43xx_SHM_SC_MINCONT 0x0003 /* Minimum contention window */
220 #define BCM43xx_SHM_SC_MAXCONT 0x0004 /* Maximum contention window */
221 #define BCM43xx_SHM_SC_CURCONT 0x0005 /* Current contention window */
222 #define BCM43xx_SHM_SC_SRLIMIT 0x0006 /* Short retry count limit */
223 #define BCM43xx_SHM_SC_LRLIMIT 0x0007 /* Long retry count limit */
224 #define BCM43xx_SHM_SC_DTIMC 0x0008 /* Current DTIM count */
225 #define BCM43xx_SHM_SC_BTL0LEN 0x0015 /* Beacon 0 template length */
226 #define BCM43xx_SHM_SC_BTL1LEN 0x0016 /* Beacon 1 template length */
227 #define BCM43xx_SHM_SC_SCFB 0x0017 /* Short frame transmit count threshold for rate fallback */
228 #define BCM43xx_SHM_SC_LCFB 0x0018 /* Long frame transmit count threshold for rate fallback */
231 /* Hardware Radio Enable masks */
232 #define BCM43xx_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
233 #define BCM43xx_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
235 /* HostFlags. See bcm43xx_hf_read/write() */
236 #define BCM43xx_HF_ANTDIVHELP 0x00000001 /* ucode antenna div helper */
237 #define BCM43xx_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
238 #define BCM43xx_HF_RXPULLW 0x00000004 /* RX pullup workaround */
239 #define BCM43xx_HF_CCKBOOST 0x00000008 /* 4dB CCK power boost (exclusive with OFDM boost) */
240 #define BCM43xx_HF_BTCOEX 0x00000010 /* Bluetooth coexistance */
241 #define BCM43xx_HF_GDCW 0x00000020 /* G-PHY DV canceller filter bw workaround */
242 #define BCM43xx_HF_OFDMPABOOST 0x00000040 /* Enable PA gain boost for OFDM */
243 #define BCM43xx_HF_ACPR 0x00000080 /* Disable for Japan, channel 14 */
244 #define BCM43xx_HF_EDCF 0x00000100 /* on if WME and MAC suspended */
245 #define BCM43xx_HF_TSSIRPSMW 0x00000200 /* TSSI reset PSM ucode workaround */
246 #define BCM43xx_HF_DSCRQ 0x00000400 /* Disable slow clock request in ucode */
247 #define BCM43xx_HF_ACIW 0x00000800 /* ACI workaround: shift bits by 2 on PHY CRS */
248 #define BCM43xx_HF_2060W 0x00001000 /* 2060 radio workaround */
249 #define BCM43xx_HF_RADARW 0x00002000 /* Radar workaround */
250 #define BCM43xx_HF_USEDEFKEYS 0x00004000 /* Enable use of default keys */
251 #define BCM43xx_HF_BT4PRIOCOEX 0x00010000 /* Bluetooth 2-priority coexistance */
252 #define BCM43xx_HF_FWKUP 0x00020000 /* Fast wake-up ucode */
253 #define BCM43xx_HF_VCORECALC 0x00040000 /* Force VCO recalculation when powering up synthpu */
254 #define BCM43xx_HF_PCISCW 0x00080000 /* PCI slow clock workaround */
255 #define BCM43xx_HF_4318TSSI 0x00200000 /* 4318 TSSI */
256 #define BCM43xx_HF_FBCMCFIFO 0x00400000 /* Flush bcast/mcast FIFO immediately */
257 #define BCM43xx_HF_HWPCTL 0x00800000 /* Enable hardwarre power control */
258 #define BCM43xx_HF_BTCOEXALT 0x01000000 /* Bluetooth coexistance in alternate pins */
259 #define BCM43xx_HF_TXBTCHECK 0x02000000 /* Bluetooth check during transmission */
260 #define BCM43xx_HF_SKCFPUP 0x04000000 /* Skip CFP update */
263 /* MacFilter offsets. */
264 #define BCM43xx_MACFILTER_SELF 0x0000
265 #define BCM43xx_MACFILTER_ASSOC 0x0003
268 #define BCM43xx_PCTL_IN 0xB0
269 #define BCM43xx_PCTL_OUT 0xB4
270 #define BCM43xx_PCTL_OUTENABLE 0xB8
271 #define BCM43xx_PCTL_XTAL_POWERUP 0x40
272 #define BCM43xx_PCTL_PLL_POWERDOWN 0x80
274 /* PowerControl Clock Modes */
275 #define BCM43xx_PCTL_CLK_FAST 0x00
276 #define BCM43xx_PCTL_CLK_SLOW 0x01
277 #define BCM43xx_PCTL_CLK_DYNAMIC 0x02
279 #define BCM43xx_PCTL_FORCE_SLOW 0x0800
280 #define BCM43xx_PCTL_FORCE_PLL 0x1000
281 #define BCM43xx_PCTL_DYN_XTAL 0x2000
284 #define BCM43xx_PHYTYPE_A 0x00
285 #define BCM43xx_PHYTYPE_B 0x01
286 #define BCM43xx_PHYTYPE_G 0x02
289 #define BCM43xx_PHY_ILT_A_CTRL 0x0072
290 #define BCM43xx_PHY_ILT_A_DATA1 0x0073
291 #define BCM43xx_PHY_ILT_A_DATA2 0x0074
292 #define BCM43xx_PHY_G_LO_CONTROL 0x0810
293 #define BCM43xx_PHY_ILT_G_CTRL 0x0472
294 #define BCM43xx_PHY_ILT_G_DATA1 0x0473
295 #define BCM43xx_PHY_ILT_G_DATA2 0x0474
296 #define BCM43xx_PHY_A_PCTL 0x007B
297 #define BCM43xx_PHY_G_PCTL 0x0029
298 #define BCM43xx_PHY_A_CRS 0x0029
299 #define BCM43xx_PHY_RADIO_BITFIELD 0x0401
300 #define BCM43xx_PHY_G_CRS 0x0429
301 #define BCM43xx_PHY_NRSSILT_CTRL 0x0803
302 #define BCM43xx_PHY_NRSSILT_DATA 0x0804
305 #define BCM43xx_RADIOCTL_ID 0x01
307 /* MAC Control bitfield */
308 #define BCM43xx_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
309 #define BCM43xx_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
310 #define BCM43xx_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
311 #define BCM43xx_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
312 #define BCM43xx_MACCTL_SHM_UPPER 0x00000200 /* SHM Upper */
313 #define BCM43xx_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
314 #define BCM43xx_MACCTL_PSM_DBG 0x00002000 /* Microcode debugging enabled */
315 #define BCM43xx_MACCTL_GPOUTSMSK 0x0000C000 /* GPOUT Select Mask */
316 #define BCM43xx_MACCTL_BE 0x00010000 /* Big Endian mode */
317 #define BCM43xx_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
318 #define BCM43xx_MACCTL_AP 0x00040000 /* AccessPoint mode */
319 #define BCM43xx_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
320 #define BCM43xx_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
321 #define BCM43xx_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
322 #define BCM43xx_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
323 #define BCM43xx_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
324 #define BCM43xx_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
325 #define BCM43xx_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
326 #define BCM43xx_MACCTL_AWAKE 0x04000000 /* Device is awake */
327 #define BCM43xx_MACCTL_CLOSEDNET 0x08000000 /* Closed net (no SSID bcast) */
328 #define BCM43xx_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
329 #define BCM43xx_MACCTL_DISCTXSTAT 0x20000000 /* Discard TX status */
330 #define BCM43xx_MACCTL_DISCPMQ 0x40000000 /* Discard Power Management Queue */
331 #define BCM43xx_MACCTL_GMODE 0x80000000 /* G Mode */
333 /* StatusBitField *///FIXME rename these all
334 #define BCM43xx_SBF_MAC_ENABLED 0x00000001
335 #define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/
336 #define BCM43xx_SBF_CORE_READY 0x00000004
337 #define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/
338 #define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/
339 #define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/
340 #define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
341 #define BCM43xx_SBF_MODE_NOTADHOC 0x00020000
342 #define BCM43xx_SBF_MODE_AP 0x00040000
343 #define BCM43xx_SBF_RADIOREG_LOCK 0x00080000
344 #define BCM43xx_SBF_MODE_MONITOR 0x00400000
345 #define BCM43xx_SBF_MODE_PROMISC 0x01000000
346 #define BCM43xx_SBF_PS1 0x02000000
347 #define BCM43xx_SBF_PS2 0x04000000
348 #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000
349 #define BCM43xx_SBF_TIME_UPDATE 0x10000000
350 #define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/
352 /* 802.11 core specific TM State Low flags */
353 #define BCM43xx_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
354 #define BCM43xx_TMSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select */
355 #define BCM43xx_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */
356 #define BCM43xx_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
357 #define BCM43xx_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
359 /* 802.11 core specific TM State High flags */
360 #define BCM43xx_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available (rev >= 5)*/
361 #define BCM43xx_TMSHIGH_APHY 0x00020000 /* A-PHY available (rev >= 5) */
362 #define BCM43xx_TMSHIGH_GPHY 0x00010000 /* G-PHY available (rev >= 5) */
364 /* Generic-Interrupt reasons. */
365 #define BCM43xx_IRQ_MAC_SUSPENDED 0x00000001
366 #define BCM43xx_IRQ_BEACON 0x00000002
367 #define BCM43xx_IRQ_TBTT_INDI 0x00000004
368 #define BCM43xx_IRQ_BEACON_TX_OK 0x00000008
369 #define BCM43xx_IRQ_BEACON_CANCEL 0x00000010
370 #define BCM43xx_IRQ_ATIM_END 0x00000020
371 #define BCM43xx_IRQ_PMQ 0x00000040
372 #define BCM43xx_IRQ_PIO_WORKAROUND 0x00000100
373 #define BCM43xx_IRQ_MAC_TXERR 0x00000200
374 #define BCM43xx_IRQ_PHY_TXERR 0x00000800
375 #define BCM43xx_IRQ_PMEVENT 0x00001000
376 #define BCM43xx_IRQ_TIMER0 0x00002000
377 #define BCM43xx_IRQ_TIMER1 0x00004000
378 #define BCM43xx_IRQ_DMA 0x00008000
379 #define BCM43xx_IRQ_TXFIFO_FLUSH_OK 0x00010000
380 #define BCM43xx_IRQ_CCA_MEASURE_OK 0x00020000
381 #define BCM43xx_IRQ_NOISESAMPLE_OK 0x00040000
382 #define BCM43xx_IRQ_UCODE_DEBUG 0x08000000
383 #define BCM43xx_IRQ_RFKILL 0x10000000
384 #define BCM43xx_IRQ_TX_OK 0x20000000
385 #define BCM43xx_IRQ_PHY_G_CHANGED 0x40000000
386 #define BCM43xx_IRQ_TIMEOUT 0x80000000
388 #define BCM43xx_IRQ_ALL 0xFFFFFFFF
389 #define BCM43xx_IRQ_MASKTEMPLATE (BCM43xx_IRQ_MAC_SUSPENDED | \
390 BCM43xx_IRQ_BEACON | \
391 BCM43xx_IRQ_TBTT_INDI | \
392 BCM43xx_IRQ_ATIM_END | \
394 BCM43xx_IRQ_MAC_TXERR | \
395 BCM43xx_IRQ_PHY_TXERR | \
397 BCM43xx_IRQ_TXFIFO_FLUSH_OK | \
398 BCM43xx_IRQ_NOISESAMPLE_OK | \
399 BCM43xx_IRQ_UCODE_DEBUG | \
400 BCM43xx_IRQ_RFKILL | \
403 /* Device specific rate values.
404 * The actual values defined here are (rate_in_mbps * 2).
405 * Some code depends on this. Don't change it. */
406 #define BCM43xx_CCK_RATE_1MB 0x02
407 #define BCM43xx_CCK_RATE_2MB 0x04
408 #define BCM43xx_CCK_RATE_5MB 0x0B
409 #define BCM43xx_CCK_RATE_11MB 0x16
410 #define BCM43xx_OFDM_RATE_6MB 0x0C
411 #define BCM43xx_OFDM_RATE_9MB 0x12
412 #define BCM43xx_OFDM_RATE_12MB 0x18
413 #define BCM43xx_OFDM_RATE_18MB 0x24
414 #define BCM43xx_OFDM_RATE_24MB 0x30
415 #define BCM43xx_OFDM_RATE_36MB 0x48
416 #define BCM43xx_OFDM_RATE_48MB 0x60
417 #define BCM43xx_OFDM_RATE_54MB 0x6C
418 /* Convert a bcm43xx rate value to a rate in 100kbps */
419 #define BCM43xx_RATE_TO_BASE100KBPS(rate) (((rate) * 10) / 2)
422 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
423 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
425 /* Max size of a security key */
426 #define BCM43xx_SEC_KEYSIZE 16
427 /* Security algorithms. */
429 BCM43xx_SEC_ALGO_NONE
= 0, /* unencrypted, as of TX header. */
430 BCM43xx_SEC_ALGO_WEP40
,
431 BCM43xx_SEC_ALGO_TKIP
,
432 BCM43xx_SEC_ALGO_AES
,
433 BCM43xx_SEC_ALGO_WEP104
,
434 BCM43xx_SEC_ALGO_AES_LEGACY
,
441 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
442 # define assert(expr) \
444 if (unlikely(!(expr))) { \
445 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \
446 #expr, __FILE__, __LINE__, __FUNCTION__); \
449 # define BCM43xx_DEBUG 1
451 # define assert(expr) do { /* nothing */ } while (0)
452 # define BCM43xx_DEBUG 0
455 /* rate limited printk(). */
459 #define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0)
460 /* rate limited printk() for debugging */
464 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
465 # define dprintkl printkl
467 # define dprintkl(f, x...) do { /* nothing */ } while (0)
470 /* debugging printk() */
474 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
475 # define dprintk(f, x...) do { printk(f ,##x); } while (0)
477 # define dprintk(f, x...) do { /* nothing */ } while (0)
483 struct bcm43xx_dmaring
;
484 struct bcm43xx_pioqueue
;
486 struct bcm43xx_initval
{
490 } __attribute__((__packed__
));
492 #define BCM43xx_PHYMODE(phytype) (1 << (phytype))
493 #define BCM43xx_PHYMODE_A BCM43xx_PHYMODE(BCM43xx_PHYTYPE_A)
494 #define BCM43xx_PHYMODE_B BCM43xx_PHYMODE(BCM43xx_PHYTYPE_B)
495 #define BCM43xx_PHYMODE_G BCM43xx_PHYMODE(BCM43xx_PHYTYPE_G)
498 /* Possible PHYMODEs on this PHY */
499 u8 possible_phymodes
;
500 /* GMODE bit enabled? */
502 /* Possible ieee80211 subsystem hwmodes for this PHY.
503 * Which mode is selected, depends on thr GMODE enabled bit */
504 #define BCM43xx_MAX_PHYHWMODES 2
505 struct ieee80211_hw_mode hwmodes
[BCM43xx_MAX_PHYHWMODES
];
509 /* BCM43xx_PHYTYPE_ */
511 /* PHY revision number. */
514 /* Radio versioning */
515 u16 radio_manuf
; /* Radio manufacturer */
516 u16 radio_ver
; /* Radio version */
517 u8 radio_rev
; /* Radio revision */
519 u8 radio_on
:1; /* Radio switched on/off */
520 u8 locked
:1; /* Only used in bcm43xx_phy_{un}lock() */
521 u8 dyn_tssi_tbl
:1; /* tssi2dbm is kmalloc()ed. */
523 /* ACI (adjacent channel interference) flags. */
525 u8 aci_wlan_automatic
:1;
531 /* TSSI to dBm table in use */
533 /* Target idle TSSI */
535 /* Current idle TSSI */
538 /* LocalOscillator control values. */
539 struct bcm43xx_txpower_lo_control
*lo_control
;
540 /* Values from bcm43xx_calc_loopback_gain() */
541 s16 max_lb_gain
; /* Maximum Loopback gain in hdB */
542 s16 trsw_rx_gain
; /* TRSW RX gain in hdB */
543 s16 lna_lod_gain
; /* LNA lod */
544 s16 lna_gain
; /* LNA */
545 s16 pga_gain
; /* PGA */
547 /* PHY lock for core.rev < 3
548 * This lock is only used by bcm43xx_phy_{un}lock()
552 /* Desired TX power level (in dBm).
553 * This is set by the user and adjusted in bcm43xx_phy_xmitpower(). */
555 /* TX Power control values. */
558 /* Current Radio Attenuation for TXpower recalculation. */
560 /* Current Baseband Attenuation for TXpower recalculation. */
562 /* Current TXpower control value for TXpower recalculation. */
570 /* Current Interference Mitigation mode */
572 /* Stack of saved values from the Interference Mitigation code.
573 * Each value in the stack is layed out as follows:
575 * bit 12-15: register ID
577 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
579 #define BCM43xx_INTERFSTACK_SIZE 26
580 u32 interfstack
[BCM43xx_INTERFSTACK_SIZE
];//FIXME: use a data structure
582 /* Saved values from the NRSSI Slope calculation */
585 /* In memory nrssi lookup table. */
588 /* current channel */
593 u16 initval
;//FIXME rename?
596 /* Data structures for DMA transmission, per 80211 core. */
598 struct bcm43xx_dmaring
*tx_ring0
;
599 struct bcm43xx_dmaring
*tx_ring1
;
600 struct bcm43xx_dmaring
*tx_ring2
;
601 struct bcm43xx_dmaring
*tx_ring3
;
602 struct bcm43xx_dmaring
*tx_ring4
;
603 struct bcm43xx_dmaring
*tx_ring5
;
605 struct bcm43xx_dmaring
*rx_ring0
;
606 struct bcm43xx_dmaring
*rx_ring3
; /* only available on core.rev < 5 */
609 /* Data structures for PIO transmission, per 80211 core. */
611 struct bcm43xx_pioqueue
*queue0
;
612 struct bcm43xx_pioqueue
*queue1
;
613 struct bcm43xx_pioqueue
*queue2
;
614 struct bcm43xx_pioqueue
*queue3
;
617 /* Context information for a noise calculation (Link Quality). */
618 struct bcm43xx_noise_calculation
{
620 u8 calculation_running
:1;
625 struct bcm43xx_stats
{
627 /* Store the last TX/RX times here for updating the leds. */
628 unsigned long last_tx
;
629 unsigned long last_rx
;
638 struct bcm43xx_wldev
;
640 /* Data structure for the WLAN parts (802.11 cores) of the bcm43xx chip. */
642 /* Pointer to the active wireless device on this chip */
643 struct bcm43xx_wldev
*current_dev
;
644 /* Pointer to the ieee80211 hardware data structure */
645 struct ieee80211_hw
*hw
;
649 spinlock_t leds_lock
;
651 /* We can only have one operating interface (802.11 core)
652 * at a time. General information about this interface follows.
655 /* Opaque ID of the operating interface (!= monitor
656 * interface) from the ieee80211 subsystem.
662 /* Current BSSID (if any). */
664 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
666 /* Counter of active monitor interfaces. */
668 /* Is the card operating in AP, STA or IBSS mode? */
669 unsigned int operating
:1;
670 /* Promisc mode active?
671 * Note that (monitor != 0) implies promisc.
673 unsigned int promisc
:1;
674 /* Stats about the wireless interface */
675 struct ieee80211_low_level_stats ieee_stats
;
679 char rng_name
[30 + 1];
681 /* List of all wireless devices on this chip */
682 struct list_head devlist
;
686 /* Pointers to the firmware data and meta information about it. */
687 struct bcm43xx_firmware
{
689 const struct firmware
*ucode
;
691 const struct firmware
*pcm
;
692 /* Initial MMIO values 0 */
693 const struct firmware
*initvals0
;
694 /* Initial MMIO values 1 */
695 const struct firmware
*initvals1
;
696 /* Firmware revision */
698 /* Firmware patchlevel */
702 /* Device (802.11 core) initialization status. */
704 BCM43xx_STAT_UNINIT
, /* Uninitialized. */
705 BCM43xx_STAT_INITIALIZING
, /* bcm43xx_wireless_core_init() in progress. */
706 BCM43xx_STAT_INITIALIZED
, /* Initialized. Note that this doesn't mean it's started. */
708 #define bcm43xx_status(bcm) atomic_read(&(bcm)->init_status)
709 #define bcm43xx_set_status(bcm, stat) do { \
710 atomic_set(&(bcm)->init_status, (stat)); \
714 /* XXX--- HOW LOCKING WORKS IN BCM43xx ---XXX
716 * You should always acquire both, wl->mutex and wl->irq_lock unless:
717 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
718 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
719 * and packet TX path (and _ONLY_ there.)
722 /* Data structure for one wireless device (802.11 core) */
723 struct bcm43xx_wldev
{
724 struct ssb_device
*dev
;
725 struct bcm43xx_wl
*wl
;
727 /* Driver initialization status BCM43xx_STAT_*** */
728 atomic_t init_status
;
729 /* Interface started? (bcm43xx_wireless_core_start()) */
732 u16 was_initialized
:1, /* for suspend/resume. */
733 was_started
:1, /* for suspend/resume. */
734 __using_pio
:1, /* Internal, use bcm43xx_using_pio(). */
735 bad_frames_preempt
:1, /* Use "Bad Frames Preemption" (default off) */
736 reg124_set_0x4
:1, /* Some variable to keep track of IRQ stuff. */
737 short_preamble
:1, /* TRUE, if short preamble is enabled. */
738 short_slot
:1, /* TRUE, if short slot timing is enabled. */
739 radio_hw_enable
:1; /* saved state of radio hardware enabled state */
741 /* PHY/Radio device. */
742 struct bcm43xx_phy phy
;
745 struct bcm43xx_dma dma
;
747 struct bcm43xx_pio pio
;
750 /* Various statistics about the physical device. */
751 struct bcm43xx_stats stats
;
753 #define BCM43xx_NR_LEDS 4
754 struct bcm43xx_led leds
[BCM43xx_NR_LEDS
];
756 /* Reason code of the last interrupt. */
759 /* saved irq enable/disable state bitfield. */
761 /* Link Quality calculation context. */
762 struct bcm43xx_noise_calculation noisecalc
;
763 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
766 /* Interrupt Service Routine tasklet (bottom-half) */
767 struct tasklet_struct isr_tasklet
;
770 struct delayed_work periodic_work
;
771 unsigned int periodic_state
;
773 struct work_struct restart_work
;
775 /* encryption/decryption */
776 u16 ktp
; /* Key table pointer */
778 struct bcm43xx_key key
[58];
780 /* Cached beacon template while uploading the template. */
781 struct sk_buff
*cached_beacon
;
784 struct bcm43xx_firmware fw
;
786 /* Devicelist in struct bcm43xx_wl (all 802.11 cores) */
787 struct list_head list
;
789 /* Debugging stuff follows. */
790 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
791 struct bcm43xx_dfsentry
*dfsentry
;
797 struct bcm43xx_wl
* hw_to_bcm43xx_wl(struct ieee80211_hw
*hw
)
802 /* Helper function, which returns a boolean.
803 * TRUE, if PIO is used; FALSE, if DMA is used.
805 #if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
807 int bcm43xx_using_pio(struct bcm43xx_wldev
*dev
)
809 return dev
->__using_pio
;
811 #elif defined(CONFIG_BCM43XX_MAC80211_DMA)
813 int bcm43xx_using_pio(struct bcm43xx_wldev
*dev
)
817 #elif defined(CONFIG_BCM43XX_MAC80211_PIO)
819 int bcm43xx_using_pio(struct bcm43xx_wldev
*dev
)
824 # error "Using neither DMA nor PIO? Confused..."
829 struct bcm43xx_wldev
* dev_to_bcm43xx_wldev(struct device
*dev
)
831 struct ssb_device
*ssb_dev
= dev_to_ssb_dev(dev
);
832 return ssb_get_drvdata(ssb_dev
);
835 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
837 int bcm43xx_is_mode(struct bcm43xx_wl
*wl
, int type
)
839 if (type
== IEEE80211_IF_TYPE_MNTR
)
840 return !!(wl
->monitor
);
841 return (wl
->operating
&&
842 wl
->if_type
== type
);
846 u16
bcm43xx_read16(struct bcm43xx_wldev
*dev
, u16 offset
)
848 return ssb_read16(dev
->dev
, offset
);
852 void bcm43xx_write16(struct bcm43xx_wldev
*dev
, u16 offset
, u16 value
)
854 ssb_write16(dev
->dev
, offset
, value
);
858 u32
bcm43xx_read32(struct bcm43xx_wldev
*dev
, u16 offset
)
860 return ssb_read32(dev
->dev
, offset
);
864 void bcm43xx_write32(struct bcm43xx_wldev
*dev
, u16 offset
, u32 value
)
866 ssb_write32(dev
->dev
, offset
, value
);
869 /** Limit a value between two limits */
873 #define limit_value(value, min, max) \
875 typeof(value) __value = (value); \
876 typeof(value) __min = (min); \
877 typeof(value) __max = (max); \
878 if (__value < __min) \
880 else if (__value > __max) \
885 #endif /* BCM43xx_H_ */