1 From 854dc4b790ce1291326d52b8405ebe771bff2edd Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Wed, 8 Mar 2023 22:42:31 +0100
4 Subject: [PATCH 1/5] nand: brcmnand: add iproc support
6 Add support for the iproc Broadcom NAND controller,
7 used in Northstar SoCs for example. Based on the Linux
10 Cc: Philippe Reynes <philippe.reynes@softathome.com>
11 Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
12 Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
13 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
14 Acked-by: William Zhang <william.zhang@broadcom.com>
15 Link: https://lore.kernel.org/all/20230308214231.378013-1-linus.walleij@linaro.org/
16 Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
18 drivers/mtd/nand/raw/Kconfig | 7 +
19 drivers/mtd/nand/raw/brcmnand/Makefile | 1 +
20 drivers/mtd/nand/raw/brcmnand/iproc_nand.c | 148 +++++++++++++++++++++
21 3 files changed, 156 insertions(+)
22 create mode 100644 drivers/mtd/nand/raw/brcmnand/iproc_nand.c
24 --- a/drivers/mtd/nand/raw/Kconfig
25 +++ b/drivers/mtd/nand/raw/Kconfig
26 @@ -156,6 +156,13 @@ config NAND_BRCMNAND_63158
28 Enable support for broadcom nand driver on bcm63158.
30 +config NAND_BRCMNAND_IPROC
31 + bool "Support Broadcom NAND controller on the iproc family"
32 + depends on NAND_BRCMNAND
34 + Enable support for broadcom nand driver on the Broadcom
35 + iproc family such as Northstar (BCM5301x, BCM4708...)
38 bool "Support TI Davinci NAND controller"
39 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
40 --- a/drivers/mtd/nand/raw/brcmnand/Makefile
41 +++ b/drivers/mtd/nand/raw/brcmnand/Makefile
42 @@ -6,5 +6,6 @@ obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6
43 obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
44 obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
45 obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
46 +obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o
47 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o
48 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o
50 +++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c
52 +// SPDX-License-Identifier: GPL-2.0
54 + * Code borrowed from the Linux driver
55 + * Copyright (C) 2015 Broadcom Corporation
60 +#include <memalign.h>
62 +#include <linux/bitops.h>
63 +#include <linux/err.h>
64 +#include <linux/errno.h>
65 +#include <linux/io.h>
66 +#include <linux/ioport.h>
69 +#include "brcmnand.h"
71 +struct iproc_nand_soc {
72 + struct brcmnand_soc soc;
73 + void __iomem *idm_base;
74 + void __iomem *ext_base;
77 +#define IPROC_NAND_CTLR_READY_OFFSET 0x10
78 +#define IPROC_NAND_CTLR_READY BIT(0)
80 +#define IPROC_NAND_IO_CTRL_OFFSET 0x00
81 +#define IPROC_NAND_APB_LE_MODE BIT(24)
82 +#define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6)
84 +static bool iproc_nand_intc_ack(struct brcmnand_soc *soc)
86 + struct iproc_nand_soc *priv =
87 + container_of(soc, struct iproc_nand_soc, soc);
88 + void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET;
89 + u32 val = brcmnand_readl(mmio);
91 + if (val & IPROC_NAND_CTLR_READY) {
92 + brcmnand_writel(IPROC_NAND_CTLR_READY, mmio);
99 +static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en)
101 + struct iproc_nand_soc *priv =
102 + container_of(soc, struct iproc_nand_soc, soc);
103 + void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
104 + u32 val = brcmnand_readl(mmio);
107 + val |= IPROC_NAND_INT_CTRL_READ_ENABLE;
109 + val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE;
111 + brcmnand_writel(val, mmio);
114 +static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare,
117 + struct iproc_nand_soc *priv =
118 + container_of(soc, struct iproc_nand_soc, soc);
119 + void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
122 + val = brcmnand_readl(mmio);
125 + * In the case of BE or when dealing with NAND data, always configure
126 + * the APB bus to LE mode before accessing the FIFO and back to BE mode
127 + * after the access is done
129 + if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN) || !is_param) {
131 + val |= IPROC_NAND_APB_LE_MODE;
133 + val &= ~IPROC_NAND_APB_LE_MODE;
134 + } else { /* when in LE accessing the parameter page, keep APB in BE */
135 + val &= ~IPROC_NAND_APB_LE_MODE;
138 + brcmnand_writel(val, mmio);
141 +static int iproc_nand_probe(struct udevice *dev)
143 + struct udevice *pdev = dev;
144 + struct iproc_nand_soc *priv = dev_get_priv(dev);
145 + struct brcmnand_soc *soc;
146 + struct resource res;
151 + ret = dev_read_resource_byname(pdev, "iproc-idm", &res);
155 + priv->idm_base = devm_ioremap(dev, res.start, resource_size(&res));
156 + if (IS_ERR(priv->idm_base))
157 + return PTR_ERR(priv->idm_base);
159 + ret = dev_read_resource_byname(pdev, "iproc-ext", &res);
163 + priv->ext_base = devm_ioremap(dev, res.start, resource_size(&res));
164 + if (IS_ERR(priv->ext_base))
165 + return PTR_ERR(priv->ext_base);
167 + soc->ctlrdy_ack = iproc_nand_intc_ack;
168 + soc->ctlrdy_set_enabled = iproc_nand_intc_set;
169 + soc->prepare_data_bus = iproc_nand_apb_access;
171 + return brcmnand_probe(pdev, soc);
174 +static const struct udevice_id iproc_nand_dt_ids[] = {
176 + .compatible = "brcm,nand-iproc",
181 +U_BOOT_DRIVER(iproc_nand) = {
182 + .name = "iproc-nand",
184 + .of_match = iproc_nand_dt_ids,
185 + .probe = iproc_nand_probe,
186 + .priv_auto = sizeof(struct iproc_nand_soc),
189 +void board_nand_init(void)
191 + struct udevice *dev;
194 + ret = uclass_get_device_by_driver(UCLASS_MTD,
195 + DM_DRIVER_GET(iproc_nand), &dev);
196 + if (ret && ret != -ENODEV)
197 + pr_err("Failed to initialize %s. (error %d)\n", dev->name,