1 From 3d6098a662b7ff5b80c4b75c54fcd1b2baf9f150 Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Mon, 24 Apr 2023 09:38:28 +0200
4 Subject: [PATCH 3/5] arm: dts: Import device tree for Broadcom Northstar
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 This brings in the main SoC device tree used by the
10 Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
11 This is taken from the v6.3 Linux kernel.
13 Cc: Rafał Miłecki <rafal@milecki.pl>
14 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
16 arch/arm/dts/bcm5301x.dtsi | 581 ++++++++++++++++++++++++++++
17 include/dt-bindings/clock/bcm-nsp.h | 51 +++
18 2 files changed, 632 insertions(+)
19 create mode 100644 arch/arm/dts/bcm5301x.dtsi
20 create mode 100644 include/dt-bindings/clock/bcm-nsp.h
23 +++ b/arch/arm/dts/bcm5301x.dtsi
26 + * Broadcom BCM470X / BCM5301X ARM platform code.
27 + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
28 + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
30 + * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
32 + * Licensed under the GNU/GPL. See COPYING for details.
35 +#include <dt-bindings/clock/bcm-nsp.h>
36 +#include <dt-bindings/gpio/gpio.h>
37 +#include <dt-bindings/input/input.h>
38 +#include <dt-bindings/interrupt-controller/irq.h>
39 +#include <dt-bindings/interrupt-controller/arm-gic.h>
42 + #address-cells = <1>;
44 + interrupt-parent = <&gic>;
46 + chipcommon-a-bus@18000000 {
47 + compatible = "simple-bus";
48 + ranges = <0x00000000 0x18000000 0x00001000>;
49 + #address-cells = <1>;
53 + compatible = "ns16550";
54 + reg = <0x0300 0x100>;
55 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
56 + clocks = <&iprocslow>;
57 + status = "disabled";
61 + compatible = "ns16550";
62 + reg = <0x0400 0x100>;
63 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
64 + clocks = <&iprocslow>;
65 + pinctrl-names = "default";
66 + pinctrl-0 = <&pinmux_uart1>;
67 + status = "disabled";
71 + mpcore-bus@19000000 {
72 + compatible = "simple-bus";
73 + ranges = <0x00000000 0x19000000 0x00023000>;
74 + #address-cells = <1>;
79 + compatible = "brcm,nsp-armpll";
81 + reg = <0x00000 0x1000>;
85 + compatible = "arm,cortex-a9-scu";
86 + reg = <0x20000 0x100>;
90 + compatible = "arm,cortex-a9-global-timer";
91 + reg = <0x20200 0x100>;
92 + interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
93 + clocks = <&periph_clk>;
97 + compatible = "arm,cortex-a9-twd-timer";
98 + reg = <0x20600 0x20>;
99 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
100 + IRQ_TYPE_EDGE_RISING)>;
101 + clocks = <&periph_clk>;
105 + compatible = "arm,cortex-a9-twd-wdt";
106 + reg = <0x20620 0x20>;
107 + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
108 + IRQ_TYPE_EDGE_RISING)>;
109 + clocks = <&periph_clk>;
112 + gic: interrupt-controller@21000 {
113 + compatible = "arm,cortex-a9-gic";
114 + #interrupt-cells = <3>;
115 + #address-cells = <0>;
116 + interrupt-controller;
117 + reg = <0x21000 0x1000>,
121 + L2: cache-controller@22000 {
122 + compatible = "arm,pl310-cache";
123 + reg = <0x22000 0x1000>;
125 + arm,shared-override;
126 + prefetch-data = <1>;
127 + prefetch-instr = <1>;
133 + compatible = "arm,cortex-a9-pmu";
135 + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
136 + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
140 + #address-cells = <1>;
145 + #clock-cells = <0>;
146 + compatible = "fixed-clock";
147 + clock-frequency = <25000000>;
150 + iprocmed: iprocmed {
151 + #clock-cells = <0>;
152 + compatible = "fixed-factor-clock";
153 + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
158 + iprocslow: iprocslow {
159 + #clock-cells = <0>;
160 + compatible = "fixed-factor-clock";
161 + clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
166 + periph_clk: periph_clk {
167 + #clock-cells = <0>;
168 + compatible = "fixed-factor-clock";
176 + compatible = "brcm,bus-axi";
177 + reg = <0x18000000 0x1000>;
178 + ranges = <0x00000000 0x18000000 0x00100000>;
179 + #address-cells = <1>;
182 + #interrupt-cells = <1>;
183 + interrupt-map-mask = <0x000fffff 0xffff>;
186 + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
188 + /* Switch Register Access Block */
189 + <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
190 + <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
191 + <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
192 + <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
193 + <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
194 + <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
195 + <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
196 + <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
197 + <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
198 + <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
199 + <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
200 + <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
201 + <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
203 + /* PCIe Controller 0 */
204 + <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
205 + <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
206 + <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
207 + <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
208 + <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
209 + <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
211 + /* PCIe Controller 1 */
212 + <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
213 + <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
214 + <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
215 + <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
216 + <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
217 + <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
219 + /* PCIe Controller 2 */
220 + <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
221 + <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
222 + <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
223 + <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
224 + <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
225 + <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
227 + /* USB 2.0 Controller */
228 + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
230 + /* USB 3.0 Controller */
231 + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
233 + /* Ethernet Controller 0 */
234 + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
236 + /* Ethernet Controller 1 */
237 + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
239 + /* Ethernet Controller 2 */
240 + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
242 + /* Ethernet Controller 3 */
243 + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
245 + /* NAND Controller */
246 + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
247 + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
248 + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
249 + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
250 + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
251 + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
252 + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
253 + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
255 + chipcommon: chipcommon@0 {
256 + reg = <0x00000000 0x1000>;
260 + interrupt-controller;
261 + #interrupt-cells = <2>;
264 + pcie0: pcie@12000 {
265 + reg = <0x00012000 0x1000>;
268 + pcie1: pcie@13000 {
269 + reg = <0x00013000 0x1000>;
272 + pcie2: pcie@14000 {
273 + reg = <0x00014000 0x1000>;
277 + reg = <0x00021000 0x1000>;
279 + #address-cells = <1>;
283 + interrupt-parent = <&gic>;
288 + compatible = "generic-ehci";
289 + reg = <0x00021000 0x1000>;
290 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
291 + phys = <&usb2_phy>;
293 + #address-cells = <1>;
296 + ehci_port1: port@1 {
298 + #trigger-source-cells = <0>;
301 + ehci_port2: port@2 {
303 + #trigger-source-cells = <0>;
310 + compatible = "generic-ohci";
311 + reg = <0x00022000 0x1000>;
312 + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
314 + #address-cells = <1>;
317 + ohci_port1: port@1 {
319 + #trigger-source-cells = <0>;
322 + ohci_port2: port@2 {
324 + #trigger-source-cells = <0>;
330 + reg = <0x00023000 0x1000>;
332 + #address-cells = <1>;
336 + interrupt-parent = <&gic>;
341 + compatible = "generic-xhci";
342 + reg = <0x00023000 0x1000>;
343 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
344 + phys = <&usb3_phy>;
347 + #address-cells = <1>;
350 + xhci_port1: port@1 {
352 + #trigger-source-cells = <0>;
357 + gmac0: ethernet@24000 {
358 + reg = <0x24000 0x800>;
361 + gmac1: ethernet@25000 {
362 + reg = <0x25000 0x800>;
365 + gmac2: ethernet@26000 {
366 + reg = <0x26000 0x800>;
369 + gmac3: ethernet@27000 {
370 + reg = <0x27000 0x800>;
374 + pwm: pwm@18002000 {
375 + compatible = "brcm,iproc-pwm";
376 + reg = <0x18002000 0x28>;
379 + status = "disabled";
382 + mdio: mdio@18003000 {
383 + compatible = "brcm,iproc-mdio";
384 + reg = <0x18003000 0x8>;
386 + #address-cells = <1>;
389 + mdio-mux@18003000 {
390 + compatible = "mdio-mux-mmioreg", "mdio-mux";
391 + mdio-parent-bus = <&mdio>;
392 + #address-cells = <1>;
394 + reg = <0x18003000 0x4>;
395 + mux-mask = <0x200>;
399 + #address-cells = <1>;
402 + usb3_phy: usb3-phy@10 {
403 + compatible = "brcm,ns-ax-usb3-phy";
405 + usb3-dmp-syscon = <&usb3_dmp>;
407 + status = "disabled";
412 + usb3_dmp: syscon@18105000 {
413 + reg = <0x18105000 0x1000>;
416 + uart2: serial@18008000 {
417 + compatible = "ns16550a";
418 + reg = <0x18008000 0x20>;
419 + clocks = <&iprocslow>;
420 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
422 + status = "disabled";
425 + i2c0: i2c@18009000 {
426 + compatible = "brcm,iproc-i2c";
427 + reg = <0x18009000 0x50>;
428 + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
429 + #address-cells = <1>;
431 + clock-frequency = <100000>;
432 + status = "disabled";
436 + compatible = "simple-bus";
437 + ranges = <0 0x1800c000 0x1000>;
438 + #address-cells = <1>;
442 + compatible = "brcm,ns-cru", "simple-mfd";
443 + reg = <0x100 0x1a4>;
445 + #address-cells = <1>;
448 + lcpll0: clock-controller@100 {
449 + #clock-cells = <1>;
450 + compatible = "brcm,nsp-lcpll0";
451 + reg = <0x100 0x14>;
453 + clock-output-names = "lcpll0", "pcie_phy",
457 + genpll: clock-controller@140 {
458 + #clock-cells = <1>;
459 + compatible = "brcm,nsp-genpll";
460 + reg = <0x140 0x24>;
462 + clock-output-names = "genpll", "phy",
464 + "usbclk", "iprocfast",
468 + usb2_phy: phy@164 {
469 + compatible = "brcm,ns-usb2-phy";
471 + brcm,syscon-clkset = <&cru_clkset>;
472 + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
473 + clock-names = "phy-ref-clk";
477 + cru_clkset: syscon@180 {
478 + compatible = "brcm,cru-clkset", "syscon";
482 + pinctrl: pinctrl@1c0 {
483 + compatible = "brcm,bcm4708-pinmux";
484 + reg = <0x1c0 0x24>;
485 + reg-names = "cru_gpio_control";
488 + groups = "spi_grp";
492 + pinmux_i2c: i2c-pins {
493 + groups = "i2c_grp";
497 + pinmux_pwm: pwm-pins {
498 + groups = "pwm0_grp", "pwm1_grp",
499 + "pwm2_grp", "pwm3_grp";
503 + pinmux_uart1: uart1-pins {
504 + groups = "uart1_grp";
505 + function = "uart1";
509 + thermal: thermal@2c0 {
510 + compatible = "brcm,ns-thermal";
511 + reg = <0x2c0 0x10>;
512 + #thermal-sensor-cells = <0>;
517 + srab: ethernet-switch@18007000 {
518 + compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
519 + reg = <0x18007000 0x1000>;
521 + status = "disabled";
523 + /* ports are defined in board DTS */
525 + #address-cells = <1>;
530 + rng: rng@18004000 {
531 + compatible = "brcm,bcm5301x-rng";
532 + reg = <0x18004000 0x14>;
535 + nand_controller: nand-controller@18028000 {
536 + compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
537 + reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
538 + reg-names = "nand", "iproc-idm", "iproc-ext";
539 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
541 + #address-cells = <1>;
548 + compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
549 + reg = <0x18029200 0x184>,
550 + <0x18029000 0x124>,
551 + <0x1811b408 0x004>,
552 + <0x180293a0 0x01c>;
553 + reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
554 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
555 + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
556 + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
557 + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
558 + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
559 + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
560 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
561 + interrupt-names = "mspi_done",
563 + "spi_lr_fullness_reached",
564 + "spi_lr_session_aborted",
565 + "spi_lr_impatient",
566 + "spi_lr_session_done",
568 + clocks = <&iprocmed>;
569 + clock-names = "iprocmed";
571 + #address-cells = <1>;
575 + compatible = "jedec,spi-nor";
577 + spi-max-frequency = <20000000>;
578 + status = "disabled";
581 + compatible = "brcm,bcm947xx-cfe-partitions";
587 + cpu_thermal: cpu-thermal {
588 + polling-delay-passive = <0>;
589 + polling-delay = <1000>;
590 + coefficients = <(-556) 418000>;
591 + thermal-sensors = <&thermal>;
595 + temperature = <125000>;
607 +++ b/include/dt-bindings/clock/bcm-nsp.h
612 + * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
614 + * Redistribution and use in source and binary forms, with or without
615 + * modification, are permitted provided that the following conditions
618 + * * Redistributions of source code must retain the above copyright
619 + * notice, this list of conditions and the following disclaimer.
620 + * * Redistributions in binary form must reproduce the above copyright
621 + * notice, this list of conditions and the following disclaimer in
622 + * the documentation and/or other materials provided with the
624 + * * Neither the name of Broadcom Corporation nor the names of its
625 + * contributors may be used to endorse or promote products derived
626 + * from this software without specific prior written permission.
628 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
629 + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
630 + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
631 + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
632 + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
633 + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
634 + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
635 + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
636 + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
637 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
638 + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
641 +#ifndef _CLOCK_BCM_NSP_H
642 +#define _CLOCK_BCM_NSP_H
644 +/* GENPLL clock channel ID */
645 +#define BCM_NSP_GENPLL 0
646 +#define BCM_NSP_GENPLL_PHY_CLK 1
647 +#define BCM_NSP_GENPLL_ENET_SW_CLK 2
648 +#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
649 +#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
650 +#define BCM_NSP_GENPLL_SATA1_CLK 5
651 +#define BCM_NSP_GENPLL_SATA2_CLK 6
653 +/* LCPLL0 clock channel ID */
654 +#define BCM_NSP_LCPLL0 0
655 +#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
656 +#define BCM_NSP_LCPLL0_SDIO_CLK 2
657 +#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
659 +#endif /* _CLOCK_BCM_NSP_H */