1 From b81ea0a64b01ae42e8b41d2a8b9a3fabffe97489 Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Mon, 24 Apr 2023 09:38:29 +0200
4 Subject: [PATCH 4/5] arm: Add support for the Broadcom Northstar SoCs
6 Content-Type: text/plain; charset=UTF-8
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9 The original Northstar is an ARM SoC series that comprise
10 BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
11 global timer and a few other things.
13 This series should not be confused with North Star Plus
14 (NSP) which is partly supported by U-Boot already.
16 The SoC is well supported by the Linux kernel and OpenWrt
17 as it is used in many routers.
19 Since we currently don't need any chip-specific quirks
20 and can get the system up from just the device tree, a
21 mach-* directory doesn't even need to be added, just
22 some small Kconfig fragments.
24 Cc: Rafał Miłecki <rafal@milecki.pl>
25 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
27 arch/arm/Kconfig | 21 ++++++++++++++++++++-
28 1 file changed, 20 insertions(+), 1 deletion(-)
30 --- a/arch/arm/Kconfig
31 +++ b/arch/arm/Kconfig
32 @@ -357,7 +357,7 @@ config SYS_ARM_ARCH
35 prompt "Select the ARM data write cache policy"
36 - default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
37 + default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1
38 default SYS_ARM_CACHE_WRITEBACK
40 config SYS_ARM_CACHE_WRITEBACK
41 @@ -670,6 +670,25 @@ config TARGET_BCMCYGNUS
46 + bool "Support Broadcom Northstar"
54 + select ARM_GLOBAL_TIMER
55 + imply SYS_THUMB_BUILD
58 + imply NAND_BRCMNAND_IPROC
60 + Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
61 + ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
65 bool "Support Broadcom Northstar2"