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uboot-d1: add bootloader for upcoming d1 target
[openwrt/staging/981213.git] / package / boot / uboot-d1 / patches / 0011-clk-sunxi-Add-support-for-the-D1-CCU.patch
1 From 73d6c82e34e89cfde880d1948b3e0dc714adead8 Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Sat, 30 Apr 2022 22:34:19 -0500
4 Subject: [PATCH 11/90] clk: sunxi: Add support for the D1 CCU
5
6 Since the D1 CCU binding is defined, we can add support for its
7 gates/resets, following the pattern of the existing drivers.
8
9 Series-to: sunxi
10
11 Signed-off-by: Samuel Holland <samuel@sholland.org>
12 ---
13 drivers/clk/sunxi/Kconfig | 6 +
14 drivers/clk/sunxi/Makefile | 1 +
15 drivers/clk/sunxi/clk_d1.c | 82 ++++++++++++
16 drivers/clk/sunxi/clk_sunxi.c | 5 +
17 include/dt-bindings/clock/sun20i-d1-ccu.h | 156 ++++++++++++++++++++++
18 include/dt-bindings/reset/sun20i-d1-ccu.h | 77 +++++++++++
19 6 files changed, 327 insertions(+)
20 create mode 100644 drivers/clk/sunxi/clk_d1.c
21 create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h
22 create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h
23
24 --- a/drivers/clk/sunxi/Kconfig
25 +++ b/drivers/clk/sunxi/Kconfig
26 @@ -87,6 +87,12 @@ config CLK_SUN8I_H3
27 This enables common clock driver support for platforms based
28 on Allwinner H3/H5 SoC.
29
30 +config CLK_SUN20I_D1
31 + bool "Clock driver for Allwinner D1"
32 + help
33 + This enables common clock driver support for platforms based
34 + on Allwinner D1 SoC.
35 +
36 config CLK_SUN50I_H6
37 bool "Clock driver for Allwinner H6"
38 default MACH_SUN50I_H6
39 --- a/drivers/clk/sunxi/Makefile
40 +++ b/drivers/clk/sunxi/Makefile
41 @@ -19,6 +19,7 @@ obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
42 obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
43 obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
44 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
45 +obj-$(CONFIG_CLK_SUN20I_D1) += clk_d1.o
46 obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
47 obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
48 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
49 --- /dev/null
50 +++ b/drivers/clk/sunxi/clk_d1.c
51 @@ -0,0 +1,82 @@
52 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
53 +/*
54 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
55 + */
56 +
57 +#include <common.h>
58 +#include <clk-uclass.h>
59 +#include <dm.h>
60 +#include <errno.h>
61 +#include <clk/sunxi.h>
62 +#include <dt-bindings/clock/sun20i-d1-ccu.h>
63 +#include <dt-bindings/reset/sun20i-d1-ccu.h>
64 +#include <linux/bitops.h>
65 +
66 +static struct ccu_clk_gate d1_gates[] = {
67 + [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
68 + [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
69 + [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
70 + [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
71 + [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
72 + [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
73 + [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
74 + [CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
75 + [CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
76 + [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
77 + [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
78 + [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
79 + [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
80 + [CLK_SPI0] = GATE(0x940, BIT(31)),
81 + [CLK_SPI1] = GATE(0x944, BIT(31)),
82 + [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
83 + [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
84 +
85 + [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
86 +
87 + [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
88 + [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
89 + [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
90 + [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
91 + [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
92 + [CLK_BUS_EHCI1] = GATE(0xa8c, BIT(5)),
93 + [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
94 + [CLK_BUS_LRADC] = GATE(0xa9c, BIT(0)),
95 +
96 + [CLK_RISCV] = GATE(0xd04, BIT(31)),
97 +};
98 +
99 +static struct ccu_reset d1_resets[] = {
100 + [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
101 + [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
102 + [RST_BUS_MMC2] = RESET(0x84c, BIT(18)),
103 + [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
104 + [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
105 + [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
106 + [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
107 + [RST_BUS_UART4] = RESET(0x90c, BIT(20)),
108 + [RST_BUS_UART5] = RESET(0x90c, BIT(21)),
109 + [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
110 + [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
111 + [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
112 + [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
113 + [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
114 + [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
115 +
116 + [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
117 +
118 + [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
119 + [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
120 + [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
121 + [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
122 + [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
123 + [RST_BUS_EHCI1] = RESET(0xa8c, BIT(21)),
124 + [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
125 + [RST_BUS_LRADC] = RESET(0xa9c, BIT(16)),
126 +};
127 +
128 +const struct ccu_desc d1_ccu_desc = {
129 + .gates = d1_gates,
130 + .resets = d1_resets,
131 + .num_gates = ARRAY_SIZE(d1_gates),
132 + .num_resets = ARRAY_SIZE(d1_resets),
133 +};
134 --- a/drivers/clk/sunxi/clk_sunxi.c
135 +++ b/drivers/clk/sunxi/clk_sunxi.c
136 @@ -118,6 +118,7 @@ extern const struct ccu_desc a64_ccu_des
137 extern const struct ccu_desc a80_ccu_desc;
138 extern const struct ccu_desc a80_mmc_clk_desc;
139 extern const struct ccu_desc a83t_ccu_desc;
140 +extern const struct ccu_desc d1_ccu_desc;
141 extern const struct ccu_desc f1c100s_ccu_desc;
142 extern const struct ccu_desc h3_ccu_desc;
143 extern const struct ccu_desc h6_ccu_desc;
144 @@ -183,6 +184,10 @@ static const struct udevice_id sunxi_clk
145 { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
146 .data = (ulong)&a80_mmc_clk_desc },
147 #endif
148 +#ifdef CONFIG_CLK_SUN20I_D1
149 + { .compatible = "allwinner,sun20i-d1-ccu",
150 + .data = (ulong)&d1_ccu_desc },
151 +#endif
152 #ifdef CONFIG_CLK_SUN50I_A64
153 { .compatible = "allwinner,sun50i-a64-ccu",
154 .data = (ulong)&a64_ccu_desc },
155 --- /dev/null
156 +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h
157 @@ -0,0 +1,156 @@
158 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
159 +/*
160 + * Copyright (C) 2020 huangzhenwei@allwinnertech.com
161 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
162 + */
163 +
164 +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
165 +#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
166 +
167 +#define CLK_PLL_CPUX 0
168 +#define CLK_PLL_DDR0 1
169 +#define CLK_PLL_PERIPH0_4X 2
170 +#define CLK_PLL_PERIPH0_2X 3
171 +#define CLK_PLL_PERIPH0_800M 4
172 +#define CLK_PLL_PERIPH0 5
173 +#define CLK_PLL_PERIPH0_DIV3 6
174 +#define CLK_PLL_VIDEO0_4X 7
175 +#define CLK_PLL_VIDEO0_2X 8
176 +#define CLK_PLL_VIDEO0 9
177 +#define CLK_PLL_VIDEO1_4X 10
178 +#define CLK_PLL_VIDEO1_2X 11
179 +#define CLK_PLL_VIDEO1 12
180 +#define CLK_PLL_VE 13
181 +#define CLK_PLL_AUDIO0_4X 14
182 +#define CLK_PLL_AUDIO0_2X 15
183 +#define CLK_PLL_AUDIO0 16
184 +#define CLK_PLL_AUDIO1 17
185 +#define CLK_PLL_AUDIO1_DIV2 18
186 +#define CLK_PLL_AUDIO1_DIV5 19
187 +#define CLK_CPUX 20
188 +#define CLK_CPUX_AXI 21
189 +#define CLK_CPUX_APB 22
190 +#define CLK_PSI_AHB 23
191 +#define CLK_APB0 24
192 +#define CLK_APB1 25
193 +#define CLK_MBUS 26
194 +#define CLK_DE 27
195 +#define CLK_BUS_DE 28
196 +#define CLK_DI 29
197 +#define CLK_BUS_DI 30
198 +#define CLK_G2D 31
199 +#define CLK_BUS_G2D 32
200 +#define CLK_CE 33
201 +#define CLK_BUS_CE 34
202 +#define CLK_VE 35
203 +#define CLK_BUS_VE 36
204 +#define CLK_BUS_DMA 37
205 +#define CLK_BUS_MSGBOX0 38
206 +#define CLK_BUS_MSGBOX1 39
207 +#define CLK_BUS_MSGBOX2 40
208 +#define CLK_BUS_SPINLOCK 41
209 +#define CLK_BUS_HSTIMER 42
210 +#define CLK_AVS 43
211 +#define CLK_BUS_DBG 44
212 +#define CLK_BUS_PWM 45
213 +#define CLK_BUS_IOMMU 46
214 +#define CLK_DRAM 47
215 +#define CLK_MBUS_DMA 48
216 +#define CLK_MBUS_VE 49
217 +#define CLK_MBUS_CE 50
218 +#define CLK_MBUS_TVIN 51
219 +#define CLK_MBUS_CSI 52
220 +#define CLK_MBUS_G2D 53
221 +#define CLK_MBUS_RISCV 54
222 +#define CLK_BUS_DRAM 55
223 +#define CLK_MMC0 56
224 +#define CLK_MMC1 57
225 +#define CLK_MMC2 58
226 +#define CLK_BUS_MMC0 59
227 +#define CLK_BUS_MMC1 60
228 +#define CLK_BUS_MMC2 61
229 +#define CLK_BUS_UART0 62
230 +#define CLK_BUS_UART1 63
231 +#define CLK_BUS_UART2 64
232 +#define CLK_BUS_UART3 65
233 +#define CLK_BUS_UART4 66
234 +#define CLK_BUS_UART5 67
235 +#define CLK_BUS_I2C0 68
236 +#define CLK_BUS_I2C1 69
237 +#define CLK_BUS_I2C2 70
238 +#define CLK_BUS_I2C3 71
239 +#define CLK_SPI0 72
240 +#define CLK_SPI1 73
241 +#define CLK_BUS_SPI0 74
242 +#define CLK_BUS_SPI1 75
243 +#define CLK_EMAC_25M 76
244 +#define CLK_BUS_EMAC 77
245 +#define CLK_IR_TX 78
246 +#define CLK_BUS_IR_TX 79
247 +#define CLK_BUS_GPADC 80
248 +#define CLK_BUS_THS 81
249 +#define CLK_I2S0 82
250 +#define CLK_I2S1 83
251 +#define CLK_I2S2 84
252 +#define CLK_I2S2_ASRC 85
253 +#define CLK_BUS_I2S0 86
254 +#define CLK_BUS_I2S1 87
255 +#define CLK_BUS_I2S2 88
256 +#define CLK_SPDIF_TX 89
257 +#define CLK_SPDIF_RX 90
258 +#define CLK_BUS_SPDIF 91
259 +#define CLK_DMIC 92
260 +#define CLK_BUS_DMIC 93
261 +#define CLK_AUDIO_DAC 94
262 +#define CLK_AUDIO_ADC 95
263 +#define CLK_BUS_AUDIO 96
264 +#define CLK_USB_OHCI0 97
265 +#define CLK_USB_OHCI1 98
266 +#define CLK_BUS_OHCI0 99
267 +#define CLK_BUS_OHCI1 100
268 +#define CLK_BUS_EHCI0 101
269 +#define CLK_BUS_EHCI1 102
270 +#define CLK_BUS_OTG 103
271 +#define CLK_BUS_LRADC 104
272 +#define CLK_BUS_DPSS_TOP 105
273 +#define CLK_HDMI_24M 106
274 +#define CLK_HDMI_CEC_32K 107
275 +#define CLK_HDMI_CEC 108
276 +#define CLK_BUS_HDMI 109
277 +#define CLK_MIPI_DSI 110
278 +#define CLK_BUS_MIPI_DSI 111
279 +#define CLK_TCON_LCD0 112
280 +#define CLK_BUS_TCON_LCD0 113
281 +#define CLK_TCON_TV 114
282 +#define CLK_BUS_TCON_TV 115
283 +#define CLK_TVE 116
284 +#define CLK_BUS_TVE_TOP 117
285 +#define CLK_BUS_TVE 118
286 +#define CLK_TVD 119
287 +#define CLK_BUS_TVD_TOP 120
288 +#define CLK_BUS_TVD 121
289 +#define CLK_LEDC 122
290 +#define CLK_BUS_LEDC 123
291 +#define CLK_CSI_TOP 124
292 +#define CLK_CSI_MCLK 125
293 +#define CLK_BUS_CSI 126
294 +#define CLK_TPADC 127
295 +#define CLK_BUS_TPADC 128
296 +#define CLK_BUS_TZMA 129
297 +#define CLK_DSP 130
298 +#define CLK_BUS_DSP_CFG 131
299 +#define CLK_RISCV 132
300 +#define CLK_RISCV_AXI 133
301 +#define CLK_BUS_RISCV_CFG 134
302 +#define CLK_FANOUT_24M 135
303 +#define CLK_FANOUT_12M 136
304 +#define CLK_FANOUT_16M 137
305 +#define CLK_FANOUT_25M 138
306 +#define CLK_FANOUT_32K 139
307 +#define CLK_FANOUT_27M 140
308 +#define CLK_FANOUT_PCLK 141
309 +#define CLK_FANOUT0 142
310 +#define CLK_FANOUT1 143
311 +#define CLK_FANOUT2 144
312 +
313 +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */
314 --- /dev/null
315 +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h
316 @@ -0,0 +1,77 @@
317 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
318 +/*
319 + * Copyright (c) 2020 huangzhenwei@allwinnertech.com
320 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
321 + */
322 +
323 +#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
324 +#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_
325 +
326 +#define RST_MBUS 0
327 +#define RST_BUS_DE 1
328 +#define RST_BUS_DI 2
329 +#define RST_BUS_G2D 3
330 +#define RST_BUS_CE 4
331 +#define RST_BUS_VE 5
332 +#define RST_BUS_DMA 6
333 +#define RST_BUS_MSGBOX0 7
334 +#define RST_BUS_MSGBOX1 8
335 +#define RST_BUS_MSGBOX2 9
336 +#define RST_BUS_SPINLOCK 10
337 +#define RST_BUS_HSTIMER 11
338 +#define RST_BUS_DBG 12
339 +#define RST_BUS_PWM 13
340 +#define RST_BUS_DRAM 14
341 +#define RST_BUS_MMC0 15
342 +#define RST_BUS_MMC1 16
343 +#define RST_BUS_MMC2 17
344 +#define RST_BUS_UART0 18
345 +#define RST_BUS_UART1 19
346 +#define RST_BUS_UART2 20
347 +#define RST_BUS_UART3 21
348 +#define RST_BUS_UART4 22
349 +#define RST_BUS_UART5 23
350 +#define RST_BUS_I2C0 24
351 +#define RST_BUS_I2C1 25
352 +#define RST_BUS_I2C2 26
353 +#define RST_BUS_I2C3 27
354 +#define RST_BUS_SPI0 28
355 +#define RST_BUS_SPI1 29
356 +#define RST_BUS_EMAC 30
357 +#define RST_BUS_IR_TX 31
358 +#define RST_BUS_GPADC 32
359 +#define RST_BUS_THS 33
360 +#define RST_BUS_I2S0 34
361 +#define RST_BUS_I2S1 35
362 +#define RST_BUS_I2S2 36
363 +#define RST_BUS_SPDIF 37
364 +#define RST_BUS_DMIC 38
365 +#define RST_BUS_AUDIO 39
366 +#define RST_USB_PHY0 40
367 +#define RST_USB_PHY1 41
368 +#define RST_BUS_OHCI0 42
369 +#define RST_BUS_OHCI1 43
370 +#define RST_BUS_EHCI0 44
371 +#define RST_BUS_EHCI1 45
372 +#define RST_BUS_OTG 46
373 +#define RST_BUS_LRADC 47
374 +#define RST_BUS_DPSS_TOP 48
375 +#define RST_BUS_HDMI_SUB 49
376 +#define RST_BUS_HDMI_MAIN 50
377 +#define RST_BUS_MIPI_DSI 51
378 +#define RST_BUS_TCON_LCD0 52
379 +#define RST_BUS_TCON_TV 53
380 +#define RST_BUS_LVDS0 54
381 +#define RST_BUS_TVE 55
382 +#define RST_BUS_TVE_TOP 56
383 +#define RST_BUS_TVD 57
384 +#define RST_BUS_TVD_TOP 58
385 +#define RST_BUS_LEDC 59
386 +#define RST_BUS_CSI 60
387 +#define RST_BUS_TPADC 61
388 +#define RST_DSP 62
389 +#define RST_BUS_DSP_CFG 63
390 +#define RST_BUS_DSP_DBG 64
391 +#define RST_BUS_RISCV_CFG 65
392 +
393 +#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */
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