1 From 5a909f4d4d10f3a7a59b3b75eee502937e166891 Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Mon, 2 May 2022 22:00:05 -0500
4 Subject: [PATCH 13/90] clk: sunxi: Add a driver for the legacy A31/A23/A33
7 Signed-off-by: Samuel Holland <samuel@sholland.org>
9 drivers/clk/sunxi/Kconfig | 13 ++++-
10 drivers/clk/sunxi/Makefile | 1 +
11 drivers/clk/sunxi/clk_a31_apb0.c | 97 ++++++++++++++++++++++++++++++++
12 include/clk/sunxi.h | 1 +
13 4 files changed, 110 insertions(+), 2 deletions(-)
14 create mode 100644 drivers/clk/sunxi/clk_a31_apb0.c
16 --- a/drivers/clk/sunxi/Kconfig
17 +++ b/drivers/clk/sunxi/Kconfig
18 @@ -38,12 +38,21 @@ config CLK_SUN6I_A31
19 This enables common clock driver support for platforms based
20 on Allwinner A31/A31s SoC.
22 +config CLK_SUN6I_A31_APB0
23 + bool "Clock driver for Allwinner A31 generation PRCM (legacy)"
24 + default MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
26 + This enables common clock driver support for the PRCM
27 + in Allwinner A31/A31s/A23/A33 SoCs using the legacy PRCM
30 config CLK_SUN6I_A31_R
31 - bool "Clock driver for Allwinner A31 generation PRCM"
32 + bool "Clock driver for Allwinner A31 generation PRCM (CCU)"
33 default SUNXI_GEN_SUN6I
35 This enables common clock driver support for the PRCM
36 - in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
37 + in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs using
38 + the new CCU binding.
41 bool "Clock driver for Allwinner A23/A33"
42 --- a/drivers/clk/sunxi/Makefile
43 +++ b/drivers/clk/sunxi/Makefile
44 @@ -12,6 +12,7 @@ obj-$(CONFIG_CLK_SUNIV_F1C100S) += clk_f
45 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
46 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
47 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
48 +obj-$(CONFIG_CLK_SUN6I_A31_APB0) += clk_a31_apb0.o
49 obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
50 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
51 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
53 +++ b/drivers/clk/sunxi/clk_a31_apb0.c
55 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
57 + * Copyright (C) Samuel Holland <samuel@sholland.org>
60 +#include <clk-uclass.h>
62 +#include <clk/sunxi.h>
63 +#include <linux/bitops.h>
65 +static struct ccu_clk_gate sun6i_apb0_gates[] = {
66 + [0] = GATE(0x028, BIT(0)),
67 + [1] = GATE(0x028, BIT(1)),
68 + [2] = GATE(0x028, BIT(2)),
69 + [3] = GATE(0x028, BIT(3)),
70 + [4] = GATE(0x028, BIT(4)),
71 + [5] = GATE(0x028, BIT(5)),
72 + [6] = GATE(0x028, BIT(6)),
73 + [7] = GATE(0x028, BIT(7)),
76 +static struct ccu_reset sun6i_apb0_resets[] = {
77 + [0] = RESET(0x0b0, BIT(0)),
78 + [1] = RESET(0x0b0, BIT(1)),
79 + [2] = RESET(0x0b0, BIT(2)),
80 + [3] = RESET(0x0b0, BIT(3)),
81 + [4] = RESET(0x0b0, BIT(4)),
82 + [5] = RESET(0x0b0, BIT(5)),
83 + [6] = RESET(0x0b0, BIT(6)),
84 + [7] = RESET(0x0b0, BIT(7)),
87 +const struct ccu_desc sun6i_apb0_clk_desc = {
88 + .gates = sun6i_apb0_gates,
89 + .resets = sun6i_apb0_resets,
90 + .num_gates = ARRAY_SIZE(sun6i_apb0_gates),
91 + .num_resets = ARRAY_SIZE(sun6i_apb0_resets),
94 +static int sun6i_apb0_of_to_plat(struct udevice *dev)
96 + struct ccu_plat *plat = dev_get_plat(dev);
98 + plat->base = dev_read_addr_ptr(dev->parent);
102 + plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
109 +static const struct udevice_id sun6i_apb0_clk_ids[] = {
110 + { .compatible = "allwinner,sun6i-a31-apb0-gates-clk",
111 + .data = (ulong)&sun6i_apb0_clk_desc },
112 + { .compatible = "allwinner,sun8i-a23-apb0-gates-clk",
113 + .data = (ulong)&sun6i_apb0_clk_desc },
117 +U_BOOT_DRIVER(sun6i_apb0_clk) = {
118 + .name = "sun6i_apb0_clk",
120 + .of_match = sun6i_apb0_clk_ids,
121 + .of_to_plat = sun6i_apb0_of_to_plat,
122 + .plat_auto = sizeof(struct ccu_plat),
123 + .ops = &sunxi_clk_ops,
126 +static const struct udevice_id sun6i_apb0_reset_ids[] = {
127 + { .compatible = "allwinner,sun6i-a31-clock-reset",
128 + .data = (ulong)&sun6i_apb0_clk_desc },
132 +U_BOOT_DRIVER(sun6i_apb0_reset) = {
133 + .name = "sun6i_apb0_reset",
134 + .id = UCLASS_RESET,
135 + .of_match = sun6i_apb0_reset_ids,
136 + .of_to_plat = sun6i_apb0_of_to_plat,
137 + .plat_auto = sizeof(struct ccu_plat),
138 + .ops = &sunxi_reset_ops,
141 +static const struct udevice_id sun6i_prcm_mfd_ids[] = {
142 + { .compatible = "allwinner,sun6i-a31-prcm" },
143 + { .compatible = "allwinner,sun8i-a23-prcm" },
147 +U_BOOT_DRIVER(sun6i_prcm_mfd) = {
148 + .name = "sun6i_prcm_mfd",
149 + .id = UCLASS_SIMPLE_BUS,
150 + .of_match = sun6i_prcm_mfd_ids,
152 --- a/include/clk/sunxi.h
153 +++ b/include/clk/sunxi.h
154 @@ -86,5 +86,6 @@ struct ccu_plat {
157 extern struct clk_ops sunxi_clk_ops;
158 +extern struct reset_ops sunxi_reset_ops;
160 #endif /* _CLK_SUNXI_H */