1 From fdf871a6089ee2f56439880b69d33a7d0d707d15 Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Sat, 28 Aug 2021 22:24:28 -0500
4 Subject: [PATCH 20/90] pinctrl: sunxi: Add support for the D1
6 Signed-off-by: Samuel Holland <samuel@sholland.org>
8 drivers/pinctrl/sunxi/Kconfig | 5 +++++
9 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 31 +++++++++++++++++++++++++++
10 2 files changed, 36 insertions(+)
12 --- a/drivers/pinctrl/sunxi/Kconfig
13 +++ b/drivers/pinctrl/sunxi/Kconfig
14 @@ -89,6 +89,11 @@ config PINCTRL_SUN9I_A80_R
18 +config PINCTRL_SUN20I_D1
19 + bool "Support for the Allwinner D1 PIO"
20 + default TARGET_SUN20I_D1
21 + select PINCTRL_SUNXI
23 config PINCTRL_SUN50I_A64
24 bool "Support for the Allwinner A64 PIO"
26 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
27 +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
28 @@ -588,6 +588,31 @@ static const struct sunxi_pinctrl_desc _
32 +static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
33 + { "emac", 8 }, /* PE0-PE15 */
36 + { "i2c0", 4 }, /* PB10-PB11 */
37 + { "mmc0", 2 }, /* PF0-PF5 */
38 + { "mmc1", 2 }, /* PG0-PG5 */
39 + { "mmc2", 3 }, /* PC2-PC7 */
40 + { "spi0", 2 }, /* PC2-PC7 */
41 +#if IS_ENABLED(CONFIG_UART0_PORT_F)
42 + { "uart0", 3 }, /* PF2-PF4 */
44 + { "uart0", 6 }, /* PB8-PB9 */
46 + { "uart1", 2 }, /* PG6-PG7 */
47 + { "uart2", 7 }, /* PB0-PB1 */
50 +static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
51 + .functions = sun20i_d1_pinctrl_functions,
52 + .num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions),
53 + .first_bank = SUNXI_GPIO_A,
57 static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = {
58 { "emac", 4 }, /* PD8-PD23 */
60 @@ -849,6 +874,12 @@ static const struct udevice_id sunxi_pin
61 .data = (ulong)&sun9i_a80_r_pinctrl_desc,
64 +#ifdef CONFIG_PINCTRL_SUN20I_D1
66 + .compatible = "allwinner,sun20i-d1-pinctrl",
67 + .data = (ulong)&sun20i_d1_pinctrl_desc,
70 #ifdef CONFIG_PINCTRL_SUN50I_A64
72 .compatible = "allwinner,sun50i-a64-pinctrl",