1 From ce792f7abd4294ebba76f76d9d7aa90c7970de8e Mon Sep 17 00:00:00 2001
2 From: Samuel Holland <samuel@sholland.org>
3 Date: Thu, 4 Aug 2022 23:35:09 -0500
4 Subject: [PATCH 78/90] riscv: Add Allwinner D1 devicetrees
6 Signed-off-by: Samuel Holland <samuel@sholland.org>
8 arch/riscv/dts/Makefile | 9 +
9 .../riscv/dts/sun20i-d1-clockworkpi-v3.14.dts | 242 +++++
10 .../dts/sun20i-d1-common-regulators.dtsi | 51 +
11 arch/riscv/dts/sun20i-d1-devterm-v3.14.dts | 37 +
12 .../dts/sun20i-d1-dongshan-nezha-stu.dts | 114 +++
13 .../dts/sun20i-d1-lichee-rv-86-panel-480p.dts | 29 +
14 .../dts/sun20i-d1-lichee-rv-86-panel-720p.dts | 10 +
15 .../dts/sun20i-d1-lichee-rv-86-panel.dtsi | 92 ++
16 arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts | 74 ++
17 arch/riscv/dts/sun20i-d1-lichee-rv.dts | 84 ++
18 arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts | 128 +++
19 arch/riscv/dts/sun20i-d1-nezha.dts | 171 ++++
20 arch/riscv/dts/sun20i-d1.dtsi | 900 ++++++++++++++++++
21 arch/riscv/dts/sunxi-u-boot.dtsi | 68 ++
22 include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 +
23 include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 +
24 16 files changed, 2044 insertions(+)
25 create mode 100644 arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
26 create mode 100644 arch/riscv/dts/sun20i-d1-common-regulators.dtsi
27 create mode 100644 arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
28 create mode 100644 arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
29 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
30 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
31 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
32 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
33 create mode 100644 arch/riscv/dts/sun20i-d1-lichee-rv.dts
34 create mode 100644 arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
35 create mode 100644 arch/riscv/dts/sun20i-d1-nezha.dts
36 create mode 100644 arch/riscv/dts/sun20i-d1.dtsi
37 create mode 100644 arch/riscv/dts/sunxi-u-boot.dtsi
38 create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h
39 create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h
41 --- a/arch/riscv/dts/Makefile
42 +++ b/arch/riscv/dts/Makefile
43 @@ -7,6 +7,15 @@ dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) +
44 dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
45 dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
46 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
47 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-clockworkpi-v3.14.dtb
48 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-devterm-v3.14.dtb
49 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-dongshan-nezha-stu.dtb
50 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-480p.dtb
51 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-86-panel-720p.dtb
52 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv-dock.dtb
53 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-lichee-rv.dtb
54 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-mangopi-mq-pro.dtb
55 +dtb-$(CONFIG_TARGET_SUN20I_D1) += sun20i-d1-nezha.dtb
57 include $(srctree)/scripts/Makefile.dts
60 +++ b/arch/riscv/dts/sun20i-d1-clockworkpi-v3.14.dts
62 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
63 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
67 +#include <dt-bindings/gpio/gpio.h>
69 +#include "sun20i-d1.dtsi"
70 +#include "sun20i-d1-common-regulators.dtsi"
73 + model = "ClockworkPi v3.14 (R-01)";
74 + compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
77 + ethernet0 = &ap6256;
83 + stdout-path = "serial0:115200n8";
87 + * This regulator is PWM-controlled, but the PWM controller is not
88 + * yet supported, so fix the regulator to its default voltage.
90 + reg_vdd_cpu: vdd-cpu {
91 + compatible = "regulator-fixed";
92 + regulator-name = "vdd-cpu";
93 + regulator-min-microvolt = <1100000>;
94 + regulator-max-microvolt = <1100000>;
95 + vin-supply = <®_vcc>;
98 + wifi_pwrseq: wifi-pwrseq {
99 + compatible = "mmc-pwrseq-simple";
100 + reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
105 + cpu-supply = <®_vdd_cpu>;
113 + pinctrl-0 = <&i2c0_pb10_pins>;
114 + pinctrl-names = "default";
118 + compatible = "x-powers,axp228", "x-powers,axp221";
120 + interrupt-parent = <&pio>;
121 + interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
122 + interrupt-controller;
123 + #interrupt-cells = <1>;
125 + ac_power_supply: ac-power {
126 + compatible = "x-powers,axp221-ac-power-supply";
130 + compatible = "x-powers,axp221-adc";
131 + #io-channel-cells = <1>;
134 + battery_power_supply: battery-power {
135 + compatible = "x-powers,axp221-battery-power-supply";
139 + x-powers,dcdc-freq = <3000>;
142 + regulator-name = "sys-3v3";
143 + regulator-always-on;
144 + regulator-min-microvolt = <3300000>;
145 + regulator-max-microvolt = <3300000>;
149 + regulator-name = "sys-1v8";
150 + regulator-always-on;
151 + regulator-min-microvolt = <1800000>;
152 + regulator-max-microvolt = <1800000>;
156 + regulator-name = "aud-3v3";
157 + regulator-min-microvolt = <3300000>;
158 + regulator-max-microvolt = <3300000>;
162 + regulator-name = "disp-3v3";
163 + regulator-always-on;
164 + regulator-min-microvolt = <3300000>;
165 + regulator-max-microvolt = <3300000>;
169 + regulator-name = "vdd-wifi";
170 + regulator-min-microvolt = <1800000>;
171 + regulator-max-microvolt = <1800000>;
174 + /* DLDO1 and ELDO1-3 are connected in parallel. */
176 + regulator-name = "vbat-wifi-a";
177 + regulator-always-on;
178 + regulator-min-microvolt = <3300000>;
179 + regulator-max-microvolt = <3300000>;
182 + /* DLDO2-DLDO4 are connected in parallel. */
184 + regulator-name = "vcc-3v3-ext-a";
185 + regulator-always-on;
186 + regulator-min-microvolt = <3300000>;
187 + regulator-max-microvolt = <3300000>;
191 + regulator-name = "vcc-3v3-ext-b";
192 + regulator-always-on;
193 + regulator-min-microvolt = <3300000>;
194 + regulator-max-microvolt = <3300000>;
198 + regulator-name = "vcc-3v3-ext-c";
199 + regulator-always-on;
200 + regulator-min-microvolt = <3300000>;
201 + regulator-max-microvolt = <3300000>;
205 + regulator-name = "vbat-wifi-b";
206 + regulator-always-on;
207 + regulator-min-microvolt = <3300000>;
208 + regulator-max-microvolt = <3300000>;
212 + regulator-name = "vbat-wifi-c";
213 + regulator-always-on;
214 + regulator-min-microvolt = <3300000>;
215 + regulator-max-microvolt = <3300000>;
219 + regulator-name = "vbat-wifi-d";
220 + regulator-always-on;
221 + regulator-min-microvolt = <3300000>;
222 + regulator-max-microvolt = <3300000>;
226 + usb_power_supply: usb-power {
227 + compatible = "x-powers,axp221-usb-power-supply";
228 + status = "disabled";
237 + vmmc-supply = <®_dcdc1>;
238 + vqmmc-supply = <®_vcc_3v3>;
239 + pinctrl-0 = <&mmc0_pins>;
240 + pinctrl-names = "default";
246 + mmc-pwrseq = <&wifi_pwrseq>;
248 + vmmc-supply = <®_dldo1>;
249 + vqmmc-supply = <®_aldo3>;
250 + pinctrl-0 = <&mmc1_pins>;
251 + pinctrl-names = "default";
255 + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
257 + interrupt-parent = <&pio>;
258 + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
259 + interrupt-names = "host-wake";
268 + vcc-pg-supply = <®_ldoa>;
272 + pinctrl-0 = <&uart0_pb8_pins>;
273 + pinctrl-names = "default";
279 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
280 + pinctrl-names = "default";
284 + compatible = "brcm,bcm4345c5";
285 + interrupt-parent = <&pio>;
286 + interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
287 + device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
288 + shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
289 + max-speed = <1500000>;
290 + vbat-supply = <®_dldo1>;
291 + vddio-supply = <®_aldo3>;
296 + dr_mode = "peripheral";
301 + usb0_vbus_power-supply = <&ac_power_supply>;
305 +++ b/arch/riscv/dts/sun20i-d1-common-regulators.dtsi
307 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
308 +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
312 + compatible = "regulator-fixed";
313 + regulator-name = "vcc";
314 + regulator-min-microvolt = <5000000>;
315 + regulator-max-microvolt = <5000000>;
318 + reg_vcc_3v3: vcc-3v3 {
319 + compatible = "regulator-fixed";
320 + regulator-name = "vcc-3v3";
321 + regulator-min-microvolt = <3300000>;
322 + regulator-max-microvolt = <3300000>;
323 + vin-supply = <®_vcc>;
328 + vref-supply = <®_aldo>;
332 + vcc-pb-supply = <®_vcc_3v3>;
333 + vcc-pc-supply = <®_vcc_3v3>;
334 + vcc-pd-supply = <®_vcc_3v3>;
335 + vcc-pe-supply = <®_vcc_3v3>;
336 + vcc-pf-supply = <®_vcc_3v3>;
337 + vcc-pg-supply = <®_vcc_3v3>;
341 + regulator-min-microvolt = <1800000>;
342 + regulator-max-microvolt = <1800000>;
343 + vdd33-supply = <®_vcc_3v3>;
347 + regulator-min-microvolt = <1800000>;
348 + regulator-max-microvolt = <1800000>;
349 + hpldoin-supply = <®_vcc_3v3>;
353 + regulator-always-on;
354 + regulator-min-microvolt = <1800000>;
355 + regulator-max-microvolt = <1800000>;
356 + ldo-in-supply = <®_vcc_3v3>;
359 +++ b/arch/riscv/dts/sun20i-d1-devterm-v3.14.dts
361 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
362 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
366 +#include "sun20i-d1-clockworkpi-v3.14.dts"
369 + model = "Clockwork DevTerm (R-01)";
370 + compatible = "clockwork,r-01-devterm-v3.14",
371 + "clockwork,r-01-clockworkpi-v3.14",
372 + "allwinner,sun20i-d1";
375 + compatible = "gpio-fan";
376 + gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
377 + gpio-fan,speed-map = <0 0>,
379 + #cooling-cells = <2>;
383 + compatible = "i2c-gpio";
384 + sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
385 + scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
386 + #address-cells = <1>;
390 + compatible = "ti,adc101c";
392 + interrupt-parent = <&pio>;
393 + interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
394 + vref-supply = <®_dldo2>;
399 +++ b/arch/riscv/dts/sun20i-d1-dongshan-nezha-stu.dts
401 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
402 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
406 +#include <dt-bindings/gpio/gpio.h>
407 +#include <dt-bindings/leds/common.h>
409 +#include "sun20i-d1.dtsi"
410 +#include "sun20i-d1-common-regulators.dtsi"
413 + model = "Dongshan Nezha STU";
414 + compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
423 + stdout-path = "serial0:115200n8";
427 + compatible = "gpio-leds";
430 + color = <LED_COLOR_ID_GREEN>;
431 + function = LED_FUNCTION_STATUS;
432 + gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
436 + reg_usbvbus: usbvbus {
437 + compatible = "regulator-fixed";
438 + regulator-name = "usbvbus";
439 + regulator-min-microvolt = <5000000>;
440 + regulator-max-microvolt = <5000000>;
441 + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
442 + enable-active-high;
443 + vin-supply = <®_vcc>;
447 + * This regulator is PWM-controlled, but the PWM controller is not
448 + * yet supported, so fix the regulator to its default voltage.
450 + reg_vdd_cpu: vdd-cpu {
451 + compatible = "regulator-fixed";
452 + regulator-name = "vdd-cpu";
453 + regulator-min-microvolt = <1100000>;
454 + regulator-max-microvolt = <1100000>;
455 + vin-supply = <®_vcc>;
460 + cpu-supply = <®_vdd_cpu>;
468 + pinctrl-0 = <&rgmii_pe_pins>;
469 + pinctrl-names = "default";
470 + phy-handle = <&ext_rgmii_phy>;
471 + phy-mode = "rgmii-id";
472 + phy-supply = <®_vcc_3v3>;
477 + ext_rgmii_phy: ethernet-phy@1 {
478 + compatible = "ethernet-phy-ieee802.3-c22";
487 + vmmc-supply = <®_vcc_3v3>;
488 + vqmmc-supply = <®_vcc_3v3>;
489 + pinctrl-0 = <&mmc0_pins>;
490 + pinctrl-names = "default";
499 + pinctrl-0 = <&uart0_pb8_pins>;
500 + pinctrl-names = "default";
510 + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
511 + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
512 + usb0_vbus-supply = <®_usbvbus>;
516 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-480p.dts
518 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
519 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
521 +#include "sun20i-d1-lichee-rv-86-panel.dtsi"
524 + model = "Sipeed Lichee RV 86 Panel (480p)";
525 + compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
526 + "allwinner,sun20i-d1";
530 + pinctrl-0 = <&i2c2_pb0_pins>;
531 + pinctrl-names = "default";
535 + compatible = "focaltech,ft6236";
537 + interrupt-parent = <&pio>;
538 + interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
539 + iovcc-supply = <®_vcc_3v3>;
540 + reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
541 + touchscreen-size-x = <480>;
542 + touchscreen-size-y = <480>;
543 + vcc-supply = <®_vcc_3v3>;
548 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel-720p.dts
550 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
551 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
553 +#include "sun20i-d1-lichee-rv-86-panel.dtsi"
556 + model = "Sipeed Lichee RV 86 Panel (720p)";
557 + compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
558 + "allwinner,sun20i-d1";
561 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-86-panel.dtsi
563 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
564 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
566 +#include "sun20i-d1-lichee-rv.dts"
571 + ethernet1 = &xr829;
574 + /* PC1 is repurposed as BT_WAKE_AP */
575 + /delete-node/ leds;
577 + wifi_pwrseq: wifi-pwrseq {
578 + compatible = "mmc-pwrseq-simple";
579 + clocks = <&ccu CLK_FANOUT1>;
580 + clock-names = "ext_clock";
581 + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
582 + assigned-clocks = <&ccu CLK_FANOUT1>;
583 + assigned-clock-rates = <32768>;
584 + pinctrl-0 = <&clk_pg11_pin>;
585 + pinctrl-names = "default";
594 + pinctrl-0 = <&rmii_pe_pins>;
595 + pinctrl-names = "default";
596 + phy-handle = <&ext_rmii_phy>;
598 + phy-supply = <®_vcc_3v3>;
603 + ext_rmii_phy: ethernet-phy@1 {
604 + compatible = "ethernet-phy-ieee802.3-c22";
606 + reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
612 + mmc-pwrseq = <&wifi_pwrseq>;
614 + vmmc-supply = <®_vcc_3v3>;
615 + vqmmc-supply = <®_vcc_3v3>;
616 + pinctrl-0 = <&mmc1_pins>;
617 + pinctrl-names = "default";
630 + clk_pg11_pin: clk-pg11-pin {
638 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
639 + pinctrl-names = "default";
642 + /* XR829 bluetooth is connected here */
646 + status = "disabled";
650 + /* PD20 and PD21 are repurposed for the LCD panel */
651 + /delete-property/ usb0_id_det-gpios;
652 + /delete-property/ usb0_vbus_det-gpios;
653 + usb1_vbus-supply = <®_vcc>;
656 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv-dock.dts
658 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
659 +// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
660 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
662 +#include <dt-bindings/input/input.h>
664 +#include "sun20i-d1-lichee-rv.dts"
667 + model = "Sipeed Lichee RV Dock";
668 + compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
669 + "allwinner,sun20i-d1";
672 + ethernet1 = &rtl8723ds;
675 + wifi_pwrseq: wifi-pwrseq {
676 + compatible = "mmc-pwrseq-simple";
677 + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
690 + linux,code = <KEY_OK>;
692 + voltage = <220000>;
698 + mmc-pwrseq = <&wifi_pwrseq>;
700 + vmmc-supply = <®_vcc_3v3>;
701 + vqmmc-supply = <®_vcc_3v3>;
702 + pinctrl-0 = <&mmc1_pins>;
703 + pinctrl-names = "default";
706 + rtl8723ds: wifi@1 {
717 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
718 + pinctrl-names = "default";
722 + compatible = "realtek,rtl8723ds-bt";
723 + device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
724 + enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
725 + host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
730 + usb1_vbus-supply = <®_vcc>;
733 +++ b/arch/riscv/dts/sun20i-d1-lichee-rv.dts
735 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
736 +// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
737 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
741 +#include <dt-bindings/gpio/gpio.h>
742 +#include <dt-bindings/leds/common.h>
744 +#include "sun20i-d1.dtsi"
745 +#include "sun20i-d1-common-regulators.dtsi"
748 + model = "Sipeed Lichee RV";
749 + compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
757 + stdout-path = "serial0:115200n8";
761 + compatible = "gpio-leds";
764 + color = <LED_COLOR_ID_GREEN>;
765 + function = LED_FUNCTION_STATUS;
766 + gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
770 + reg_vdd_cpu: vdd-cpu {
771 + compatible = "regulator-fixed";
772 + regulator-name = "vdd-cpu";
773 + regulator-min-microvolt = <900000>;
774 + regulator-max-microvolt = <900000>;
775 + vin-supply = <®_vcc>;
780 + cpu-supply = <®_vdd_cpu>;
791 + vmmc-supply = <®_vcc_3v3>;
792 + vqmmc-supply = <®_vcc_3v3>;
793 + pinctrl-0 = <&mmc0_pins>;
794 + pinctrl-names = "default";
803 + pinctrl-0 = <&uart0_pb8_pins>;
804 + pinctrl-names = "default";
814 + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
815 + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
816 + usb0_vbus-supply = <®_vcc>;
820 +++ b/arch/riscv/dts/sun20i-d1-mangopi-mq-pro.dts
822 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
823 +// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
827 +#include <dt-bindings/gpio/gpio.h>
829 +#include "sun20i-d1.dtsi"
830 +#include "sun20i-d1-common-regulators.dtsi"
833 + model = "MangoPi MQ Pro";
834 + compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
837 + ethernet0 = &rtl8723ds;
843 + stdout-path = "serial0:115200n8";
846 + reg_avdd2v8: avdd2v8 {
847 + compatible = "regulator-fixed";
848 + regulator-name = "avdd2v8";
849 + regulator-min-microvolt = <2800000>;
850 + regulator-max-microvolt = <2800000>;
851 + vin-supply = <®_vcc_3v3>;
855 + compatible = "regulator-fixed";
856 + regulator-name = "dvdd";
857 + regulator-min-microvolt = <1200000>;
858 + regulator-max-microvolt = <1200000>;
859 + vin-supply = <®_vcc_3v3>;
862 + reg_vdd_cpu: vdd-cpu {
863 + compatible = "regulator-fixed";
864 + regulator-name = "vdd-cpu";
865 + regulator-min-microvolt = <1100000>;
866 + regulator-max-microvolt = <1100000>;
867 + vin-supply = <®_vcc>;
870 + wifi_pwrseq: wifi-pwrseq {
871 + compatible = "mmc-pwrseq-simple";
872 + reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
877 + cpu-supply = <®_vdd_cpu>;
886 + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
888 + vmmc-supply = <®_vcc_3v3>;
889 + vqmmc-supply = <®_vcc_3v3>;
890 + pinctrl-0 = <&mmc0_pins>;
891 + pinctrl-names = "default";
897 + mmc-pwrseq = <&wifi_pwrseq>;
899 + vmmc-supply = <®_vcc_3v3>;
900 + vqmmc-supply = <®_vcc_3v3>;
901 + pinctrl-0 = <&mmc1_pins>;
902 + pinctrl-names = "default";
905 + rtl8723ds: wifi@1 {
907 + interrupt-parent = <&pio>;
908 + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
909 + interrupt-names = "host-wake";
918 + vcc-pe-supply = <®_avdd2v8>;
922 + pinctrl-0 = <&uart0_pb8_pins>;
923 + pinctrl-names = "default";
929 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
930 + pinctrl-names = "default";
934 + compatible = "realtek,rtl8723ds-bt";
935 + device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
936 + enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
937 + host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
942 + dr_mode = "peripheral";
947 + usb0_vbus-supply = <®_vcc>;
951 +++ b/arch/riscv/dts/sun20i-d1-nezha.dts
953 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
954 +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
958 +#include <dt-bindings/gpio/gpio.h>
959 +#include <dt-bindings/input/input.h>
961 +#include "sun20i-d1.dtsi"
962 +#include "sun20i-d1-common-regulators.dtsi"
965 + model = "Allwinner D1 Nezha";
966 + compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
970 + ethernet1 = &xr829;
976 + stdout-path = "serial0:115200n8";
979 + reg_usbvbus: usbvbus {
980 + compatible = "regulator-fixed";
981 + regulator-name = "usbvbus";
982 + regulator-min-microvolt = <5000000>;
983 + regulator-max-microvolt = <5000000>;
984 + gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
985 + enable-active-high;
986 + vin-supply = <®_vcc>;
990 + * This regulator is PWM-controlled, but the PWM controller is not
991 + * yet supported, so fix the regulator to its default voltage.
993 + reg_vdd_cpu: vdd-cpu {
994 + compatible = "regulator-fixed";
995 + regulator-name = "vdd-cpu";
996 + regulator-min-microvolt = <1100000>;
997 + regulator-max-microvolt = <1100000>;
998 + vin-supply = <®_vcc>;
1001 + wifi_pwrseq: wifi-pwrseq {
1002 + compatible = "mmc-pwrseq-simple";
1003 + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
1008 + cpu-supply = <®_vdd_cpu>;
1020 + pinctrl-0 = <&rgmii_pe_pins>;
1021 + pinctrl-names = "default";
1022 + phy-handle = <&ext_rgmii_phy>;
1023 + phy-mode = "rgmii-id";
1024 + phy-supply = <®_vcc_3v3>;
1029 + pinctrl-0 = <&i2c2_pb0_pins>;
1030 + pinctrl-names = "default";
1033 + pcf8574a: gpio@38 {
1034 + compatible = "nxp,pcf8574a";
1036 + interrupt-parent = <&pio>;
1037 + interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
1038 + interrupt-controller;
1040 + #gpio-cells = <2>;
1041 + #interrupt-cells = <2>;
1050 + linux,code = <KEY_OK>;
1052 + voltage = <160000>;
1057 + ext_rgmii_phy: ethernet-phy@1 {
1058 + compatible = "ethernet-phy-ieee802.3-c22";
1065 + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
1067 + vmmc-supply = <®_vcc_3v3>;
1068 + vqmmc-supply = <®_vcc_3v3>;
1069 + pinctrl-0 = <&mmc0_pins>;
1070 + pinctrl-names = "default";
1076 + mmc-pwrseq = <&wifi_pwrseq>;
1078 + vmmc-supply = <®_vcc_3v3>;
1079 + vqmmc-supply = <®_vcc_3v3>;
1080 + pinctrl-0 = <&mmc1_pins>;
1081 + pinctrl-names = "default";
1098 + pinctrl-0 = <&uart0_pb8_pins>;
1099 + pinctrl-names = "default";
1105 + pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
1106 + pinctrl-names = "default";
1109 + /* XR829 bluetooth is connected here */
1118 + usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
1119 + usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
1120 + usb0_vbus-supply = <®_usbvbus>;
1121 + usb1_vbus-supply = <®_vcc>;
1125 +++ b/arch/riscv/dts/sun20i-d1.dtsi
1127 +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
1128 +// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
1130 +#include <dt-bindings/clock/sun6i-rtc.h>
1131 +#include <dt-bindings/clock/sun8i-de2.h>
1132 +#include <dt-bindings/clock/sun8i-tcon-top.h>
1133 +#include <dt-bindings/clock/sun20i-d1-ccu.h>
1134 +#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
1135 +#include <dt-bindings/interrupt-controller/irq.h>
1136 +#include <dt-bindings/reset/sun8i-de2.h>
1137 +#include <dt-bindings/reset/sun20i-d1-ccu.h>
1138 +#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
1139 +#include <dt-bindings/thermal/thermal.h>
1142 + #address-cells = <1>;
1143 + #size-cells = <1>;
1146 + timebase-frequency = <24000000>;
1147 + #address-cells = <1>;
1148 + #size-cells = <0>;
1151 + compatible = "thead,c906", "riscv";
1152 + device_type = "cpu";
1154 + clocks = <&ccu CLK_RISCV>;
1155 + clock-frequency = <24000000>;
1156 + d-cache-block-size = <64>;
1157 + d-cache-sets = <256>;
1158 + d-cache-size = <32768>;
1159 + i-cache-block-size = <64>;
1160 + i-cache-sets = <128>;
1161 + i-cache-size = <32768>;
1162 + mmu-type = "riscv,sv39";
1163 + riscv,isa = "rv64imafdc";
1164 + #cooling-cells = <2>;
1166 + cpu0_intc: interrupt-controller {
1167 + compatible = "riscv,cpu-intc";
1168 + interrupt-controller;
1169 + #address-cells = <0>;
1170 + #interrupt-cells = <1>;
1175 + de: display-engine {
1176 + compatible = "allwinner,sun20i-d1-display-engine";
1177 + allwinner,pipelines = <&mixer0>, <&mixer1>;
1178 + status = "disabled";
1181 + osc24M: osc24M-clk {
1182 + compatible = "fixed-clock";
1183 + clock-frequency = <24000000>;
1184 + clock-output-names = "osc24M";
1185 + #clock-cells = <0>;
1189 + compatible = "simple-bus";
1191 + interrupt-parent = <&plic>;
1193 + #address-cells = <1>;
1194 + #size-cells = <1>;
1196 + dsp_wdt: watchdog@1700400 {
1197 + compatible = "allwinner,sun20i-d1-wdt";
1198 + reg = <0x1700400 0x20>;
1199 + interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
1200 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
1201 + clock-names = "hosc", "losc";
1202 + status = "reserved";
1205 + pio: pinctrl@2000000 {
1206 + compatible = "allwinner,sun20i-d1-pinctrl";
1207 + reg = <0x2000000 0x800>;
1208 + interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
1209 + <87 IRQ_TYPE_LEVEL_HIGH>,
1210 + <89 IRQ_TYPE_LEVEL_HIGH>,
1211 + <91 IRQ_TYPE_LEVEL_HIGH>,
1212 + <93 IRQ_TYPE_LEVEL_HIGH>,
1213 + <95 IRQ_TYPE_LEVEL_HIGH>;
1214 + clocks = <&ccu CLK_APB0>,
1216 + <&rtc CLK_OSC32K>;
1217 + clock-names = "apb", "hosc", "losc";
1219 + interrupt-controller;
1220 + #gpio-cells = <3>;
1221 + #interrupt-cells = <3>;
1224 + i2c0_pb10_pins: i2c0-pb10-pins {
1225 + pins = "PB10", "PB11";
1226 + function = "i2c0";
1230 + i2c2_pb0_pins: i2c2-pb0-pins {
1231 + pins = "PB0", "PB1";
1232 + function = "i2c2";
1236 + lcd_rgb666_pins: lcd-rgb666-pins {
1237 + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
1238 + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
1239 + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
1240 + "PD18", "PD19", "PD20", "PD21";
1241 + function = "lcd0";
1245 + mmc0_pins: mmc0-pins {
1246 + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
1247 + function = "mmc0";
1251 + mmc1_pins: mmc1-pins {
1252 + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
1253 + function = "mmc1";
1257 + mmc2_pins: mmc2-pins {
1258 + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
1259 + function = "mmc2";
1263 + rgmii_pe_pins: rgmii-pe-pins {
1264 + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
1265 + "PE5", "PE6", "PE7", "PE8", "PE9",
1266 + "PE11", "PE12", "PE13", "PE14", "PE15";
1267 + function = "emac";
1271 + rmii_pe_pins: rmii-pe-pins {
1272 + pins = "PE0", "PE1", "PE2", "PE3", "PE4",
1273 + "PE5", "PE6", "PE7", "PE8", "PE9";
1274 + function = "emac";
1278 + uart0_pb8_pins: uart0-pb8-pins {
1279 + pins = "PB8", "PB9";
1280 + function = "uart0";
1284 + uart1_pg6_pins: uart1-pg6-pins {
1285 + pins = "PG6", "PG7";
1286 + function = "uart1";
1290 + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
1291 + pins = "PG8", "PG9";
1292 + function = "uart1";
1296 + ccu: clock-controller@2001000 {
1297 + compatible = "allwinner,sun20i-d1-ccu";
1298 + reg = <0x2001000 0x1000>;
1299 + clocks = <&osc24M>,
1300 + <&rtc CLK_OSC32K>,
1302 + clock-names = "hosc", "losc", "iosc";
1303 + #clock-cells = <1>;
1304 + #reset-cells = <1>;
1307 + lradc: keys@2009800 {
1308 + compatible = "allwinner,sun20i-d1-lradc",
1309 + "allwinner,sun50i-r329-lradc";
1310 + reg = <0x2009800 0x400>;
1311 + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
1312 + clocks = <&ccu CLK_BUS_LRADC>;
1313 + resets = <&ccu RST_BUS_LRADC>;
1314 + status = "disabled";
1317 + codec: audio-codec@2030000 {
1318 + compatible = "simple-mfd", "syscon";
1319 + reg = <0x2030000 0x1000>;
1320 + #address-cells = <1>;
1321 + #size-cells = <1>;
1323 + regulators@2030348 {
1324 + compatible = "allwinner,sun20i-d1-analog-ldos";
1325 + reg = <0x2030348 0x4>;
1326 + nvmem-cells = <&bg_trim>;
1327 + nvmem-cell-names = "bg_trim";
1332 + reg_hpldo: hpldo {
1337 + i2s0: i2s@2032000 {
1338 + compatible = "allwinner,sun20i-d1-i2s",
1339 + "allwinner,sun50i-r329-i2s";
1340 + reg = <0x2032000 0x1000>;
1341 + interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
1342 + clocks = <&ccu CLK_BUS_I2S0>,
1344 + clock-names = "apb", "mod";
1345 + resets = <&ccu RST_BUS_I2S0>;
1346 + dmas = <&dma 3>, <&dma 3>;
1347 + dma-names = "rx", "tx";
1348 + status = "disabled";
1349 + #sound-dai-cells = <0>;
1352 + i2s1: i2s@2033000 {
1353 + compatible = "allwinner,sun20i-d1-i2s",
1354 + "allwinner,sun50i-r329-i2s";
1355 + reg = <0x2033000 0x1000>;
1356 + interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
1357 + clocks = <&ccu CLK_BUS_I2S1>,
1359 + clock-names = "apb", "mod";
1360 + resets = <&ccu RST_BUS_I2S1>;
1361 + dmas = <&dma 4>, <&dma 4>;
1362 + dma-names = "rx", "tx";
1363 + status = "disabled";
1364 + #sound-dai-cells = <0>;
1367 + i2s2: i2s@2034000 {
1368 + compatible = "allwinner,sun20i-d1-i2s",
1369 + "allwinner,sun50i-r329-i2s";
1370 + reg = <0x2034000 0x1000>;
1371 + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
1372 + clocks = <&ccu CLK_BUS_I2S2>,
1374 + clock-names = "apb", "mod";
1375 + resets = <&ccu RST_BUS_I2S2>;
1376 + dmas = <&dma 5>, <&dma 5>;
1377 + dma-names = "rx", "tx";
1378 + status = "disabled";
1379 + #sound-dai-cells = <0>;
1382 + timer: timer@2050000 {
1383 + compatible = "allwinner,sun20i-d1-timer",
1384 + "allwinner,sun8i-a23-timer";
1385 + reg = <0x2050000 0xa0>;
1386 + interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
1387 + <76 IRQ_TYPE_LEVEL_HIGH>;
1388 + clocks = <&osc24M>;
1391 + wdt: watchdog@20500a0 {
1392 + compatible = "allwinner,sun20i-d1-wdt-reset",
1393 + "allwinner,sun20i-d1-wdt";
1394 + reg = <0x20500a0 0x20>;
1395 + interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
1396 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
1397 + clock-names = "hosc", "losc";
1398 + status = "reserved";
1401 + uart0: serial@2500000 {
1402 + compatible = "snps,dw-apb-uart";
1403 + reg = <0x2500000 0x400>;
1404 + reg-io-width = <4>;
1406 + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
1407 + clocks = <&ccu CLK_BUS_UART0>;
1408 + resets = <&ccu RST_BUS_UART0>;
1409 + dmas = <&dma 14>, <&dma 14>;
1410 + dma-names = "rx", "tx";
1411 + status = "disabled";
1414 + uart1: serial@2500400 {
1415 + compatible = "snps,dw-apb-uart";
1416 + reg = <0x2500400 0x400>;
1417 + reg-io-width = <4>;
1419 + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
1420 + clocks = <&ccu CLK_BUS_UART1>;
1421 + resets = <&ccu RST_BUS_UART1>;
1422 + dmas = <&dma 15>, <&dma 15>;
1423 + dma-names = "rx", "tx";
1424 + status = "disabled";
1427 + uart2: serial@2500800 {
1428 + compatible = "snps,dw-apb-uart";
1429 + reg = <0x2500800 0x400>;
1430 + reg-io-width = <4>;
1432 + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
1433 + clocks = <&ccu CLK_BUS_UART2>;
1434 + resets = <&ccu RST_BUS_UART2>;
1435 + dmas = <&dma 16>, <&dma 16>;
1436 + dma-names = "rx", "tx";
1437 + status = "disabled";
1440 + uart3: serial@2500c00 {
1441 + compatible = "snps,dw-apb-uart";
1442 + reg = <0x2500c00 0x400>;
1443 + reg-io-width = <4>;
1445 + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
1446 + clocks = <&ccu CLK_BUS_UART3>;
1447 + resets = <&ccu RST_BUS_UART3>;
1448 + dmas = <&dma 17>, <&dma 17>;
1449 + dma-names = "rx", "tx";
1450 + status = "disabled";
1453 + uart4: serial@2501000 {
1454 + compatible = "snps,dw-apb-uart";
1455 + reg = <0x2501000 0x400>;
1456 + reg-io-width = <4>;
1458 + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
1459 + clocks = <&ccu CLK_BUS_UART4>;
1460 + resets = <&ccu RST_BUS_UART4>;
1461 + dmas = <&dma 18>, <&dma 18>;
1462 + dma-names = "rx", "tx";
1463 + status = "disabled";
1466 + uart5: serial@2501400 {
1467 + compatible = "snps,dw-apb-uart";
1468 + reg = <0x2501400 0x400>;
1469 + reg-io-width = <4>;
1471 + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
1472 + clocks = <&ccu CLK_BUS_UART5>;
1473 + resets = <&ccu RST_BUS_UART5>;
1474 + dmas = <&dma 19>, <&dma 19>;
1475 + dma-names = "rx", "tx";
1476 + status = "disabled";
1479 + i2c0: i2c@2502000 {
1480 + compatible = "allwinner,sun20i-d1-i2c",
1481 + "allwinner,sun8i-v536-i2c",
1482 + "allwinner,sun6i-a31-i2c";
1483 + reg = <0x2502000 0x400>;
1484 + interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
1485 + clocks = <&ccu CLK_BUS_I2C0>;
1486 + resets = <&ccu RST_BUS_I2C0>;
1487 + dmas = <&dma 43>, <&dma 43>;
1488 + dma-names = "rx", "tx";
1489 + status = "disabled";
1490 + #address-cells = <1>;
1491 + #size-cells = <0>;
1494 + i2c1: i2c@2502400 {
1495 + compatible = "allwinner,sun20i-d1-i2c",
1496 + "allwinner,sun8i-v536-i2c",
1497 + "allwinner,sun6i-a31-i2c";
1498 + reg = <0x2502400 0x400>;
1499 + interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
1500 + clocks = <&ccu CLK_BUS_I2C1>;
1501 + resets = <&ccu RST_BUS_I2C1>;
1502 + dmas = <&dma 44>, <&dma 44>;
1503 + dma-names = "rx", "tx";
1504 + status = "disabled";
1505 + #address-cells = <1>;
1506 + #size-cells = <0>;
1509 + i2c2: i2c@2502800 {
1510 + compatible = "allwinner,sun20i-d1-i2c",
1511 + "allwinner,sun8i-v536-i2c",
1512 + "allwinner,sun6i-a31-i2c";
1513 + reg = <0x2502800 0x400>;
1514 + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
1515 + clocks = <&ccu CLK_BUS_I2C2>;
1516 + resets = <&ccu RST_BUS_I2C2>;
1517 + dmas = <&dma 45>, <&dma 45>;
1518 + dma-names = "rx", "tx";
1519 + status = "disabled";
1520 + #address-cells = <1>;
1521 + #size-cells = <0>;
1524 + i2c3: i2c@2502c00 {
1525 + compatible = "allwinner,sun20i-d1-i2c",
1526 + "allwinner,sun8i-v536-i2c",
1527 + "allwinner,sun6i-a31-i2c";
1528 + reg = <0x2502c00 0x400>;
1529 + interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
1530 + clocks = <&ccu CLK_BUS_I2C3>;
1531 + resets = <&ccu RST_BUS_I2C3>;
1532 + dmas = <&dma 46>, <&dma 46>;
1533 + dma-names = "rx", "tx";
1534 + status = "disabled";
1535 + #address-cells = <1>;
1536 + #size-cells = <0>;
1539 + syscon: syscon@3000000 {
1540 + compatible = "allwinner,sun20i-d1-system-control";
1541 + reg = <0x3000000 0x1000>;
1543 + #address-cells = <1>;
1544 + #size-cells = <1>;
1546 + regulators@3000150 {
1547 + compatible = "allwinner,sun20i-d1-system-ldos";
1548 + reg = <0x3000150 0x4>;
1558 + dma: dma-controller@3002000 {
1559 + compatible = "allwinner,sun20i-d1-dma";
1560 + reg = <0x3002000 0x1000>;
1561 + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
1562 + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
1563 + clock-names = "bus", "mbus";
1564 + resets = <&ccu RST_BUS_DMA>;
1565 + dma-channels = <16>;
1566 + dma-requests = <48>;
1570 + sid: efuse@3006000 {
1571 + compatible = "allwinner,sun20i-d1-sid";
1572 + reg = <0x3006000 0x1000>;
1573 + #address-cells = <1>;
1574 + #size-cells = <1>;
1576 + ths_calib: ths-calib@14 {
1580 + bg_trim: bg-trim@28 {
1586 + mbus: dram-controller@3102000 {
1587 + compatible = "allwinner,sun20i-d1-mbus";
1588 + reg = <0x3102000 0x1000>,
1589 + <0x3103000 0x1000>;
1590 + reg-names = "mbus", "dram";
1591 + interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
1592 + clocks = <&ccu CLK_MBUS>,
1594 + <&ccu CLK_BUS_DRAM>;
1595 + clock-names = "mbus", "dram", "bus";
1596 + dma-ranges = <0 0x40000000 0x80000000>;
1597 + #address-cells = <1>;
1598 + #size-cells = <1>;
1599 + #interconnect-cells = <1>;
1602 + mmc0: mmc@4020000 {
1603 + compatible = "allwinner,sun20i-d1-mmc";
1604 + reg = <0x4020000 0x1000>;
1605 + interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
1606 + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
1607 + clock-names = "ahb", "mmc";
1608 + resets = <&ccu RST_BUS_MMC0>;
1609 + reset-names = "ahb";
1611 + max-frequency = <150000000>;
1613 + status = "disabled";
1614 + #address-cells = <1>;
1615 + #size-cells = <0>;
1618 + mmc1: mmc@4021000 {
1619 + compatible = "allwinner,sun20i-d1-mmc";
1620 + reg = <0x4021000 0x1000>;
1621 + interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
1622 + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
1623 + clock-names = "ahb", "mmc";
1624 + resets = <&ccu RST_BUS_MMC1>;
1625 + reset-names = "ahb";
1627 + max-frequency = <150000000>;
1629 + status = "disabled";
1630 + #address-cells = <1>;
1631 + #size-cells = <0>;
1634 + mmc2: mmc@4022000 {
1635 + compatible = "allwinner,sun20i-d1-emmc",
1636 + "allwinner,sun50i-a100-emmc";
1637 + reg = <0x4022000 0x1000>;
1638 + interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
1639 + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
1640 + clock-names = "ahb", "mmc";
1641 + resets = <&ccu RST_BUS_MMC2>;
1642 + reset-names = "ahb";
1643 + cap-mmc-highspeed;
1644 + max-frequency = <150000000>;
1649 + status = "disabled";
1650 + #address-cells = <1>;
1651 + #size-cells = <0>;
1654 + usb_otg: usb@4100000 {
1655 + compatible = "allwinner,sun20i-d1-musb",
1656 + "allwinner,sun8i-a33-musb";
1657 + reg = <0x4100000 0x400>;
1658 + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
1659 + interrupt-names = "mc";
1660 + clocks = <&ccu CLK_BUS_OTG>;
1661 + resets = <&ccu RST_BUS_OTG>;
1662 + extcon = <&usbphy 0>;
1663 + phys = <&usbphy 0>;
1664 + phy-names = "usb";
1665 + status = "disabled";
1668 + usbphy: phy@4100400 {
1669 + compatible = "allwinner,sun20i-d1-usb-phy";
1670 + reg = <0x4100400 0x100>,
1671 + <0x4101800 0x100>,
1672 + <0x4200800 0x100>;
1673 + reg-names = "phy_ctrl",
1676 + clocks = <&osc24M>,
1678 + clock-names = "usb0_phy",
1680 + resets = <&ccu RST_USB_PHY0>,
1681 + <&ccu RST_USB_PHY1>;
1682 + reset-names = "usb0_reset",
1684 + status = "disabled";
1688 + ehci0: usb@4101000 {
1689 + compatible = "allwinner,sun20i-d1-ehci",
1691 + reg = <0x4101000 0x100>;
1692 + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
1693 + clocks = <&ccu CLK_BUS_OHCI0>,
1694 + <&ccu CLK_BUS_EHCI0>,
1695 + <&ccu CLK_USB_OHCI0>;
1696 + resets = <&ccu RST_BUS_OHCI0>,
1697 + <&ccu RST_BUS_EHCI0>;
1698 + phys = <&usbphy 0>;
1699 + phy-names = "usb";
1700 + status = "disabled";
1703 + ohci0: usb@4101400 {
1704 + compatible = "allwinner,sun20i-d1-ohci",
1706 + reg = <0x4101400 0x100>;
1707 + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
1708 + clocks = <&ccu CLK_BUS_OHCI0>,
1709 + <&ccu CLK_USB_OHCI0>;
1710 + resets = <&ccu RST_BUS_OHCI0>;
1711 + phys = <&usbphy 0>;
1712 + phy-names = "usb";
1713 + status = "disabled";
1716 + ehci1: usb@4200000 {
1717 + compatible = "allwinner,sun20i-d1-ehci",
1719 + reg = <0x4200000 0x100>;
1720 + interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
1721 + clocks = <&ccu CLK_BUS_OHCI1>,
1722 + <&ccu CLK_BUS_EHCI1>,
1723 + <&ccu CLK_USB_OHCI1>;
1724 + resets = <&ccu RST_BUS_OHCI1>,
1725 + <&ccu RST_BUS_EHCI1>;
1726 + phys = <&usbphy 1>;
1727 + phy-names = "usb";
1728 + status = "disabled";
1731 + ohci1: usb@4200400 {
1732 + compatible = "allwinner,sun20i-d1-ohci",
1734 + reg = <0x4200400 0x100>;
1735 + interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
1736 + clocks = <&ccu CLK_BUS_OHCI1>,
1737 + <&ccu CLK_USB_OHCI1>;
1738 + resets = <&ccu RST_BUS_OHCI1>;
1739 + phys = <&usbphy 1>;
1740 + phy-names = "usb";
1741 + status = "disabled";
1744 + emac: ethernet@4500000 {
1745 + compatible = "allwinner,sun20i-d1-emac",
1746 + "allwinner,sun50i-a64-emac";
1747 + reg = <0x4500000 0x10000>;
1748 + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
1749 + interrupt-names = "macirq";
1750 + clocks = <&ccu CLK_BUS_EMAC>;
1751 + clock-names = "stmmaceth";
1752 + resets = <&ccu RST_BUS_EMAC>;
1753 + reset-names = "stmmaceth";
1754 + syscon = <&syscon>;
1755 + status = "disabled";
1758 + compatible = "snps,dwmac-mdio";
1759 + #address-cells = <1>;
1760 + #size-cells = <0>;
1764 + display_clocks: clock-controller@5000000 {
1765 + compatible = "allwinner,sun20i-d1-de2-clk",
1766 + "allwinner,sun50i-h5-de2-clk";
1767 + reg = <0x5000000 0x10000>;
1768 + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
1769 + clock-names = "bus", "mod";
1770 + resets = <&ccu RST_BUS_DE>;
1771 + #clock-cells = <1>;
1772 + #reset-cells = <1>;
1775 + mixer0: mixer@5100000 {
1776 + compatible = "allwinner,sun20i-d1-de2-mixer-0";
1777 + reg = <0x5100000 0x100000>;
1778 + clocks = <&display_clocks CLK_BUS_MIXER0>,
1779 + <&display_clocks CLK_MIXER0>;
1780 + clock-names = "bus", "mod";
1781 + resets = <&display_clocks RST_MIXER0>;
1784 + #address-cells = <1>;
1785 + #size-cells = <0>;
1787 + mixer0_out: port@1 {
1790 + mixer0_out_tcon_top_mixer0: endpoint {
1791 + remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
1797 + mixer1: mixer@5200000 {
1798 + compatible = "allwinner,sun20i-d1-de2-mixer-1";
1799 + reg = <0x5200000 0x100000>;
1800 + clocks = <&display_clocks CLK_BUS_MIXER1>,
1801 + <&display_clocks CLK_MIXER1>;
1802 + clock-names = "bus", "mod";
1803 + resets = <&display_clocks RST_MIXER1>;
1806 + #address-cells = <1>;
1807 + #size-cells = <0>;
1809 + mixer1_out: port@1 {
1812 + mixer1_out_tcon_top_mixer1: endpoint {
1813 + remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
1819 + tcon_top: tcon-top@5460000 {
1820 + compatible = "allwinner,sun20i-d1-tcon-top";
1821 + reg = <0x5460000 0x1000>;
1822 + clocks = <&ccu CLK_BUS_DPSS_TOP>,
1823 + <&ccu CLK_TCON_TV>,
1825 + <&ccu CLK_TCON_LCD0>;
1826 + clock-names = "bus", "tcon-tv0", "tve0", "dsi";
1827 + clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
1828 + resets = <&ccu RST_BUS_DPSS_TOP>;
1829 + #clock-cells = <1>;
1832 + #address-cells = <1>;
1833 + #size-cells = <0>;
1835 + tcon_top_mixer0_in: port@0 {
1837 + #address-cells = <1>;
1838 + #size-cells = <0>;
1840 + tcon_top_mixer0_in_mixer0: endpoint@0 {
1842 + remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
1846 + tcon_top_mixer0_out: port@1 {
1848 + #address-cells = <1>;
1849 + #size-cells = <0>;
1851 + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
1853 + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
1856 + tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
1858 + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
1862 + tcon_top_mixer1_in: port@2 {
1864 + #address-cells = <1>;
1865 + #size-cells = <0>;
1867 + tcon_top_mixer1_in_mixer1: endpoint@1 {
1869 + remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
1873 + tcon_top_mixer1_out: port@3 {
1875 + #address-cells = <1>;
1876 + #size-cells = <0>;
1878 + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
1880 + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
1883 + tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
1885 + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
1889 + tcon_top_hdmi_in: port@4 {
1892 + tcon_top_hdmi_in_tcon_tv0: endpoint {
1893 + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
1897 + tcon_top_hdmi_out: port@5 {
1903 + tcon_lcd0: lcd-controller@5461000 {
1904 + compatible = "allwinner,sun20i-d1-tcon-lcd";
1905 + reg = <0x5461000 0x1000>;
1906 + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
1907 + clocks = <&ccu CLK_BUS_TCON_LCD0>,
1908 + <&ccu CLK_TCON_LCD0>;
1909 + clock-names = "ahb", "tcon-ch0";
1910 + clock-output-names = "tcon-pixel-clock";
1911 + resets = <&ccu RST_BUS_TCON_LCD0>,
1912 + <&ccu RST_BUS_LVDS0>;
1913 + reset-names = "lcd", "lvds";
1914 + #clock-cells = <0>;
1917 + #address-cells = <1>;
1918 + #size-cells = <0>;
1920 + tcon_lcd0_in: port@0 {
1922 + #address-cells = <1>;
1923 + #size-cells = <0>;
1925 + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
1927 + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
1930 + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
1932 + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
1936 + tcon_lcd0_out: port@1 {
1942 + tcon_tv0: lcd-controller@5470000 {
1943 + compatible = "allwinner,sun20i-d1-tcon-tv";
1944 + reg = <0x5470000 0x1000>;
1945 + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
1946 + clocks = <&ccu CLK_BUS_TCON_TV>,
1947 + <&tcon_top CLK_TCON_TOP_TV0>;
1948 + clock-names = "ahb", "tcon-ch1";
1949 + resets = <&ccu RST_BUS_TCON_TV>;
1950 + reset-names = "lcd";
1953 + #address-cells = <1>;
1954 + #size-cells = <0>;
1956 + tcon_tv0_in: port@0 {
1958 + #address-cells = <1>;
1959 + #size-cells = <0>;
1961 + tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
1963 + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
1966 + tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
1968 + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
1972 + tcon_tv0_out: port@1 {
1975 + tcon_tv0_out_tcon_top_hdmi: endpoint {
1976 + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
1982 + riscv_wdt: watchdog@6011000 {
1983 + compatible = "allwinner,sun20i-d1-wdt";
1984 + reg = <0x6011000 0x20>;
1985 + interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
1986 + clocks = <&osc24M>, <&rtc CLK_OSC32K>;
1987 + clock-names = "hosc", "losc";
1990 + r_ccu: clock-controller@7010000 {
1991 + compatible = "allwinner,sun20i-d1-r-ccu";
1992 + reg = <0x7010000 0x400>;
1993 + clocks = <&osc24M>,
1994 + <&rtc CLK_OSC32K>,
1996 + <&ccu CLK_PLL_PERIPH0_DIV3>;
1997 + clock-names = "hosc", "losc", "iosc", "pll-periph";
1998 + #clock-cells = <1>;
1999 + #reset-cells = <1>;
2002 + rtc: rtc@7090000 {
2003 + compatible = "allwinner,sun20i-d1-rtc",
2004 + "allwinner,sun50i-r329-rtc";
2005 + reg = <0x7090000 0x400>;
2006 + interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
2007 + clocks = <&r_ccu CLK_BUS_R_RTC>,
2009 + <&r_ccu CLK_R_AHB>;
2010 + clock-names = "bus", "hosc", "ahb";
2011 + #clock-cells = <1>;
2014 + plic: interrupt-controller@10000000 {
2015 + compatible = "allwinner,sun20i-d1-plic",
2016 + "thead,c900-plic";
2017 + reg = <0x10000000 0x4000000>;
2018 + interrupts-extended = <&cpu0_intc 11>,
2020 + interrupt-controller;
2021 + riscv,ndev = <176>;
2022 + #address-cells = <0>;
2023 + #interrupt-cells = <2>;
2028 +++ b/arch/riscv/dts/sunxi-u-boot.dtsi
2030 +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2032 +#include "binman.dtsi"
2045 + u-boot-sunxi-with-spl {
2046 + filename = "u-boot-sunxi-with-spl.bin";
2047 + pad-byte = <0xff>;
2050 + filename = "spl/sunxi-spl.bin";
2054 + filename = "u-boot.itb";
2099 +++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h
2101 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2103 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
2106 +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
2107 +#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
2109 +#define CLK_R_AHB 0
2111 +#define CLK_BUS_R_TIMER 2
2112 +#define CLK_BUS_R_TWD 3
2113 +#define CLK_BUS_R_PPU 4
2114 +#define CLK_R_IR_RX 5
2115 +#define CLK_BUS_R_IR_RX 6
2116 +#define CLK_BUS_R_RTC 7
2117 +#define CLK_BUS_R_CPUCFG 8
2119 +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
2121 +++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h
2123 +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2125 + * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
2128 +#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
2129 +#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_
2131 +#define RST_BUS_R_TIMER 0
2132 +#define RST_BUS_R_TWD 1
2133 +#define RST_BUS_R_PPU 2
2134 +#define RST_BUS_R_IR_RX 3
2135 +#define RST_BUS_R_RTC 4
2136 +#define RST_BUS_R_CPUCFG 5
2138 +#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */