1 --- a/arch/arm/mach-kirkwood/Kconfig
2 +++ b/arch/arm/mach-kirkwood/Kconfig
3 @@ -62,6 +62,9 @@ config TARGET_NSA310
8 + bool "Zyxel NSA325 board"
13 @@ -85,5 +88,6 @@ source "board/Seagate/goflexhome/Kconfig
14 source "board/Seagate/nas220/Kconfig"
15 source "board/zyxel/nsa310/Kconfig"
16 source "board/zyxel/nsa310s/Kconfig"
17 +source "board/zyxel/nsa325/Kconfig"
21 +++ b/board/zyxel/nsa325/Kconfig
31 +config SYS_CONFIG_NAME
36 +++ b/board/zyxel/nsa325/MAINTAINERS
39 +M: Alberto Bursi <alberto.bursi@outlook.it>
41 +F: board/zyxel/nsa325/
42 +F: include/configs/nsa325.h
43 +F: configs/nsa325_defconfig
45 +++ b/board/zyxel/nsa325/Makefile
48 +# (C) Copyright 2015 bodhi <mibodhi@gmail.com>
52 +# Marvell Semiconductor <www.marvell.com>
53 +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
55 +# SPDX-License-Identifier: GPL-2.0+
61 +++ b/board/zyxel/nsa325/kwbimage.cfg
63 +# Copyright (C) 2015 bodhi <mibodhi@gmail.com>
65 +# Extracted from Zyxel GPL source for u-boot-1.1.4_NSA325v2
67 +# See file CREDITS for list of people who contributed to this
70 +# This program is free software; you can redistribute it and/or
71 +# modify it under the terms of the GNU General Public License as
72 +# published by the Free Software Foundation; either version 2 of
73 +# the License, or (at your option) any later version.
75 +# This program is distributed in the hope that it will be useful,
76 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
77 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
78 +# GNU General Public License for more details.
80 +# You should have received a copy of the GNU General Public License
81 +# along with this program; if not, write to the Free Software
82 +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
85 +# Refer docs/README.kwimage for more details about how-to configure
86 +# and create kirkwood boot image
89 +# Boot Media configurations
92 +NAND_ECC_MODE default
93 +NAND_PAGE_SIZE 0x0800
95 +# SOC registers configuration using bootrom header extension
96 +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
98 +# Configure RGMII-0 interface pad voltage to 1.8V
99 +DATA 0xFFD100e0 0x1b1b1b9b
102 +DATA 0xFFD01400 0x4301503E # DDR Configuration register
103 +DATA 0xFFD01404 0xB9843000 # DDR Controller Control Low
104 +DATA 0xFFD01408 0x33137777 # DDR Timing (Low)
105 +DATA 0xFFD0140C 0x16000C55 # DDR Timing (High)
106 +DATA 0xFFD01410 0x04000000 # DDR Address Control
107 +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
108 +DATA 0xFFD01418 0x00000000 # DDR Operation
109 +DATA 0xFFD0141C 0x00000672 # DDR Mode
110 +DATA 0xFFD01420 0x00000004 # DDR Extended Mode
111 +DATA 0xFFD01424 0x0000F14F # DDR Controller Control High
112 +DATA 0xFFD01428 0x000D6720 # DDR3 ODT Read Timing
113 +DATA 0xFFD0147C 0x0000B571 # DDR2 ODT Write Timing
114 +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size
115 +DATA 0xFFD01508 0x20000000 # CS[1]n Base address to 512Mb
116 +DATA 0xFFD0150C 0x1FFFFFF4 # CS[1]n Size 512Mb Window enabled for CS1
117 +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
118 +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
119 +DATA 0xFFD01494 0x00120000 # DDR ODT Control (Low)
120 +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
121 +DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
123 +DATA 0xFFD015D0 0x00000630
124 +DATA 0xFFD015D4 0x00000046
125 +DATA 0xFFD015D8 0x00000008
126 +DATA 0xFFD015DC 0x00000000
127 +DATA 0xFFD015E0 0x00000023
128 +DATA 0xFFD015E4 0x00203C18
129 +DATA 0xFFD01620 0x00384800
130 +DATA 0xFFD01480 0x00000001
131 +DATA 0xFFD20134 0x66666666
132 +DATA 0xFFD20138 0x00066666
134 +#Disable nsa325 hardware watchdog to allow successful kwbooting
135 +DATA 0xFFD10100 0x00004000 # set GPIO 14 to high to disable the watchdog
136 +DATA 0xFFD10104 0xFFFFBFFF # set GPIO 14 to output (to block any other input to it)
138 +# End of Header extension
142 +++ b/board/zyxel/nsa325/nsa325.c
145 + * Copyright (C) 2015 bodhi <mibodhi@gmail.com>
148 + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
150 + * Based on nsa320.c originall written by
151 + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
153 + * Based on guruplug.c originally written by
154 + * Siddarth Gore <gores@marvell.com>
155 + * (C) Copyright 2009
156 + * Marvell Semiconductor <www.marvell.com>
158 + * See file CREDITS for list of people who contributed to this
161 + * This program is free software; you can redistribute it and/or
162 + * modify it under the terms of the GNU General Public License as
163 + * published by the Free Software Foundation; either version 2 of
164 + * the License, or (at your option) any later version.
166 + * This program is distributed in the hope that it will be useful,
167 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
168 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
169 + * GNU General Public License for more details.
171 + * You should have received a copy of the GNU General Public License
172 + * along with this program; if not, write to the Free Software
173 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
174 + * MA 02110-1301 USA
179 +#include <asm/arch/soc.h>
180 +#include <asm/arch/mpp.h>
181 +#include <asm/arch/cpu.h>
182 +#include <asm/gpio.h>
185 +#include <asm/arch/gpio.h>
187 +DECLARE_GLOBAL_DATA_PTR;
189 +int board_early_init_f(void)
192 + * default gpio configuration
193 + * There are maximum 64 gpios controlled through 2 sets of registers
194 + * the below configuration configures mainly initial LED status
196 + mvebu_config_gpio(NSA325_VAL_LOW, NSA325_VAL_HIGH,
197 + NSA325_OE_LOW, NSA325_OE_HIGH);
199 + /* Multi-Purpose Pins Functionality configuration */
200 + /* (all LEDs & power off active high) */
201 + u32 kwmpp_config[] = {
210 + MPP8_TW_SDA, /* PCF8563 RTC chip */
211 + MPP9_TW_SCK, /* connected to TWSI */
214 + MPP12_GPO, /* HDD2 LED (green) */
215 + MPP13_GPIO, /* HDD2 LED (red) */
216 + MPP14_GPIO, /* MCU DATA pin (in) */
217 + MPP15_GPIO, /* USB LED (green) */
218 + MPP16_GPIO, /* MCU CLK pin (out) */
219 + MPP17_GPIO, /* MCU ACT pin (out) */
223 + MPP21_GPIO, /* USB power */
230 + MPP28_GPIO, /* SYS LED (green) */
231 + MPP29_GPIO, /* SYS LED (orange) */
238 + MPP36_GPIO, /* reset button */
239 + MPP37_GPIO, /* copy button */
240 + MPP38_GPIO, /* VID B0 */
241 + MPP39_GPIO, /* COPY LED (green) */
242 + MPP40_GPIO, /* COPY LED (red) */
243 + MPP41_GPIO, /* HDD1 LED (green) */
244 + MPP42_GPIO, /* HDD1 LED (red) */
245 + MPP43_GPIO, /* HTP pin */
246 + MPP44_GPIO, /* buzzer */
247 + MPP45_GPIO, /* VID B1 */
248 + MPP46_GPIO, /* power button */
249 + MPP47_GPIO, /* HDD2 power */
250 + MPP48_GPIO, /* power off */
253 + kirkwood_mpp_conf(kwmpp_config, NULL);
257 +int board_init(void)
260 + /* address of boot parameters */
261 + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
263 + /* This disables the hardware watchdog in the mcu on this board. */
264 + kw_gpio_set_valid(14, 1);
265 + kw_gpio_direction_output(14, 0);
266 + kw_gpio_set_value(14, 1);
271 +#ifdef CONFIG_RESET_PHY_R
272 +/* Configure and enable MV88E1318 PHY */
273 +void reset_phy(void)
277 + char *name = "egiga0";
279 + if (miiphy_set_current_dev(name))
282 + /* command to read PHY dev address */
283 + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
284 + printf("Err..%s could not read PHY dev address\n",
289 + /* Set RGMII delay */
290 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
291 + miiphy_read(name, devadr, MV88E1318_MAC_CTRL_REG, ®);
292 + reg |= (MV88E1318_RGMII_RXTM_CTRL | MV88E1318_RGMII_TXTM_CTRL);
293 + miiphy_write(name, devadr, MV88E1318_MAC_CTRL_REG, reg);
294 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
296 + /* reset the phy */
297 + miiphy_reset(name, devadr);
299 + /* The ZyXEL NSA325 uses the 88E1310S Alaska (interface identical to 88E1318) */
300 + /* and has an MCU attached to the LED[2] via tristate interrupt */
303 + /* switch to LED register page */
304 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, MV88E1318_LED_PG);
305 + /* read out LED polarity register */
306 + miiphy_read(name, devadr, MV88E1318_LED_POL_REG, ®);
307 + /* clear 4, set 5 - LED2 low, tri-state */
308 + reg &= ~(MV88E1318_LED2_4);
309 + reg |= (MV88E1318_LED2_5);
310 + /* write back LED polarity register */
311 + miiphy_write(name, devadr, MV88E1318_LED_POL_REG, reg);
312 + /* jump back to page 0, per the PHY chip documenation. */
313 + miiphy_write(name, devadr, MV88E1318_PGADR_REG, 0);
315 + /* Set the phy back to auto-negotiation mode. Onboard mcu sets it as 10Mbits/s on poweroff for WoL function */
316 + miiphy_write(name, devadr, 0x4, 0x1e1);
317 + miiphy_write(name, devadr, 0x9, 0x300);
319 + miiphy_write(name, devadr, 0x10, 0x3860);
320 + miiphy_write(name, devadr, 0x0, 0x9140);
322 + printf("MV88E1318 PHY initialized on %s\n", name);
325 +#endif /* CONFIG_RESET_PHY_R */
327 +#ifdef CONFIG_SHOW_BOOT_PROGRESS
328 +void show_boot_progress(int val)
330 + struct kwgpio_registers *gpio0 = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
331 + u32 dout0 = readl(&gpio0->dout);
332 + u32 blen0 = readl(&gpio0->blink_en);
334 + struct kwgpio_registers *gpio1 = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
335 + u32 dout1 = readl(&gpio1->dout);
336 + u32 blen1 = readl(&gpio1->blink_en);
339 + case BOOTSTAGE_ID_DECOMP_IMAGE:
340 + writel(blen0 & ~(SYS_GREEN_LED | SYS_ORANGE_LED), &gpio0->blink_en);
341 + writel((dout0 & ~SYS_GREEN_LED) | SYS_ORANGE_LED, &gpio0->dout);
343 + case BOOTSTAGE_ID_RUN_OS:
344 + writel(dout0 & ~SYS_ORANGE_LED, &gpio0->dout);
345 + writel(blen0 | SYS_GREEN_LED, &gpio0->blink_en);
347 + case BOOTSTAGE_ID_NET_START:
348 + writel(dout1 & ~COPY_RED_LED, &gpio1->dout);
349 + writel((blen1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->blink_en);
351 + case BOOTSTAGE_ID_NET_LOADED:
352 + writel(blen1 & ~(COPY_RED_LED | COPY_GREEN_LED), &gpio1->blink_en);
353 + writel((dout1 & ~COPY_RED_LED) | COPY_GREEN_LED, &gpio1->dout);
355 + case -BOOTSTAGE_ID_NET_NETLOOP_OK:
356 + case -BOOTSTAGE_ID_NET_LOADED:
357 + writel(dout1 & ~COPY_GREEN_LED, &gpio1->dout);
358 + writel((blen1 & ~COPY_GREEN_LED) | COPY_RED_LED, &gpio1->blink_en);
363 + printf("Error occured, error code = %d\n", -val);
364 + writel(dout0 & ~SYS_GREEN_LED, &gpio0->dout);
365 + writel(blen0 | SYS_ORANGE_LED, &gpio0->blink_en);
372 +#if defined(CONFIG_KIRKWOOD_GPIO)
373 +/* Return GPIO button status */
376 + gpio-36 (Reset Button ) in hi (act lo) - IRQ edge (clear )
377 + gpio-37 (Copy Button ) in hi (act lo) - IRQ edge (clear )
378 + gpio-46 (Power Button ) in lo (act hi) - IRQ edge (clear )
380 + gpio-36 (Reset Button ) in lo (act hi) - IRQ edge (clear )
381 + gpio-37 (Copy Button ) in lo (act hi) - IRQ edge (clear )
382 + gpio-46 (Power Button ) in hi (act lo) - IRQ edge (clear )
386 +do_read_button(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
388 + if (strcmp(argv[1], "power") == 0) {
389 + kw_gpio_set_valid(BTN_POWER, GPIO_INPUT_OK);
390 + kw_gpio_direction_input(BTN_POWER);
391 + return !kw_gpio_get_value(BTN_POWER);
393 + else if (strcmp(argv[1], "reset") == 0)
394 + return kw_gpio_get_value(BTN_RESET);
395 + else if (strcmp(argv[1], "copy") == 0)
396 + return kw_gpio_get_value(BTN_COPY);
402 +U_BOOT_CMD(button, 2, 0, do_read_button,
403 + "Return GPIO button status 0=off 1=on",
404 + "- button power|reset|copy: test buttons states\n"
410 +++ b/board/zyxel/nsa325/nsa325.h
413 + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
415 + * Based on nsa320.h originall written by
416 + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
418 + * Based on guruplug.h originally written by
419 + * Siddarth Gore <gores@marvell.com>
420 + * (C) Copyright 2009
421 + * Marvell Semiconductor <www.marvell.com>
423 + * See file CREDITS for list of people who contributed to this
426 + * This program is free software; you can redistribute it and/or
427 + * modify it under the terms of the GNU General Public License as
428 + * published by the Free Software Foundation; either version 2 of
429 + * the License, or (at your option) any later version.
431 + * This program is distributed in the hope that it will be useful,
432 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
433 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
434 + * GNU General Public License for more details.
436 + * You should have received a copy of the GNU General Public License
437 + * along with this program; if not, write to the Free Software
438 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
439 + * MA 02110-1301 USA
446 +#define HDD2_GREEN_LED (1 << 12)
447 +#define HDD2_RED_LED (1 << 13)
448 +#define USB_GREEN_LED (1 << 15)
449 +#define USB_POWER (1 << 21)
450 +#define SYS_GREEN_LED (1 << 28)
451 +#define SYS_ORANGE_LED (1 << 29)
453 +#define PIN_USB_GREEN_LED 15
454 +#define PIN_USB_POWER 21
456 +#define NSA325_OE_LOW (~(HDD2_GREEN_LED | HDD2_RED_LED | \
457 + USB_GREEN_LED | USB_POWER | \
458 + SYS_GREEN_LED | SYS_ORANGE_LED))
459 +#define NSA325_VAL_LOW (SYS_GREEN_LED | USB_POWER)
462 +#define COPY_GREEN_LED (1 << 7)
463 +#define COPY_RED_LED (1 << 8)
464 +#define HDD1_GREEN_LED (1 << 9)
465 +#define HDD1_RED_LED (1 << 10)
466 +#define HDD2_POWER (1 << 15)
467 +#define WATCHDOG_SIGNAL (1 << 14)
469 +#define NSA325_OE_HIGH (~(COPY_GREEN_LED | COPY_RED_LED | \
470 + HDD1_GREEN_LED | HDD1_RED_LED | HDD2_POWER | WATCHDOG_SIGNAL ))
471 +#define NSA325_VAL_HIGH (WATCHDOG_SIGNAL | HDD2_POWER)
474 +#define MV88E1318_PGADR_REG 22
475 +#define MV88E1318_MAC_CTRL_PG 2
476 +#define MV88E1318_MAC_CTRL_REG 21
477 +#define MV88E1318_RGMII_TXTM_CTRL (1 << 4)
478 +#define MV88E1318_RGMII_RXTM_CTRL (1 << 5)
479 +#define MV88E1318_LED_PG 3
480 +#define MV88E1318_LED_POL_REG 17
481 +#define MV88E1318_LED2_4 (1 << 4)
482 +#define MV88E1318_LED2_5 (1 << 5)
484 +#define BTN_POWER 46
485 +#define BTN_RESET 36
488 +#endif /* __NSA325_H */
490 +++ b/configs/nsa325_defconfig
494 +CONFIG_SYS_TEXT_BASE=0x600000
495 +CONFIG_TARGET_NSA325=y
496 +CONFIG_IDENT_STRING="\nZyXEL NSA325 2-Bay Power Media Server"
498 +CONFIG_SYS_PROMPT="NSA325> "
499 +# CONFIG_CMD_IMLS is not set
500 +# CONFIG_CMD_FLASH is not set
501 +CONFIG_SYS_NS16550=y
504 +CONFIG_CMD_SETEXPR=y
517 +CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x0c0000(uboot),0x80000(uboot_env),0x7ec0000(ubi)"
518 +CONFIG_CMD_MTDPARTS=y
521 +CONFIG_EFI_PARTITION=y
522 +CONFIG_ENV_IS_IN_NAND=y
524 +CONFIG_USB_EHCI_HCD=y
525 +CONFIG_USB_STORAGE=y
528 +CONFIG_SYS_LONGHELP=y
530 +++ b/include/configs/nsa325.h
533 + * (C) Copyright 2016 bodhi <mibodhi@gmail.com>
536 + * Copyright (C) 2014 Jason Plum <jplum@archlinuxarm.org>
538 + * Copyright (C) 2012 Peter Schildmann <linux@schildmann.info>
540 + * Based on guruplug.h originally written by
541 + * Siddarth Gore <gores@marvell.com>
542 + * (C) Copyright 2009
543 + * Marvell Semiconductor <www.marvell.com>
545 + * See file CREDITS for list of people who contributed to this
548 + * This program is free software; you can redistribute it and/or
549 + * modify it under the terms of the GNU General Public License as
550 + * published by the Free Software Foundation; either version 2 of
551 + * the License, or (at your option) any later version.
553 + * This program is distributed in the hope that it will be useful,
554 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
555 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
556 + * GNU General Public License for more details.
558 + * You should have received a copy of the GNU General Public License
559 + * along with this program; if not, write to the Free Software
560 + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
561 + * MA 02110-1301 USA
564 +#ifndef _CONFIG_NSA325_H
565 +#define _CONFIG_NSA325_H
568 + * High Level Configuration Options (easy to change)
570 +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
571 +#define CONFIG_KW88F6281 1 /* SOC Name */
573 +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
576 + * Misc Configuration Options
578 +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progess display (LED's) */
581 + * Commands configuration
583 +#define CONFIG_PREBOOT
586 + * mv-common.h should be defined after CMD configs since it used them
587 + * to enable certain macros
589 +#include "mv-common.h"
592 + * Environment variables configurations
594 +#ifdef CONFIG_CMD_NAND
595 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
598 + * max 4k env size is enough, but in case of nand
599 + * it has to be rounded to sector size
601 +#define CONFIG_ENV_SIZE 0x20000 /* 128k */
602 +#define CONFIG_ENV_ADDR 0xc0000
603 +#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here */
606 + * Default environment variables
608 +#define CONFIG_BOOTCOMMAND \
610 + "ubi read 0x800000 kernel; " \
613 +#define CONFIG_EXTRA_ENV_SETTINGS \
614 + "console=console=ttyS0,115200\0" \
615 + "mtdids=nand0=orion_nand\0" \
616 + "mtdparts="CONFIG_MTDPARTS_DEFAULT \
620 + * Ethernet Driver configuration
622 +#ifdef CONFIG_CMD_NET
623 +#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
624 +#define CONFIG_PHY_BASE_ADR 0x1
625 +#define CONFIG_NETCONSOLE
626 +#endif /* CONFIG_CMD_NET */
629 + * SATA Driver configuration
631 +#ifdef CONFIG_MVSATA_IDE
632 +#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
633 +#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
634 +#endif /* CONFIG_MVSATA_IDE */
639 +#define CONFIG_JFFS2_NAND
640 +#define CONFIG_JFFS2_LZO
641 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
642 +#define CONFIG_MTD_PARTITIONS
647 +#ifdef CONFIG_CMD_DATE
648 +#define CONFIG_RTC_MV
649 +#endif /* CONFIG_CMD_DATE */
651 +#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
653 +#endif /* _CONFIG_NSA325_H */