1 From e2c59cedebf72e4a002134a2932f722b508a5448 Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Wed, 29 Aug 2012 22:08:15 +0200
4 Subject: net: switchlib: add driver for Lantiq PSB697X switch family
6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8 --- a/drivers/net/switch/Makefile
9 +++ b/drivers/net/switch/Makefile
10 @@ -10,6 +10,7 @@ include $(TOPDIR)/config.mk
11 LIB := $(obj)libswitch.o
13 COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
14 +COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
17 SRCS := $(COBJS:.o=.c)
19 +++ b/drivers/net/switch/psb697x.c
22 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
24 + * SPDX-License-Identifier: GPL-2.0+
32 +#define PSB697X_CHIPID1 0x2599
33 +#define PSB697X_PORT_COUNT 7
35 +#define PSB697X_PORT_BASE(p) (p * 0x20)
36 +#define PSB697X_REG_PS(p) (PSB697X_PORT_BASE(p) + 0x00)
37 +#define PSB697X_REG_PBC(p) (PSB697X_PORT_BASE(p) + 0x01)
38 +#define PSB697X_REG_PEC(p) (PSB697X_PORT_BASE(p) + 0x02)
40 +#define PSB697X_REG_SGC1 0x0E0 /* Switch Global Control Register 1 */
41 +#define PSB697X_REG_SGC2 0x0E1 /* Switch Global Control Register 2 */
42 +#define PSB697X_REG_CMH 0x0E2 /* CPU Port & Mirror Control */
43 +#define PSB697X_REG_MIICR 0x0F5 /* MII Port Control */
44 +#define PSB697X_REG_CI0 0x100 /* Chip Identifier 0 */
45 +#define PSB697X_REG_CI1 0x101 /* Chip Identifier 1 */
46 +#define PSB697X_REG_MIIAC 0x120 /* MII Indirect Access Control */
47 +#define PSB697X_REG_MIIWD 0x121 /* MII Indirect Write Data */
48 +#define PSB697X_REG_MIIRD 0x122 /* MII Indirect Read Data */
50 +#define PSB697X_REG_PORT_FLP (1 << 2) /* Force link up */
51 +#define PSB697X_REG_PORT_FLD (1 << 1) /* Force link down */
53 +#define PSB697X_REG_SGC2_SE (1 << 15) /* Switch enable */
55 +#define PSB697X_REG_CMH_CPN_MASK 0x7
56 +#define PSB697X_REG_CMH_CPN_SHIFT 5
59 +static inline int psb697x_mii_read(struct mii_dev *bus, u16 reg)
63 + ret = bus->read(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE, reg & 0x1f);
68 +static inline int psb697x_mii_write(struct mii_dev *bus, u16 reg, u16 val)
72 + ret = bus->write(bus, (reg >> 5) & 0x1f, MDIO_DEVAD_NONE,
78 +static int psb697x_probe(struct switch_device *dev)
80 + struct mii_dev *bus = dev->bus;
83 + ci1 = psb697x_mii_read(bus, PSB697X_REG_CI1);
85 + if (ci1 == PSB697X_CHIPID1)
91 +static void psb697x_setup(struct switch_device *dev)
93 + struct mii_dev *bus = dev->bus;
97 + psb697x_mii_write(bus, PSB697X_REG_SGC2, PSB697X_REG_SGC2_SE);
100 + * Force 100 Mbps as default value for CPU ports 5 and 6 to get
103 + psb697x_mii_write(bus, PSB697X_REG_MIICR, 0x0773);
105 + for (i = 0; i < PSB697X_PORT_COUNT; i++) {
106 + state = dev->port_mask & (1 << i);
109 + * Software workaround from Errata Sheet:
110 + * Force link down and reset internal PHY, keep that state
111 + * for all unconnected ports and disable force link down
112 + * for all connected ports
114 + psb697x_mii_write(bus, PSB697X_REG_PBC(i),
115 + PSB697X_REG_PORT_FLD);
117 + if (i == dev->cpu_port)
118 + /* Force link up for CPU port */
119 + psb697x_mii_write(bus, PSB697X_REG_PBC(i),
120 + PSB697X_REG_PORT_FLP);
122 + /* Disable force link down for active LAN ports */
123 + psb697x_mii_write(bus, PSB697X_REG_PBC(i), 0);
127 +static struct switch_driver psb697x_drv = {
131 +void switch_psb697x_init(void)
133 + /* For archs with manual relocation */
134 + psb697x_drv.probe = psb697x_probe;
135 + psb697x_drv.setup = psb697x_setup;
137 + switch_driver_register(&psb697x_drv);
139 --- a/drivers/net/switch/switch.c
140 +++ b/drivers/net/switch/switch.c
141 @@ -17,6 +17,10 @@ void switch_init(void)
142 INIT_LIST_HEAD(&switch_drivers);
143 INIT_LIST_HEAD(&switch_devices);
145 +#if defined(CONFIG_SWITCH_PSB697X)
146 + switch_psb697x_init();
152 --- a/include/switch.h
153 +++ b/include/switch.h
154 @@ -97,6 +97,7 @@ static inline void switch_setup(struct s
157 /* Init functions for supported Switch drivers */
158 +extern void switch_psb697x_init(void);
160 #endif /* __SWITCH_H */