1 From 42cb399df978a33539b95d668b3f973d927cb902 Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Mon, 17 Dec 2012 23:37:57 +0100
4 Subject: net: switchlib: add driver for REALTEK RTL8306
6 Signed-off-by: Oliver Muth <dr.o.muth@gmx.de>
7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 --- a/drivers/net/switch/Makefile
10 +++ b/drivers/net/switch/Makefile
11 @@ -13,6 +13,7 @@ COBJS-$(CONFIG_SWITCH_MULTI) += switch.o
12 COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o
13 COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o
14 COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o
15 +COBJS-$(CONFIG_SWITCH_RTL8306) += rtl8306.o
18 SRCS := $(COBJS:.o=.c)
20 +++ b/drivers/net/switch/rtl8306.c
23 + * Based on OpenWRT linux driver
25 + * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
26 + * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
28 + * SPDX-License-Identifier: GPL-2.0+
36 +#define RTL8306_REG_PAGE 16
37 +#define RTL8306_REG_PAGE_LO (1 << 15)
38 +#define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */
39 +#define RTL8306_CHIPID 0x5988
41 +#define RTL8306_NUM_VLANS 16
42 +#define RTL8306_NUM_PORTS 6
43 +#define RTL8306_PORT_CPU 5
44 +#define RTL8306_NUM_PAGES 4
45 +#define RTL8306_NUM_REGS 32
73 + RTL_REG_TRUNK_PORTSEL,
79 + RTL_REG_VLAN_ENABLE,
80 + RTL_REG_VLAN_FILTER,
81 + RTL_REG_VLAN_TAG_ONLY,
82 + RTL_REG_VLAN_TAG_AWARE,
83 +#define RTL_VLAN_ENUM(id) \
84 + RTL_REG_VLAN##id##_VID, \
85 + RTL_REG_VLAN##id##_PORTMASK
102 +#define RTL_PORT_ENUM(id) \
103 + RTL_REG_PORT##id##_PVID, \
104 + RTL_REG_PORT##id##_NULL_VID_REPLACE, \
105 + RTL_REG_PORT##id##_NON_PVID_DISCARD, \
106 + RTL_REG_PORT##id##_VID_INSERT, \
107 + RTL_REG_PORT##id##_TAG_INSERT, \
108 + RTL_REG_PORT##id##_LINK, \
109 + RTL_REG_PORT##id##_SPEED, \
110 + RTL_REG_PORT##id##_NWAY, \
111 + RTL_REG_PORT##id##_NRESTART, \
112 + RTL_REG_PORT##id##_DUPLEX, \
113 + RTL_REG_PORT##id##_RXEN, \
114 + RTL_REG_PORT##id##_TXEN, \
115 + RTL_REG_PORT##id##_LRNEN
124 +static const struct rtl_reg rtl_regs[] = {
125 + [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 },
126 + [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 },
127 + [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 },
129 + /* CPU port number */
130 + [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 },
131 + /* Enable CPU port function */
132 + [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 },
133 + /* Enable CPU port tag insertion */
134 + [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 },
135 + /* Enable CPU port tag removal */
136 + [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 },
137 + /* Enable CPU port tag checking */
138 + [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 },
139 + [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 },
140 + [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 },
141 + [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 },
142 + [RTL_REG_PHY_RESET] = { 0, 0, 0, 1, 15, 0 },
143 + [RTL_REG_CPU_LINKUP] = { 0, 6, 22, 1, 15, 0 },
144 + [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 },
146 + [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 },
147 + [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 },
148 + [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 },
149 + [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 },
151 +#define RTL_VLAN_REGS(id, phy, page, regofs) \
152 + [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \
153 + [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 }
154 + RTL_VLAN_REGS( 0, 0, 0, 0),
155 + RTL_VLAN_REGS( 1, 1, 0, 0),
156 + RTL_VLAN_REGS( 2, 2, 0, 0),
157 + RTL_VLAN_REGS( 3, 3, 0, 0),
158 + RTL_VLAN_REGS( 4, 4, 0, 0),
159 + RTL_VLAN_REGS( 5, 0, 1, 2),
160 + RTL_VLAN_REGS( 6, 1, 1, 2),
161 + RTL_VLAN_REGS( 7, 2, 1, 2),
162 + RTL_VLAN_REGS( 8, 3, 1, 2),
163 + RTL_VLAN_REGS( 9, 4, 1, 2),
164 + RTL_VLAN_REGS(10, 0, 1, 4),
165 + RTL_VLAN_REGS(11, 1, 1, 4),
166 + RTL_VLAN_REGS(12, 2, 1, 4),
167 + RTL_VLAN_REGS(13, 3, 1, 4),
168 + RTL_VLAN_REGS(14, 4, 1, 4),
169 + RTL_VLAN_REGS(15, 0, 1, 6),
171 +#define REG_PORT_SETTING(port, phy) \
172 + [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \
173 + [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \
174 + [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \
175 + [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \
176 + [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \
177 + [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \
178 + [RTL_REG_PORT##port##_LRNEN] = { 0, phy, 24, 1, 9, 0 }, \
179 + [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \
180 + [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \
181 + [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \
182 + [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \
183 + [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 }
185 + REG_PORT_SETTING(0, 0),
186 + REG_PORT_SETTING(1, 1),
187 + REG_PORT_SETTING(2, 2),
188 + REG_PORT_SETTING(3, 3),
189 + REG_PORT_SETTING(4, 4),
190 + REG_PORT_SETTING(5, 6),
192 +#define REG_PORT_PVID(phy, page, regofs) \
193 + { page, phy, 24 + regofs, 4, 12, 0 }
194 + [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0),
195 + [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0),
196 + [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0),
197 + [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0),
198 + [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0),
199 + [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2),
202 +static void rtl_set_page(struct mii_dev *bus, unsigned int page)
206 + BUG_ON(page > RTL8306_NUM_PAGES);
208 + pgsel = bus->read(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE);
209 + pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI);
211 + if (page & (1 << 0))
212 + pgsel |= RTL8306_REG_PAGE_LO;
214 + if (!(page & (1 << 1))) /* bit is inverted */
215 + pgsel |= RTL8306_REG_PAGE_HI;
217 + bus->write(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE, pgsel);
221 +static __maybe_unused int rtl_w16(struct mii_dev *bus, unsigned int page, unsigned int phy,
222 + unsigned int reg, u16 val)
224 + rtl_set_page(bus, page);
226 + bus->write(bus, phy, MDIO_DEVAD_NONE, reg, val);
227 + bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */
232 +static int rtl_r16(struct mii_dev *bus, unsigned int page, unsigned int phy,
235 + rtl_set_page(bus, page);
237 + return bus->read(bus, phy, MDIO_DEVAD_NONE, reg);
240 +static u16 rtl_rmw(struct mii_dev *bus, unsigned int page, unsigned int phy,
241 + unsigned int reg, u16 mask, u16 val)
245 + rtl_set_page(bus, page);
247 + r = bus->read(bus, phy, MDIO_DEVAD_NONE, reg);
250 + bus->write(bus, phy, MDIO_DEVAD_NONE, reg, r);
252 + return bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */
255 +static int rtl_get(struct mii_dev *bus, enum rtl_regidx s)
257 + const struct rtl_reg *r = &rtl_regs[s];
260 + BUG_ON(s >= ARRAY_SIZE(rtl_regs));
262 + if (r->bits == 0) /* unimplemented */
265 + val = rtl_r16(bus, r->page, r->phy, r->reg);
273 + val &= (1 << r->bits) - 1;
278 +static __maybe_unused int rtl_set(struct mii_dev *bus, enum rtl_regidx s, unsigned int val)
280 + const struct rtl_reg *r = &rtl_regs[s];
283 + BUG_ON(s >= ARRAY_SIZE(rtl_regs));
285 + if (r->bits == 0) /* unimplemented */
294 + if (r->bits != 16) {
295 + mask = (1 << r->bits) - 1;
301 + return rtl_rmw(bus, r->page, r->phy, r->reg, mask, val);
304 +static int rtl8306_probe(struct switch_device *dev)
306 + struct mii_dev *bus = dev->bus;
307 + unsigned int chipid, chipver, chiptype;
309 + chipid = rtl_get(bus, RTL_REG_CHIPID);
310 + chipver = rtl_get(bus, RTL_REG_CHIPVER);
311 + chiptype = rtl_get(bus, RTL_REG_CHIPTYPE);
313 + debug("%s: chipid %x, chipver %x, chiptype %x\n",
314 + __func__, chipid, chipver, chiptype);
316 + if (chipid == RTL8306_CHIPID)
322 +static void rtl8306_setup(struct switch_device *dev)
324 + struct mii_dev *bus = dev->bus;
326 + /* initialize cpu port settings */
327 + rtl_set(bus, RTL_REG_CPUPORT, dev->cpu_port);
328 + rtl_set(bus, RTL_REG_EN_CPUPORT, 1);
330 + /* enable phy 5 link status */
331 + rtl_set(bus, RTL_REG_CPU_LINKUP, 1);
332 +// rtl_set(bus, RTL_REG_PORT5_TXEN, 1);
333 +// rtl_set(bus, RTL_REG_PORT5_RXEN, 1);
334 +// rtl_set(bus, RTL_REG_PORT5_LRNEN, 1);
336 + debug("%s: CPU link up: %i\n",
337 + __func__, rtl_get(bus, RTL_REG_PORT5_LINK));
342 +static struct switch_driver rtl8306_drv = {
346 +void switch_rtl8306_init(void)
348 + /* For archs with manual relocation */
349 + rtl8306_drv.probe = rtl8306_probe;
350 + rtl8306_drv.setup = rtl8306_setup;
352 + switch_driver_register(&rtl8306_drv);
354 --- a/drivers/net/switch/switch.c
355 +++ b/drivers/net/switch/switch.c
356 @@ -26,6 +26,9 @@ void switch_init(void)
357 #if defined(CONFIG_SWITCH_AR8216)
358 switch_ar8216_init();
360 +#if defined(CONFIG_SWITCH_RTL8306)
361 + switch_rtl8306_init();
366 --- a/include/switch.h
367 +++ b/include/switch.h
368 @@ -100,6 +100,7 @@ static inline void switch_setup(struct s
369 extern void switch_psb697x_init(void);
370 extern void switch_adm6996i_init(void);
371 extern void switch_ar8216_init(void);
372 +extern void switch_rtl8306_init(void);
374 #endif /* __SWITCH_H */