1 From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001
2 From: Luka Perkov <luka@openwrt.org>
3 Date: Sat, 2 Mar 2013 23:34:00 +0100
4 Subject: tools: add some helper tools for Lantiq SoCs
6 Signed-off-by: Luka Perkov Luka Perkov <luka@openwrt.org>
7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
9 diff --git a/tools/gct.pl b/tools/gct.pl
11 index 0000000..33fa6f7
37 + die("\n Syntax: perl gct.pl uart_ddr_settings.conf u-boot.srec u-boot.asc\n");
40 +open(IN_UART_DDR_SETTINGS, "<$ARGV[0]") || die("failed to open uart_ddr_settings.conf\n");
41 +open(IN_UART_SREC, "<$ARGV[1]") || die("failed to open u-boot.srec\n");
42 +open(OUT_UBOOT_ASC, ">$ARGV[2]") || die("failed to open u-boot.asc\n");
45 +while ($line = <IN_UART_DDR_SETTINGS>){
47 + if($line!~/[;#\*]/){
49 + printf OUT_UBOOT_ASC ("33333333");
53 + @array=split(/ +/,$line);
55 + while(@array[$j]!~/\w/){
59 + $regval=@array[$j+1];
62 + printf OUT_UBOOT_ASC ("%08x%08x",hex($addr),hex($regval));
66 + printf OUT_UBOOT_ASC ("\n");
72 +while($i lt 8 && $i gt 0){
73 + printf OUT_UBOOT_ASC "00"x8;
78 + printf OUT_UBOOT_ASC ("\n");
81 +while($aline=<IN_UART_SREC>){
84 + next if(($aline=~/^S0/) || ($aline=~/^S7/));
85 + ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline;
86 + $length = hex($length);
87 + $address = hex($address);
93 + $addstr = sprintf("%x", $address);
94 + $addstr = "0"x(8-length($addstr)).$addstr;
95 + print OUT_UBOOT_ASC $addstr;
98 + $currentaddr=$address;
99 + $loadaddr = $addstr;
103 + $addstr = sprintf("%x", $currentaddr);
104 + $addstr = "0"x(8-length($addstr)).$addstr;
105 + print OUT_UBOOT_ASC $addstr;
109 +#printf("*** %x != %x\n", $address, $currentaddr) if $address != $currentaddr;
111 + if($currentaddr < $address) {
112 + print OUT_UBOOT_ASC "00";
119 + $bytes[$i]=~tr/ABCDEF/abcdef/;
120 + print OUT_UBOOT_ASC "$bytes[$i]";
121 + addchsum($bytes[$i]);
126 + last if($length==0);
130 + print OUT_UBOOT_ASC "\n";
136 + for($i=0;$i<(64-$count);$i++){
137 + print OUT_UBOOT_ASC "00";
140 + print OUT_UBOOT_ASC "\n";
144 +print OUT_UBOOT_ASC "11"x4;
146 +$chsum=$chsum & 0xffffffff;
147 +$chsum = sprintf("%X", $chsum);
148 +$chsum = "0"x(8-length($chsum)).$chsum;
149 +$chsum =~tr/ABCDEF/abcdef/;
150 +print OUT_UBOOT_ASC $chsum;
151 +print OUT_UBOOT_ASC "00"x60;
152 +print OUT_UBOOT_ASC "\n";
154 +print OUT_UBOOT_ASC "99"x4;
155 +print OUT_UBOOT_ASC $loadaddr;
156 +print OUT_UBOOT_ASC "00"x60;
157 +print OUT_UBOOT_ASC "\n";
159 +close OUT_UBOOT_ASC;
163 + $holder=$holder.$cc;
164 + if(length($holder)==8){
165 + $holder = hex($holder);
170 diff --git a/tools/lantiq_bdi_conf.awk b/tools/lantiq_bdi_conf.awk
172 index 0000000..c732289
174 +++ b/tools/lantiq_bdi_conf.awk
178 +# Copyright (C) 2013 Luka Perkov <luka@openwrt.org>
179 +# Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
182 +# awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h
184 +# Additional information:
185 +# http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf
187 +# SPDX-License-Identifier: GPL-2.0+
190 +function print_header()
193 + print "; Copyright (C) 2013 Luka Perkov <luka@openwrt.org> "
194 + print "; Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> "
196 + print "; This file has been generated with lantiq_bdi_conf.awk script. "
198 + print "; SPDX-License-Identifier: GPL-2.0+ "
203 +function init_ar9_prologue()
205 + print "WM32 0xBF103010 0x80 ; CGU for CPU 333Mhz, DDR 167Mhz"
206 + print "WM32 0xBF103014 0x01 ; CGU update"
207 + print "WM32 0xBF800010 0x0 ; Clear error access log register"
208 + print "WM32 0xBF800020 0x0 ; Clear error access log register"
209 + print "WM32 0xBF800060 0xD ; Enable FPI, DDR and SRAM module in memory controller"
210 + print "WM32 0xBF801030 0x0 ; Clear start bit of DDR memory controller"
213 +function init_ar9_epilogue()
215 + print "WM32 0xBE105360 0x4001D7FF ; EBU setup"
218 +function init_ddr1_epilogue()
220 + print "WM32 0xBF801030 0x100 ; Set start bit of DDR memory controller"
223 +function ar9_target()
225 + print "CPUTYPE M34K"
227 + print "JTAGCLOCK 1"
228 + print "BDIMODE AGENT ; [ LOADONLY, AGENT ]"
229 + print "RESET JTAG ; [ NONE, JTAG, HARD ]"
230 + print "POWERUP 100"
232 + print "BREAKMODE HARD ; [ SOFT, HARD ]"
233 + print "STEPMODE SWBP ; [ JTAG, HWBP, SWBP ]"
234 + print "VECTOR CATCH"
235 + print "SCANSUCC 1 5"
238 +function flash_p2601hnfx()
240 + print "CHIPTYPE MIRRORX16"
241 + print "CHIPSIZE 0x1000000"
242 + print "BUSWIDTH 16"
248 + reg_base = 0xbf801000
251 + init_ar9_prologue()
254 + print "Invalid or no value for SoC specified!"
260 + /* DC03 contains MC enable bit and must not be set here */
261 + if (tolower($2) != "mc_dc03_value")
262 + printf("WM32 0x%x %s\n", reg_base, tolower($3))
270 + init_ddr1_epilogue()
271 + init_ar9_epilogue()
277 + print "PROMPT \"ar9> \""
292 diff --git a/tools/lantiq_ram_extract_magic.awk b/tools/lantiq_ram_extract_magic.awk
294 index 0000000..64f1cbc
296 +++ b/tools/lantiq_ram_extract_magic.awk
299 +# Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
302 +# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk
304 +# SPDX-License-Identifier: GPL-2.0+
309 + print " * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> "
311 + print " * This file has been generated with lantiq_ram_extract_magic.awk script. "
313 + print " * SPDX-License-Identifier: GPL-2.0+ "
320 + mc_dc_value_print=0
321 + mc_dc_number_print=0
325 + if (right_section) {
326 + split($4, tmp, ",")
327 + mc_dc_value=sprintf("%X", tmp[2])
328 + mc_dc_value_print=1
333 + if (right_section) {
334 + split($4, tmp, ",0x")
335 + mc_dc_value=sprintf("%s", tmp[2])
336 + mc_dc_value=toupper(mc_dc_value)
337 + mc_dc_value_print=1
341 +/t2,[0-9]+\(t1\)$/ {
342 + if (right_section) {
343 + split($4, tmp, ",")
344 + split(tmp[2], tmp, "(")
345 + mc_dc_number=tmp[1]/16
346 + mc_dc_number_print=1
351 + if (right_section && mc_dc_number_print && mc_dc_value_print) {
352 + if (mc_dc_number < 10)
353 + print "#define MC_DC0" mc_dc_number "_VALUE\t0x" mc_dc_value
355 + print "#define MC_DC" mc_dc_number "_VALUE\t0x" mc_dc_value
356 + mc_dc_value_print=0
357 + mc_dc_number_print=0
360 + if ($4 == "t1,t1,0x1000")
364 + if ($4 == "t2,736(t1)")
367 diff --git a/tools/lantiq_ram_init_uart.awk b/tools/lantiq_ram_init_uart.awk
369 index 0000000..dc82645
371 +++ b/tools/lantiq_ram_init_uart.awk
375 +# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org>
376 +# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
379 +# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h
381 +# SPDX-License-Identifier: GPL-2.0+
384 +function print_header()
387 + print "; Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> "
388 + print "; Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> "
390 + print "; This file has been generated with lantiq_ram_init_uart.awk script. "
392 + print "; SPDX-License-Identifier: GPL-2.0+ "
396 +function mc_danube_prologue()
398 + /* Clear access error log registers */
399 + print "0xbf800010", "0x0"
400 + print "0xbf800020", "0x0"
402 + /* Enable DDR and SRAM module in memory controller */
403 + print "0xbf800060", "0x5"
405 + /* Clear start bit of DDR memory controller */
406 + print "0xbf801030", "0x0"
409 +function mc_ar9_prologue()
411 + /* Clear access error log registers */
412 + print "0xbf800010", "0x0"
413 + print "0xbf800020", "0x0"
415 + /* Enable FPI, DDR and SRAM module in memory controller */
416 + print "0xbf800060", "0xD"
418 + /* Clear start bit of DDR memory controller */
419 + print "0xbf801030", "0x0"
422 +function mc_ddr1_epilogue()
424 + /* Set start bit of DDR memory controller */
425 + print "0xbf801030", "0x100"
428 +function mc_ddr2_prologue()
430 + /* Put memory controller in inactive mode */
431 + print "0xbf401070", "0x0"
434 +function mc_ddr2_epilogue(mc_ccr07_value)
436 + /* Put memory controller in active mode */
437 + mc_ccr07_value = or(mc_ccr07_value, 0x100)
438 + printf("0xbf401070 0x%x\n", mc_ccr07_value)
444 + reg_base = 0xbf801000
446 + mc_danube_prologue()
449 + reg_base = 0xbf801000
454 + reg_base = 0xbf401000
459 + print "Invalid or no value for soc specified!"
467 + /* CCR07 contains MC enable bit and must not be set here */
468 + if (tolower($2) == "mc_ccr07_value")
469 + mc_ccr07_value = strtonum($3)
470 + if (tolower($2) == "mc_dc03_value")
471 + /* CCR07 contains MC enable bit and must not be set here */
473 + printf("0x%x %s\n", reg_base, tolower($3))
485 + mc_ddr2_epilogue(mc_ccr07_value)