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uboot-lantiq: reorder and rework patches
[openwrt/staging/rmilecki.git] / package / boot / uboot-lantiq / patches / 0100-MIPS-add-board-support-for-Easy-50712.patch
1 --- /dev/null
2 +++ b/board/lantiq/easy50712/Makefile
3 @@ -0,0 +1,27 @@
4 +#
5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
6 +#
7 +# SPDX-License-Identifier: GPL-2.0+
8 +#
9 +
10 +include $(TOPDIR)/config.mk
11 +
12 +LIB = $(obj)lib$(BOARD).o
13 +
14 +COBJS = $(BOARD).o
15 +
16 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
17 +OBJS := $(addprefix $(obj),$(COBJS))
18 +SOBJS := $(addprefix $(obj),$(SOBJS))
19 +
20 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
21 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
22 +
23 +#########################################################################
24 +
25 +# defines $(obj).depend target
26 +include $(SRCTREE)/rules.mk
27 +
28 +sinclude $(obj).depend
29 +
30 +#########################################################################
31 --- /dev/null
32 +++ b/board/lantiq/easy50712/config.mk
33 @@ -0,0 +1,7 @@
34 +#
35 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
36 +#
37 +# SPDX-License-Identifier: GPL-2.0+
38 +#
39 +
40 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
41 --- /dev/null
42 +++ b/board/lantiq/easy50712/ddr_settings.h
43 @@ -0,0 +1,54 @@
44 +/*
45 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
46 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
47 + *
48 + * SPDX-License-Identifier: GPL-2.0+
49 + */
50 +
51 +#define MC_DC00_VALUE 0x1B1B
52 +#define MC_DC01_VALUE 0x0
53 +#define MC_DC02_VALUE 0x0
54 +#define MC_DC03_VALUE 0x0
55 +#define MC_DC04_VALUE 0x0
56 +#define MC_DC05_VALUE 0x200
57 +#define MC_DC06_VALUE 0x605
58 +#define MC_DC07_VALUE 0x303
59 +#define MC_DC08_VALUE 0x102
60 +#define MC_DC09_VALUE 0x70a
61 +#define MC_DC10_VALUE 0x203
62 +#define MC_DC11_VALUE 0xc02
63 +#define MC_DC12_VALUE 0x1C8
64 +#define MC_DC13_VALUE 0x1
65 +#define MC_DC14_VALUE 0x0
66 +#define MC_DC15_VALUE 0x13c
67 +#define MC_DC16_VALUE 0xC800
68 +#define MC_DC17_VALUE 0xd
69 +#define MC_DC18_VALUE 0x300
70 +#define MC_DC19_VALUE 0x200
71 +#define MC_DC20_VALUE 0xA04
72 +#define MC_DC21_VALUE 0xd00
73 +#define MC_DC22_VALUE 0xd0d
74 +#define MC_DC23_VALUE 0x0
75 +#define MC_DC24_VALUE 0x62
76 +#define MC_DC25_VALUE 0x0
77 +#define MC_DC26_VALUE 0x0
78 +#define MC_DC27_VALUE 0x0
79 +#define MC_DC28_VALUE 0x510
80 +#define MC_DC29_VALUE 0x2d89
81 +#define MC_DC30_VALUE 0x8300
82 +#define MC_DC31_VALUE 0x0
83 +#define MC_DC32_VALUE 0x0
84 +#define MC_DC33_VALUE 0x0
85 +#define MC_DC34_VALUE 0x0
86 +#define MC_DC35_VALUE 0x0
87 +#define MC_DC36_VALUE 0x0
88 +#define MC_DC37_VALUE 0x0
89 +#define MC_DC38_VALUE 0x0
90 +#define MC_DC39_VALUE 0x0
91 +#define MC_DC40_VALUE 0x0
92 +#define MC_DC41_VALUE 0x0
93 +#define MC_DC42_VALUE 0x0
94 +#define MC_DC43_VALUE 0x0
95 +#define MC_DC44_VALUE 0x0
96 +#define MC_DC45_VALUE 0x500
97 +#define MC_DC46_VALUE 0x0
98 --- /dev/null
99 +++ b/board/lantiq/easy50712/easy50712.c
100 @@ -0,0 +1,112 @@
101 +/*
102 + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
103 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
104 + *
105 + * SPDX-License-Identifier: GPL-2.0+
106 + */
107 +
108 +#include <common.h>
109 +#include <switch.h>
110 +#include <spi.h>
111 +#include <asm/gpio.h>
112 +#include <asm/lantiq/eth.h>
113 +#include <asm/lantiq/reset.h>
114 +#include <asm/lantiq/chipid.h>
115 +
116 +static void gpio_init(void)
117 +{
118 + /* SPI/CS output (low-active) for serial flash */
119 + gpio_direction_output(22, 1);
120 +
121 + /* EBU.FL_CS1 as output for NAND CE */
122 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
123 + /* EBU.FL_A23 as output for NAND CLE */
124 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
125 + /* EBU.FL_A24 as output for NAND ALE */
126 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
127 +
128 + /* enable CLK_OUT2 for external switch */
129 + gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
130 +}
131 +
132 +int board_early_init_f(void)
133 +{
134 + gpio_init();
135 +
136 + return 0;
137 +}
138 +
139 +int checkboard(void)
140 +{
141 + puts("Board: " CONFIG_BOARD_NAME "\n");
142 + ltq_chip_print_info();
143 +
144 + return 0;
145 +}
146 +
147 +static const struct ltq_eth_port_config eth_port_config[] = {
148 + /* MAC0: Lantiq ADM6996I switch */
149 + { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
150 +};
151 +
152 +static const struct ltq_eth_board_config eth_board_config = {
153 + .ports = eth_port_config,
154 + .num_ports = ARRAY_SIZE(eth_port_config),
155 +};
156 +
157 +int board_eth_init(bd_t *bis)
158 +{
159 + return ltq_eth_initialize(&eth_board_config);
160 +}
161 +
162 +static struct switch_device adm6996i_dev = {
163 + .name = "adm6996i",
164 + .cpu_port = 5,
165 + .port_mask = 0xF,
166 +};
167 +
168 +int board_switch_init(void)
169 +{
170 + /* Deactivate HRST line to release reset of ADM6996I switch */
171 + ltq_reset_once(LTQ_RESET_HARD, 200000);
172 +
173 + /* ADM6996I needs some time to come out of reset */
174 + __udelay(50000);
175 +
176 + return switch_device_register(&adm6996i_dev);
177 +}
178 +
179 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
180 +{
181 + if (bus)
182 + return 0;
183 +
184 + switch (cs) {
185 + case 2:
186 + return 1;
187 + default:
188 + return 0;
189 + }
190 +}
191 +
192 +void spi_cs_activate(struct spi_slave *slave)
193 +{
194 + switch (slave->cs) {
195 + case 2:
196 + gpio_set_value(22, 0);
197 + break;
198 + default:
199 + break;
200 + }
201 +}
202 +
203 +void spi_cs_deactivate(struct spi_slave *slave)
204 +{
205 + switch (slave->cs) {
206 + case 2:
207 + gpio_set_value(22, 1);
208 + break;
209 + default:
210 + break;
211 + }
212 +}
213 --- a/boards.cfg
214 +++ b/boards.cfg
215 @@ -502,6 +502,9 @@ Active mips mips32 au1x0
216 Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
217 Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
218 Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
219 +Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
220 +Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
221 +Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
222 Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
223 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
224 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
225 --- /dev/null
226 +++ b/include/configs/easy50712.h
227 @@ -0,0 +1,79 @@
228 +/*
229 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
230 + *
231 + * SPDX-License-Identifier: GPL-2.0+
232 + */
233 +
234 +#ifndef __CONFIG_H
235 +#define __CONFIG_H
236 +
237 +#define CONFIG_MACH_TYPE "EASY50712"
238 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
239 +#define CONFIG_BOARD_NAME "Lantiq EASY50712 Danube Reference Board"
240 +
241 +/* Configure SoC */
242 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
243 +
244 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
245 +
246 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
247 +
248 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
249 +#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */
250 +
251 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH
252 +
253 +#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
254 +
255 +#define CONFIG_LTQ_SPL_COMP_LZO
256 +#define CONFIG_LTQ_SPL_CONSOLE
257 +
258 +/* Switch devices */
259 +#define CONFIG_SWITCH_MULTI
260 +#define CONFIG_SWITCH_ADM6996I
261 +
262 +/* Environment */
263 +#define CONFIG_ENV_SPI_BUS 0
264 +#define CONFIG_ENV_SPI_CS 2
265 +#define CONFIG_ENV_SPI_MAX_HZ 20000000
266 +#define CONFIG_ENV_SPI_MODE 0
267 +
268 +#if defined(CONFIG_SYS_BOOT_NOR)
269 +#define CONFIG_ENV_IS_IN_FLASH
270 +#define CONFIG_ENV_OVERWRITE
271 +#define CONFIG_ENV_OFFSET (256 * 1024)
272 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
273 +#elif defined(CONFIG_SYS_BOOT_NORSPL)
274 +#define CONFIG_ENV_IS_IN_FLASH
275 +#define CONFIG_ENV_OVERWRITE
276 +#define CONFIG_ENV_OFFSET (128 * 1024)
277 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
278 +#else
279 +#define CONFIG_ENV_IS_NOWHERE
280 +#endif
281 +
282 +#define CONFIG_ENV_SIZE (8 * 1024)
283 +
284 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
285 +
286 +/* Console */
287 +#define CONFIG_LTQ_ADVANCED_CONSOLE
288 +#define CONFIG_BAUDRATE 115200
289 +#define CONFIG_CONSOLE_ASC 1
290 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
291 +
292 +/* Pull in default board configs for Lantiq XWAY Danube */
293 +#include <asm/lantiq/config.h>
294 +#include <asm/arch/config.h>
295 +
296 +/* Pull in default OpenWrt configs for Lantiq SoC */
297 +#include "openwrt-lantiq-common.h"
298 +
299 +#define CONFIG_ENV_UPDATE_UBOOT_NOR \
300 + "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
301 +
302 +#define CONFIG_EXTRA_ENV_SETTINGS \
303 + CONFIG_ENV_LANTIQ_DEFAULTS \
304 + CONFIG_ENV_UPDATE_UBOOT_NOR
305 +
306 +#endif /* __CONFIG_H */
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