2 +++ b/board/arcadyan/arv7506pw11/Makefile
5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
7 +# SPDX-License-Identifier: GPL-2.0+
10 +include $(TOPDIR)/config.mk
12 +LIB = $(obj)lib$(BOARD).o
16 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
17 +OBJS := $(addprefix $(obj),$(COBJS))
18 +SOBJS := $(addprefix $(obj),$(SOBJS))
20 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
21 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
23 +#########################################################################
25 +# defines $(obj).depend target
26 +include $(SRCTREE)/rules.mk
28 +sinclude $(obj).depend
30 +#########################################################################
32 +++ b/board/arcadyan/arv7506pw11/arv7506pw11.c
35 + * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
37 + * SPDX-License-Identifier: GPL-2.0+
42 +#include <asm/gpio.h>
43 +#include <asm/lantiq/eth.h>
44 +#include <asm/lantiq/reset.h>
45 +#include <asm/lantiq/chipid.h>
47 +#if defined(CONFIG_SYS_BOOT_RAM)
48 +#define do_gpio_init 1
49 +#elif defined(CONFIG_SYS_BOOT_NOR)
50 +#define do_gpio_init 1
52 +#define do_gpio_init 0
55 +#define GPIO_POWER_GREEN 3
56 +#define GPIO_POWER_RED 6
57 +#define GPIO_GPHY_RESET 19
59 +static void gpio_init(void)
61 + /* Reset switch to have him in a clean state on reboot */
62 + gpio_direction_output(GPIO_GPHY_RESET, 0);
64 + gpio_direction_output(GPIO_GPHY_RESET, 1);
66 + /* Turn on the green power LED */
67 + gpio_direction_output(GPIO_POWER_GREEN, 0);
69 + /* Turn off the red power LED */
70 + gpio_direction_output(GPIO_POWER_RED, 1);
73 +int board_early_init_f(void)
83 + puts("Board: " CONFIG_BOARD_NAME "\n");
84 + ltq_chip_print_info();
89 +void show_boot_progress(int arg)
95 + /* Success - turn off the red power LED and turn on the green power LED */
96 + gpio_set_value(GPIO_POWER_RED, 1);
97 + gpio_set_value(GPIO_POWER_GREEN, 0);
99 + /* Failure - turn off green power LED and turn on red power LED */
100 + gpio_set_value(GPIO_POWER_GREEN, 1);
101 + gpio_set_value(GPIO_POWER_RED, 0);
107 +static const struct ltq_eth_port_config eth_port_config[] = {
108 + /* MAC0: Realtek rtl8306 switch */
109 + { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
112 +static const struct ltq_eth_board_config eth_board_config = {
113 + .ports = eth_port_config,
114 + .num_ports = ARRAY_SIZE(eth_port_config),
117 +int board_eth_init(bd_t *bis)
119 + return ltq_eth_initialize(ð_board_config);
121 +static struct switch_device rtl8306_dev = {
127 +int board_switch_init(void)
129 + return switch_device_register(&rtl8306_dev);
132 +++ b/board/arcadyan/arv7506pw11/config.mk
135 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
137 +# SPDX-License-Identifier: GPL-2.0+
140 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
142 +++ b/board/arcadyan/arv7506pw11/ddr_settings.h
145 + * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
147 + * This file has been generated with lantiq_ram_extract_magic.awk script.
149 + * SPDX-License-Identifier: GPL-2.0+
152 +#define MC_DC00_VALUE 0x1B1B
153 +#define MC_DC01_VALUE 0x0
154 +#define MC_DC02_VALUE 0x0
155 +#define MC_DC03_VALUE 0x0
156 +#define MC_DC04_VALUE 0x0
157 +#define MC_DC05_VALUE 0x200
158 +#define MC_DC06_VALUE 0x605
159 +#define MC_DC07_VALUE 0x303
160 +#define MC_DC08_VALUE 0x102
161 +#define MC_DC09_VALUE 0x70A
162 +#define MC_DC10_VALUE 0x203
163 +#define MC_DC11_VALUE 0xC02
164 +#define MC_DC12_VALUE 0x1C8
165 +#define MC_DC13_VALUE 0x1
166 +#define MC_DC14_VALUE 0x0
167 +#define MC_DC15_VALUE 0x142
168 +#define MC_DC16_VALUE 0xC800
169 +#define MC_DC17_VALUE 0xD
170 +#define MC_DC18_VALUE 0x301
171 +#define MC_DC19_VALUE 0x200
172 +#define MC_DC20_VALUE 0xA03
173 +#define MC_DC21_VALUE 0x1300
174 +#define MC_DC22_VALUE 0x1313
175 +#define MC_DC23_VALUE 0x0
176 +#define MC_DC24_VALUE 0x68
177 +#define MC_DC25_VALUE 0x0
178 +#define MC_DC26_VALUE 0x0
179 +#define MC_DC27_VALUE 0x0
180 +#define MC_DC28_VALUE 0x510
181 +#define MC_DC29_VALUE 0x4E20
182 +#define MC_DC30_VALUE 0x8235
183 +#define MC_DC31_VALUE 0x0
184 +#define MC_DC32_VALUE 0x0
185 +#define MC_DC33_VALUE 0x0
186 +#define MC_DC34_VALUE 0x0
187 +#define MC_DC35_VALUE 0x0
188 +#define MC_DC36_VALUE 0x0
189 +#define MC_DC37_VALUE 0x0
190 +#define MC_DC38_VALUE 0x0
191 +#define MC_DC39_VALUE 0x0
192 +#define MC_DC40_VALUE 0x0
193 +#define MC_DC41_VALUE 0x0
194 +#define MC_DC42_VALUE 0x0
195 +#define MC_DC43_VALUE 0x0
196 +#define MC_DC44_VALUE 0x0
197 +#define MC_DC45_VALUE 0x500
198 +#define MC_DC46_VALUE 0x0
201 @@ -505,6 +505,9 @@ Active mips mips32 au1x0
202 Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
203 Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
204 Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
205 +Active mips mips32 danube arcadyan arv7506pw11 arv7506pw11_brn arv7506pw11:SYS_BOOT_BRN Mathias Kresin <dev@kresin.me>
206 +Active mips mips32 danube arcadyan arv7506pw11 arv7506pw11_nor arv7506pw11:SYS_BOOT_NOR Mathias Kresin <dev@kresin.me>
207 +Active mips mips32 danube arcadyan arv7506pw11 arv7506pw11_ram arv7506pw11:SYS_BOOT_RAM Mathias Kresin <dev@kresin.me>
208 Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org>
209 Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org>
210 Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org>
212 +++ b/include/configs/arv7506pw11.h
215 + * Copyright (C) 2016 Mathias Kresin <dev@kresin.me>
217 + * SPDX-License-Identifier: GPL-2.0+
223 +#define CONFIG_MACH_TYPE "ARV7506PW11"
224 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
225 +#define CONFIG_BOARD_NAME "Arcadyan ARV7506PW11"
228 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
230 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
232 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
234 +#define CONFIG_SYS_BOOTM_LEN 0x1000000 /* 16 MB */
236 +/* Switch devices */
237 +#define CONFIG_SWITCH_MULTI
238 +#define CONFIG_SWITCH_RTL8306
241 +#if defined(CONFIG_SYS_BOOT_BRN)
242 +#define CONFIG_SYS_TEXT_BASE 0x80002000
243 +#define CONFIG_SKIP_LOWLEVEL_INIT
244 +#define CONFIG_SYS_DISABLE_CACHE
245 +#define CONFIG_ENV_IS_NOWHERE
246 +#define CONFIG_ENV_OVERWRITE 1
247 +#elif defined(CONFIG_SYS_BOOT_NOR)
248 +#define CONFIG_ENV_IS_IN_FLASH
249 +#define CONFIG_ENV_OVERWRITE
250 +#define CONFIG_ENV_OFFSET (256 * 1024)
251 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
253 +#define CONFIG_ENV_IS_NOWHERE
256 +#define CONFIG_ENV_SIZE (64 * 1024)
258 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
261 +#define CONFIG_LTQ_ADVANCED_CONSOLE
262 +#define CONFIG_BAUDRATE 115200
263 +#define CONFIG_CONSOLE_ASC 1
264 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
266 +/* Pull in default board configs for Lantiq XWAY Danube */
267 +#include <asm/lantiq/config.h>
268 +#include <asm/arch/config.h>
270 +/* Pull in default OpenWrt configs for Lantiq SoC */
271 +#include "openwrt-lantiq-common.h"
273 +#define CONFIG_EXTRA_ENV_SETTINGS \
274 + CONFIG_ENV_LANTIQ_DEFAULTS \
275 + "kernel_addr=0xB0050000\0"
277 +#endif /* __CONFIG_H */