1 From 014f9196e18f4157232d0521f3a7502e7dbbb974 Mon Sep 17 00:00:00 2001
2 From: Alison Wang <b18965@freescale.com>
3 Date: Fri, 13 May 2016 13:28:07 +0800
4 Subject: [PATCH 02/93] armv8: SMP support for loading 32-bit OS
6 Spin-table method is used for secondary cores to load 32-bit OS. The
7 architecture information will be got through checking FIT image and
8 saved in the os_arch element of spin-table, then the secondary cores
9 will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
11 Signed-off-by: Alison Wang <alison.wang@nxp.com>
12 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
14 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 21 +++++++++++++++++++++
15 arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 ++++++++++
16 arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++++
17 arch/arm/lib/bootm.c | 5 +++++
18 4 files changed, 42 insertions(+)
20 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
21 index 9c69ed1..93f4a65 100644
22 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
23 +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
26 #include <asm/arch/mp.h>
28 +#include <asm/u-boot.h>
31 mov x29, lr /* Save LR */
32 @@ -320,6 +321,11 @@ ENTRY(secondary_boot_func)
33 gic_wait_for_interrupt_m x0, w1
37 + ldr x6, =IH_ARCH_DEFAULT
41 bl secondary_switch_to_el2
42 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
43 bl secondary_switch_to_el1
44 @@ -337,6 +343,21 @@ slave_cpu:
45 tbz x1, #25, cpu_is_le
46 rev x0, x0 /* BE to LE conversion */
50 + ldr x6, =IH_ARCH_DEFAULT
54 +#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
55 + bl secondary_switch_to_el2
57 + bl armv8_switch_to_el1_aarch32
59 + bl armv8_switch_to_el2_aarch32
63 br x0 /* branch to the given address */
64 ENDPROC(secondary_boot_func)
66 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
67 index df7ffb8..dd91550 100644
68 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
69 +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
70 @@ -22,6 +22,16 @@ phys_addr_t determine_mp_bootpg(void)
71 return (phys_addr_t)&secondary_boot_code;
74 +void update_os_arch_secondary_cores(uint8_t os_arch)
76 + u64 *table = get_spin_tbl_addr();
79 + for (i = 1; i < CONFIG_MAX_CPUS; i++)
80 + table[i * WORDS_PER_SPIN_TABLE_ENTRY +
81 + SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch;
84 int fsl_layerscape_wake_seconday_cores(void)
86 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
87 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
88 index e46e076..55f0e0c 100644
89 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h
90 +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
92 * uint64_t entry_addr;
97 * we pad this struct to 64 bytes so each entry is in its own cacheline
98 * the actual spin table is an array of these structures
100 #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0
101 #define SPIN_TABLE_ELEM_STATUS_IDX 1
102 #define SPIN_TABLE_ELEM_LPID_IDX 2
103 +#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3
104 #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */
105 #define SPIN_TABLE_ELEM_SIZE 64
107 @@ -35,4 +37,8 @@ phys_addr_t determine_mp_bootpg(void);
108 void secondary_boot_func(void);
109 int is_core_online(u64 cpu_id);
112 +#define IH_ARCH_ARM 2 /* ARM */
113 +#define IH_ARCH_ARM64 22 /* ARM64 */
115 #endif /* _FSL_LAYERSCAPE_MP_H */
116 diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
117 index 36f2cb0..aae8c5b 100644
118 --- a/arch/arm/lib/bootm.c
119 +++ b/arch/arm/lib/bootm.c
120 @@ -258,6 +258,10 @@ bool armv7_boot_nonsec(void)
124 +__weak void update_os_arch_secondary_cores(uint8_t os_arch)
129 static void boot_jump_linux(bootm_headers_t *images, int flag)
131 @@ -276,6 +280,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
132 announce_and_cleanup(fake);
135 + update_os_arch_secondary_cores(images->os.arch);
136 if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) &&
137 (images->os.arch == IH_ARCH_ARM)) {