1 From b3bbf1aeb0245a0f5565f669dd4b2f5f5be40d8a Mon Sep 17 00:00:00 2001
2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
3 Date: Wed, 16 Mar 2016 08:43:55 +0530
4 Subject: [PATCH 08/93] armv8/ls1043a: Add the OCRAM initialization
6 Clear the content to zero and the ECC error bit of OCRAM1/2.
8 The OCRAM must be initialized to ZERO by the unit of 8-Byte before
9 accessing it, or else it will generate ECC error. And the IBR has
10 accessed the OCRAM before this initialization, so the ECC error
11 status bit should to be cleared.
13 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
14 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
16 arch/arm/cpu/armv8/start.S | 39 +++++++++++++++++++++++++++++++++++++++
17 1 file changed, 39 insertions(+)
19 diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
20 index dd583c9..235213f 100644
21 --- a/arch/arm/cpu/armv8/start.S
22 +++ b/arch/arm/cpu/armv8/start.S
24 #include <asm/macro.h>
25 #include <asm/armv8/mmu.h>
27 +#define DCSR_SYS_DCFG_SBEESR2 0x20140534
28 +#define DCSR_SYS_DCFG_MBEESR2 0x20140544
30 /*************************************************************************
32 * Startup Code (reset vector)
33 @@ -215,10 +218,46 @@ WEAK(lowlevel_init)
34 #endif /* CONFIG_ARMV8_MULTIENTRY */
37 +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
40 mov lr, x29 /* Restore LR */
42 ENDPROC(lowlevel_init)
44 +#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
45 +ENTRY(fsl_ocram_init)
46 + mov x28, lr /* Save LR */
48 + bl fsl_ocram_clear_ecc_err
49 + mov lr, x28 /* Restore LR */
51 +ENDPROC(fsl_ocram_init)
53 +ENTRY(fsl_clear_ocram)
55 + ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
56 + ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
64 +ENDPROC(fsl_clear_ocram)
66 +ENTRY(fsl_ocram_clear_ecc_err)
67 + /* OCRAM1/2 ECC status bit */
69 + ldr x0, =DCSR_SYS_DCFG_SBEESR2
71 + ldr x0, =DCSR_SYS_DCFG_MBEESR2
74 +ENDPROC(fsl_ocram_init)
77 WEAK(smp_kick_all_cpus)
78 /* Kick secondary cpus up by SGI 0 interrupt */
79 mov x29, lr /* Save LR */