1 From 6bcd65ed47844e747ff6db066b092632f1760256 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 3 Mar 2021 10:51:43 +0800
4 Subject: [PATCH 08/12] board: mt7622: use new spi-nand driver
6 Enable new spi-nand driver support for mt7622_rfb_defconfig
8 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
10 arch/arm/dts/mt7622-rfb.dts | 7 +++++++
11 arch/arm/dts/mt7622.dtsi | 16 ++++++++++++++++
12 configs/mt7622_rfb_defconfig | 5 +++++
13 3 files changed, 28 insertions(+)
15 --- a/arch/arm/dts/mt7622-rfb.dts
16 +++ b/arch/arm/dts/mt7622-rfb.dts
22 + pinctrl-names = "default";
23 + pinctrl-0 = <&snfi_pins>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&uart0_pins>;
31 --- a/arch/arm/dts/mt7622.dtsi
32 +++ b/arch/arm/dts/mt7622.dtsi
37 + snand: snand@1100d000 {
38 + compatible = "mediatek,mt7622-snand";
39 + reg = <0x1100d000 0x1000>,
40 + <0x1100e000 0x1000>;
41 + reg-names = "nfi", "ecc";
42 + clocks = <&pericfg CLK_PERI_NFI_PD>,
43 + <&pericfg CLK_PERI_SNFI_PD>,
44 + <&pericfg CLK_PERI_NFIECC_PD>;
45 + clock-names = "nfi_clk", "pad_clk", "ecc_clk";
46 + assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
47 + <&topckgen CLK_TOP_NFI_INFRA_SEL>;
48 + assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
49 + <&topckgen CLK_TOP_UNIVPLL2_D8>;
50 + status = "disabled";
54 compatible = "mediatek,mtk-snor";
55 reg = <0x11014000 0x1000>;
56 --- a/configs/mt7622_rfb_defconfig
57 +++ b/configs/mt7622_rfb_defconfig
58 @@ -15,6 +15,7 @@ CONFIG_LOG=y
59 CONFIG_SYS_PROMPT="MT7622> "
66 @@ -27,6 +28,10 @@ CONFIG_SYSCON=y
68 CONFIG_MMC_HS200_SUPPORT=y
72 +CONFIG_MTK_SPI_NAND=y
73 +CONFIG_MTK_SPI_NAND_MTD=y
75 CONFIG_SPI_FLASH_EON=y
76 CONFIG_SPI_FLASH_GIGADEVICE=y